Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
| Date         : Sun Sep 13 18:09:49 2026
| Host         : DESKTOP-8JFH0O2 running 64-bit major release  (build 9200)
| Command      : report_cdc -details -return_string
| Design       : fm_top
| Device       : 7z010-clg400
| Speed File   : -2  PRODUCTION 1.12 2019-11-22
| Design State : Synthesized
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CDC Report

ID     Severity  Count  Description
-----  --------  -----  -------------------------------------------------------
CDC-3  Info          2  1-bit synchronized with ASYNC_REG property
CDC-9  Info          2  Asynchronous reset synchronized with ASYNC_REG property

Source Clock: clk_out2_clk_global
Destination Clock: clk_out1_clk_global
CDC Type: Safely Timed

Row  ID     Severity  Description                                              Depth  Exception   Source (From)                                                                                                         Destination (To)
---  -----  --------  -------------------------------------------------------  -----  ----------  --------------------------------------------------------------------------------------------------------------------  -----------------------------------------------------------------------------------------------------------------------------------
  1  CDC-3  Info      1-bit synchronized with ASYNC_REG property                   3  False Path  core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C  core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  2  CDC-9  Info      Asynchronous reset synchronized with ASYNC_REG property      4  False Path  resets/released_reg/C                                                                                                 resets/axis_sync/arststages_ff_reg[0]/CLR

Source Clock: clk_out1_clk_global
Destination Clock: clk_out2_clk_global
CDC Type: Safely Timed

Row  ID     Severity  Description                                 Depth  Exception   Source (From)                                                                                                         Destination (To)
---  -----  --------  ------------------------------------------  -----  ----------  --------------------------------------------------------------------------------------------------------------------  -----------------------------------------------------------------------------------------------------------------------------------
  1  CDC-3  Info      1-bit synchronized with ASYNC_REG property      3  False Path  core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C  core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D

Source Clock: input port clock
Destination Clock: clk_out2_clk_global
CDC Type: No Common Primary Clock

Row  ID     Severity  Description                                              Depth  Exception   Source (From)  Destination (To)
---  -----  --------  -------------------------------------------------------  -----  ----------  -------------  -----------------------------------------
  1  CDC-9  Info      Asynchronous reset synchronized with ASYNC_REG property      4  False Path  rst_n          resets/lock_sync/arststages_ff_reg[0]/CLR
