# Coverage exceptions for this ISA.
# Format: mnemonic_pattern | incomplete_axes | justification
#
# Axes: a=decode, b=addr_calc, c=mfma/wmma, d=execute, e=wavefront_ctx,
#        f=pc_manipulation, g=waitcnt, h=coherency
#
# The instruction execution harness (Phase E) tests scalar ALU instructions
# with synthesized encodings. Vector and memory instructions are tested via
# end-to-end kernel simulation tests (VectorAdd, Matmul, HIP tests).

# --- Vector instructions (require valid VGPR state) ---
v_*                    | d          | Tested via kernel simulation, not harness

# --- Memory instructions (require valid addresses) ---
s_load_*               | d,g,h      | Tested via kernel simulation
s_store_*              | d,g,h      | Tested via kernel simulation
s_buffer_*             | d,g,h      | Tested via kernel simulation
s_atomic_*             | d,g,h      | Tested via kernel simulation
buffer_*               | d,g,h      | Tested via kernel simulation
tbuffer_*              | d,g,h      | Tested via kernel simulation
flat_*                 | d,g,h      | Tested via kernel simulation
global_*               | d,g,h      | Tested via kernel simulation
scratch_*              | d,g,h      | Tested via kernel simulation
ds_*                   | d,g        | Tested via kernel simulation

# --- Image instructions (placeholder execute bodies) ---
image_*                | d          | Image sampling/query not simulated

# --- DPP/SDWA (skipped in codegen) ---
*_dpp                  | a,d        | DPP modifier encoding not generated
*_sdwa                 | a,d        | SDWA modifier encoding not generated

# --- VOPD (dual-issue, not decoded) ---
*_vopdxy               | a,d        | VOPD dual-issue not supported
