# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
# SPDX-License-Identifier: Apache-2.0

config SOC_FAMILY_RENESAS_RA
	select SOC_RESET_HOOK
	select SOC_EARLY_INIT_HOOK
	select SOC_LATE_INIT_HOOK
	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE

if SOC_FAMILY_RENESAS_RA

config SERIES_SPECIFIC_SOC_INIT
	bool "Use series specific initialize"

config OUTPUT_RPD
	bool "Build a Renesas Partition Data in rpd format"
	depends on CPU_HAS_RENESAS_RA_IDAU
	help
	  Build a partition data zephyr/zephyr.rpd in the build directory.
	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.

config CPU_HAS_RENESAS_RA_IDAU
	bool
	select CPU_HAS_TEE
	help
	  MCU implements the ARM Implementation-Defined Attribution Unit (IDAU).

rsource "*/Kconfig"

config SOC_RA_ENABLE_START_SECOND_CORE
	bool "Allows the primary core to start the secondary core"
	depends on ((RENESAS_PN_NUMBER_OF_CORES = 2) && CPU_CORTEX_M85)
	help
	  Indicates the second core will be start in the soc_late_init_hook when enabled

config SOC_RA_SECOND_CORE_BUILD
	bool "Indicates the image is built for the secondary core"
	help
	  Indicates the image is built for the secondary core when enabled

config RENESAS_RA_BATTERY_BACKUP_MANUAL_CONFIGURE
	bool "VBAT switching manual"
	default y
	depends on DT_HAS_RENESAS_RA_BATTERY_BACKUP_ENABLED && $(dt_compat_any_has_prop,$(DT_COMPAT_RENESAS_RA_BATTERY_BACKUP),manual-configure)
	help
	  Enable if this SoC's battery backup domain allows switching to VBAT manually.
	  Leave disabled if switching is automatic.

if CPU_HAS_DCACHE

config CPU_RA_HAS_DCACHE_WRITETHROUGH
	bool
	help
	  Indicates that the SoC supports forcing the data cache to operate in write-through mode.

choice CPU_RA_DCACHE_WRITE_POLICY
	bool "Renesas RA data cache write policy"
	default CPU_RA_DCACHE_FORCE_WRITETHROUGH
	help
	  Select the DCACHE write policy.

config CPU_RA_DCACHE_FORCE_WRITETHROUGH
	bool "Force data cache to be write-through"
	depends on CPU_RA_HAS_DCACHE_WRITETHROUGH
	help
	  Force the data cache to operate in write-through mode. This may be necessary for some
	  SoCs to ensure proper operation of peripherals that directly access memory.

config CPU_RA_DCACHE_WRITEBACK
	bool "Allow data cache to operate in write-back mode"
	help
	  Allow the data cache to operate in write-back mode, which may improve performance but
	  requires proper cache management to ensure data consistency.

endchoice # CPU_RA_DCACHE_WRITE_POLICY

endif # CPU_HAS_DCACHE

# Promptless (non-user) config options

config SOC_RA_DYNAMIC_INTERRUPT_NUMBER
	bool
	help
	  Indicates that the interrupt numbers are not fixed and can be assigned dynamically
	  when the SoC selects this configuration

endif # SOC_FAMILY_RENESAS_RA
