arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	total_power	routing_power_perc	clock_power_perc	tile_power_perc	
k6_frac_N10_mem32K_40nm.xml	ch_intrinsics.v	common	2.50	vpr	67.07 MiB		0.04	9216	-1	-1	3	0.22	-1	-1	33384	-1	52224	68	99	1	0	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	68680	99	130	363	493	1	251	298	12	12	144	clb	auto	27.9 MiB	0.08	2086.98	833	72933	20806	43322	8805	67.1 MiB	0.14	0.00	2.81842	2.05868	-218.035	-2.05868	2.05868	0.10	0.00056371	0.000524631	0.0466752	0.0434927	-1	-1	-1	-1	40	1417	9	5.66058e+06	4.21279e+06	333335.	2314.82	0.67	0.239433	0.217959	12666	64609	-1	1317	9	506	676	37595	13839	2.5573	2.5573	-230.905	-2.5573	0	0	419432.	2912.72	0.01	0.04	0.05	-1	-1	0.01	0.0231087	0.0218261	0.008686	0.1989	0.06808	0.733	
k6_frac_N10_mem32K_40nm.xml	diffeq1.v	common	7.03	vpr	71.54 MiB		0.04	9216	-1	-1	15	0.30	-1	-1	34688	-1	54116	39	162	0	5	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	73260	162	96	999	932	1	692	302	16	16	256	mult_36	auto	31.8 MiB	0.25	9298.09	5644	61022	15647	45087	288	71.5 MiB	0.33	0.01	25.0935	21.4097	-1818.6	-21.4097	21.4097	0.21	0.00219731	0.00202289	0.142407	0.133486	-1	-1	-1	-1	48	10837	24	1.21132e+07	4.08187e+06	756778.	2956.16	3.12	0.856819	0.797376	25228	149258	-1	9642	22	3071	6112	861906	245213	23.0275	23.0275	-1946.13	-23.0275	0	0	968034.	3781.38	0.03	0.26	0.10	-1	-1	0.03	0.117615	0.111417	0.007718	0.3481	0.01643	0.6355	
