arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	routed_wirelength	avg_routed_wirelength	routed_wiresegment	avg_routed_wiresegment	total_nets_routed	total_connections_routed	total_heap_pushes	total_heap_pops	logic_block_area_total	logic_block_area_used	routing_area_total	routing_area_per_tile	crit_path_route_success_iteration	num_rr_graph_nodes	num_rr_graph_edges	collapsed_nodes	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	create_rr_graph_time	create_intra_cluster_rr_graph_time	adding_internal_edges	route_mem	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	router_lookahead_mem	tile_lookahead_computation_time	router_lookahead_computation_time	
hard_fpu_arch_timing.xml	mm3.v	common	1.21	vpr	63.49 MiB		0.02	6528	-1	-1	1	0.03	-1	-1	30068	-1	-1	0	193	-1	-1	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	65012	193	32	545	422	1	289	227	21	21	441	io	auto	24.3 MiB	0.44	4898	3702	43823	17714	25682	427	63.5 MiB	0.13	0.00	2.985	2.985	-825.053	-2.985	2.985	0.00	0.0010349	0.000962829	0.068971	0.0643542	-1	-1	-1	-1	4668	16.2083	1227	4.26042	421	421	167123	44673	809148	68766.3	979092.	2220.16	4	24050	197379	-1	2.985	2.985	-815.455	-2.985	-21.8252	-0.0851	0.16	-1	-1	63.5 MiB	0.04	0.0870625	0.081579	63.5 MiB	-1	0.04	
