arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
shorted_flyover_wires.xml	raygentop.v	common	12.55	vpr	87.02 MiB		0.26	31488	-1	-1	3	0.92	-1	-1	39900	-1	-1	123	214	0	8	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	89104	214	305	2963	2869	1	1441	650	19	19	361	io clb	auto	47.0 MiB	2.47	24907.5	12322	234212	77309	149582	7321	87.0 MiB	1.18	0.02	5.20445	4.39044	-2709.58	-4.39044	4.39044	0.26	0.0045718	0.004154	0.458995	0.421114	-1	-1	-1	-1	62	26901	39	1.65001e+07	9.79696e+06	1.07728e+06	2984.15	4.37	1.60589	1.47902	35161	217957	-1	22066	14	5733	13948	1621510	447945	5.5	5.5	-3060.5	-5.5	0	0	1.33769e+06	3705.50	0.05	0.51	0.17	-1	-1	0.05	0.222763	0.211018	
buffered_flyover_wires.xml	raygentop.v	common	13.86	vpr	86.36 MiB		0.31	31104	-1	-1	3	0.90	-1	-1	39900	-1	-1	123	214	0	8	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	88432	214	305	2963	2869	1	1441	650	19	19	361	io clb	auto	46.7 MiB	2.57	24403.5	11315	231398	74532	151010	5856	86.4 MiB	1.18	0.02	6.11069	4.66004	-2796.88	-4.66004	4.66004	0.26	0.00558569	0.00523781	0.43992	0.40459	-1	-1	-1	-1	60	26125	41	1.65001e+07	9.79696e+06	1.07648e+06	2981.95	5.41	1.89272	1.74429	34801	210837	-1	20782	19	6589	16161	2052508	564833	4.75371	4.75371	-3043.13	-4.75371	0	0	1.35858e+06	3763.38	0.04	0.64	0.15	-1	-1	0.04	0.27685	0.261099	
