arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
7series_BRAM_DSP_carry.xml	stereovision3.v	common	3.18	vpr	74.55 MiB		-1	-1	0.21	31924	4	0.07	-1	-1	36540	-1	-1	-1	11	0	-1	success	v8.0.0-14857-g1880999910-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-5.15.0-119-generic x86_64	2025-12-27T09:05:28	goeders10	/home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks	76344	11	2	305	285	2	111	34	7	7	49	CLB	auto	35.0 MiB	1.44	540.712	407	3334	1001	1646	687	74.6 MiB	0.04	0.00	3.27166	3.27166	-180.771	-3.27166	3.206	0.11	0.000282651	0.000253225	0.0197949	0.0176086	-1	-1	-1	-1	46	458	13	1.34735e+06	1.13177e+06	196131.	4002.68	0.72	0.0733911	0.0637213	6872	100829	-1	373	10	297	1066	134374	64223	3.59075	3.10115	-222.561	-3.59075	-2.342	-0.04	273579.	5583.25	0.03	0.02	0.05	-1	-1	0.03	0.0114024	0.0105351	
7series_BRAM_DSP_carry.xml	diffeq2.v	common	31.75	vpr	133.50 MiB		-1	-1	0.14	33428	5	0.08	-1	-1	38748	-1	-1	-1	66	0	-1	success	v8.0.0-14857-g1880999910-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-5.15.0-119-generic x86_64	2025-12-27T09:05:28	goeders10	/home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks	136708	66	96	1817	1078	1	1146	337	26	26	676	DSP	auto	42.3 MiB	2.54	20173	8967	121053	44342	64617	12094	127.5 MiB	1.13	0.01	22.2113	19.941	-1076.44	-19.941	19.941	3.14	0.00132403	0.00123609	0.14602	0.134802	-1	-1	-1	-1	66	11691	24	3.53732e+07	1.31946e+07	5.28660e+06	7820.41	17.27	0.55046	0.50229	131110	3085689	-1	10525	13	4779	8508	2934069	701503	21.0887	21.0887	-1281.35	-21.0887	-1.7	-0.034	7.09031e+06	10488.6	1.78	0.35	1.32	-1	-1	1.78	0.0497438	0.0465201	
