 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 k6_N10_mem32K_40nm.xml	  multiclock.blif	  common_-sdc_file_sdc/samples/A.sdc	  0.24	  vpr	  68.93 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  5	  0	  0	  success	  v8.0.0-15524-gc54b14007f-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.14.0-33-generic x86_64	  2026-04-08T13:51:14	  alex-ThinkPad-X1-Carbon-Gen-9	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc	  70584	  5	  3	  11	  14	  2	  9	  10	  4	  4	  16	  clb	  auto	  30.2 MiB	  0.00	  22	  20	  810	  394	  244	  172	  68.9 MiB	  0.01	  0.00	  0.814658	  0.814658	  -2.77132	  -0.814658	  0.571	  0.01	  2.2513e-05	  1.8363e-05	  0.00244241	  0.00192556	  -1	  -1	  -1	  -1	  8	  11	  2	  107788	  107788	  4794.78	  299.674	  0.01	  0.0055991	  0.00452299	  564	  862	  -1	  18	  4	  13	  13	  372	  218	  0.739641	  0.571	  -2.62128	  -0.739641	  0	  0	  5401.54	  337.596	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00076432	  0.000700843	 
 k6_N10_mem32K_40nm.xml	  multiclock.blif	  common_-sdc_file_sdc/samples/B.sdc	  0.24	  vpr	  68.95 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  5	  0	  0	  success	  v8.0.0-15524-gc54b14007f-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.14.0-33-generic x86_64	  2026-04-08T13:51:14	  alex-ThinkPad-X1-Carbon-Gen-9	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc	  70604	  5	  3	  11	  14	  2	  9	  10	  4	  4	  16	  clb	  auto	  30.1 MiB	  0.00	  22	  20	  870	  405	  235	  230	  68.9 MiB	  0.01	  0.00	  0.571	  0.571	  0	  0	  0.571	  0.01	  2.8531e-05	  2.361e-05	  0.00230183	  0.00189839	  -1	  -1	  -1	  -1	  8	  17	  4	  107788	  107788	  4794.78	  299.674	  0.01	  0.00537077	  0.00444801	  564	  862	  -1	  17	  4	  12	  12	  252	  131	  0.571	  0.571	  0	  0	  0	  0	  5401.54	  337.596	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.000884836	  0.000825175	 
 k6_N10_mem32K_40nm.xml	  multiclock.blif	  common_-sdc_file_sdc/samples/C.sdc	  0.22	  vpr	  69.32 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  5	  0	  0	  success	  v8.0.0-15524-gc54b14007f-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.14.0-33-generic x86_64	  2026-04-08T13:51:14	  alex-ThinkPad-X1-Carbon-Gen-9	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc	  70980	  5	  3	  11	  14	  2	  9	  10	  4	  4	  16	  clb	  auto	  30.4 MiB	  0.00	  22	  21	  620	  285	  243	  92	  69.3 MiB	  0.00	  0.00	  0.646297	  0.645978	  -2.18969	  -0.645978	  0.571	  0.01	  2.8927e-05	  2.117e-05	  0.00151322	  0.00113836	  -1	  -1	  -1	  -1	  6	  21	  8	  107788	  107788	  3417.33	  213.583	  0.01	  0.00253522	  0.00201709	  552	  802	  -1	  20	  8	  24	  24	  508	  283	  0.59309	  0.571	  -2.01015	  -0.59309	  0	  0	  4794.78	  299.674	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.0013267	  0.00120733	 
 k6_N10_mem32K_40nm.xml	  multiclock.blif	  common_-sdc_file_sdc/samples/D.sdc	  0.22	  vpr	  69.23 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  5	  0	  0	  success	  v8.0.0-15524-gc54b14007f-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.14.0-33-generic x86_64	  2026-04-08T13:51:14	  alex-ThinkPad-X1-Carbon-Gen-9	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc	  70888	  5	  3	  11	  14	  2	  9	  10	  4	  4	  16	  clb	  auto	  30.2 MiB	  0.00	  22	  20	  740	  332	  288	  120	  69.2 MiB	  0.00	  0.00	  1.64604	  1.64598	  -5.31901	  -1.64598	  0.571	  0.00	  1.7558e-05	  1.3049e-05	  0.00135864	  0.00101115	  -1	  -1	  -1	  -1	  8	  19	  2	  107788	  107788	  4794.78	  299.674	  0.01	  0.00341811	  0.00261767	  564	  862	  -1	  29	  9	  35	  35	  1639	  1127	  1.57153	  0.571	  -5.57057	  -1.57153	  0	  0	  5401.54	  337.596	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.0015363	  0.00137492	 
 k6_N10_mem32K_40nm.xml	  multiclock.blif	  common_-sdc_file_sdc/samples/E.sdc	  0.21	  vpr	  68.55 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  5	  0	  0	  success	  v8.0.0-15524-gc54b14007f-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.14.0-33-generic x86_64	  2026-04-08T13:51:14	  alex-ThinkPad-X1-Carbon-Gen-9	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc	  70200	  5	  3	  11	  14	  2	  9	  10	  4	  4	  16	  clb	  auto	  29.7 MiB	  0.00	  22	  20	  200	  38	  110	  52	  68.6 MiB	  0.00	  0.00	  1.44967	  1.44871	  -2.90935	  -1.44871	  0.571	  0.01	  3.9391e-05	  3.2145e-05	  0.000846346	  0.000677721	  -1	  -1	  -1	  -1	  6	  26	  6	  107788	  107788	  3417.33	  213.583	  0.01	  0.00194939	  0.00162896	  552	  802	  -1	  15	  20	  48	  48	  1206	  797	  1.56638	  0.571	  -2.99759	  -1.56638	  0	  0	  4794.78	  299.674	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00203941	  0.0016942	 
 k6_N10_mem32K_40nm.xml	  multiclock.blif	  common_-sdc_file_sdc/samples/F.sdc	  0.16	  vpr	  69.23 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  5	  0	  0	  success	  v8.0.0-15524-gc54b14007f-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.14.0-33-generic x86_64	  2026-04-08T13:51:14	  alex-ThinkPad-X1-Carbon-Gen-9	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc	  70892	  5	  3	  11	  14	  2	  9	  10	  4	  4	  16	  clb	  auto	  30.5 MiB	  0.00	  22	  20	  530	  219	  169	  142	  69.2 MiB	  0.00	  0.00	  0.146298	  0.145978	  0	  0	  0.571	  0.01	  1.2908e-05	  1.0442e-05	  0.00110155	  0.000880865	  -1	  -1	  -1	  -1	  6	  20	  4	  107788	  107788	  3417.33	  213.583	  0.00	  0.00192893	  0.00162631	  552	  802	  -1	  17	  2	  11	  11	  260	  139	  0.0715255	  0.571	  0	  0	  0	  0	  4794.78	  299.674	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00075435	  0.000708582	 
 k6_N10_mem32K_40nm.xml	  multiclock.blif	  common_-sdc_file_sdc/samples/create_clock/sink_pin_targets.sdc	  0.17	  vpr	  68.33 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  5	  0	  0	  success	  v8.0.0-15524-gc54b14007f-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.14.0-33-generic x86_64	  2026-04-08T13:51:14	  alex-ThinkPad-X1-Carbon-Gen-9	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc	  69968	  5	  3	  11	  14	  2	  9	  10	  4	  4	  16	  clb	  auto	  29.6 MiB	  0.00	  22	  20	  870	  405	  235	  230	  68.3 MiB	  0.00	  0.00	  0.814658	  0.814658	  0	  0	  0.570999	  0.01	  1.5855e-05	  1.3108e-05	  0.00156429	  0.00125665	  -1	  -1	  -1	  -1	  8	  17	  4	  107788	  107788	  4794.78	  299.674	  0.01	  0.00410006	  0.00326283	  564	  862	  -1	  17	  4	  12	  12	  248	  131	  0.757297	  0.570999	  0	  0	  0	  0	  5401.54	  337.596	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00070429	  0.000652111	 
 k6_N10_mem32K_40nm.xml	  multiclock.blif	  common_-sdc_file_sdc/samples/create_clock/sink_pin_targets_2.sdc	  0.20	  vpr	  68.24 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  5	  0	  0	  success	  v8.0.0-15524-gc54b14007f-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.14.0-33-generic x86_64	  2026-04-08T13:51:14	  alex-ThinkPad-X1-Carbon-Gen-9	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc	  69876	  5	  3	  11	  14	  2	  9	  10	  4	  4	  16	  clb	  auto	  29.5 MiB	  0.00	  22	  20	  870	  405	  235	  230	  68.2 MiB	  0.00	  0.00	  0.814658	  0.814658	  0	  0	  0.570999	  0.01	  1.5618e-05	  1.2894e-05	  0.00169567	  0.00139845	  -1	  -1	  -1	  -1	  8	  17	  4	  107788	  107788	  4794.78	  299.674	  0.01	  0.00395761	  0.00318921	  564	  862	  -1	  17	  4	  12	  12	  248	  131	  0.757297	  0.570999	  0	  0	  0	  0	  5401.54	  337.596	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00154887	  0.00143508	 
