arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_global_nets	num_routed_nets	
timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml	verilog/multiclock_output_and_latch.v	common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	1.94	vpr	65.54 MiB		-1	-1	0.06	19920	1	0.04	-1	-1	31668	-1	-1	2	6	0	0	success	v8.0.0-14178-g4818739e3-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-71-generic x86_64	2025-10-15T12:13:40	betzgrp-wintermute	/home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow	67116	6	1	16	17	2	10	9	17	17	289	-1	auto	26.9 MiB	0.01	118	30	360	97	253	10	65.5 MiB	0.00	0.00	2.15593	1.39165	-4.15326	-1.39165	0.805	0.25	2.1003e-05	1.6736e-05	0.00116047	0.000912615	-1	-1	-1	-1	26	103	2	1.34605e+07	107788	535376.	1852.51	0.54	0.00754728	0.00590795	25250	102406	-1	94	2	13	13	8389	4709	2.36808	0.805	-5.23212	-2.36808	-1.24266	-0.621885	656571.	2271.87	0.02	0.10	0.06	-1	-1	0.02	0.00129463	0.00122734	1	9	
timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml	verilog/and_latch.v	common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	1.02	vpr	65.45 MiB		-1	-1	0.06	19916	1	0.02	-1	-1	29416	-1	-1	1	3	0	0	success	v8.0.0-14178-g4818739e3-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-71-generic x86_64	2025-10-15T12:13:40	betzgrp-wintermute	/home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow	67020	3	1	5	6	1	4	5	13	13	169	-1	auto	27.2 MiB	0.00	38	14	116	17	99	0	65.4 MiB	0.00	0.00	1.29226	0.764009	-1.29997	-0.764009	0.764009	0.13	9.616e-06	6.36e-06	0.000369143	0.000250838	-1	-1	-1	-1	20	41	1	6.63067e+06	53894	227243.	1344.63	0.11	0.00149772	0.00130761	13251	44387	-1	41	1	4	4	2063	1083	1.62142	1.62142	-1.62142	-1.62142	-0.542974	-0.542974	294987.	1745.49	0.01	0.05	0.03	-1	-1	0.01	0.00103006	0.000997599	0	4	
timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml	verilog/multiclock_output_and_latch.v	common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	1.98	vpr	65.82 MiB		-1	-1	0.07	19652	1	0.04	-1	-1	31668	-1	-1	2	6	0	0	success	v8.0.0-14178-g4818739e3-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-71-generic x86_64	2025-10-15T12:13:40	betzgrp-wintermute	/home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow	67404	6	1	16	17	2	10	9	17	17	289	-1	auto	27.2 MiB	0.01	118	30	351	97	247	7	65.8 MiB	0.00	0.00	2.15759	1.39165	-4.15382	-1.39165	0.805	0.25	2.089e-05	1.6651e-05	0.00107174	0.000831921	-1	-1	-1	-1	26	103	2	1.34605e+07	107788	547923.	1895.93	0.55	0.00782104	0.00609381	25250	106300	-1	103	4	17	17	12886	7176	2.68631	0.805	-5.86194	-2.68631	-1.24377	-0.622992	673298.	2329.75	0.02	0.10	0.07	-1	-1	0.02	0.00141076	0.00131948	1	9	
timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml	verilog/and_latch.v	common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	1.00	vpr	65.82 MiB		-1	-1	0.06	19652	1	0.02	-1	-1	29572	-1	-1	1	3	0	0	success	v8.0.0-14178-g4818739e3-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-71-generic x86_64	2025-10-15T12:13:40	betzgrp-wintermute	/home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow	67404	3	1	5	6	1	4	5	13	13	169	-1	auto	27.1 MiB	0.00	38	14	116	17	99	0	65.8 MiB	0.00	0.00	1.29226	0.764009	-1.29997	-0.764009	0.764009	0.13	9.685e-06	6.379e-06	0.000366524	0.000251655	-1	-1	-1	-1	20	41	1	6.63067e+06	53894	235789.	1395.20	0.10	0.00144377	0.0012637	13251	46155	-1	50	1	4	4	2211	1137	1.93995	1.93995	-1.93995	-1.93995	-0.544081	-0.544081	303533.	1796.05	0.01	0.05	0.03	-1	-1	0.01	0.00106621	0.00102911	0	4	
timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml	verilog/multiclock_output_and_latch.v	common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	1.92	vpr	65.76 MiB		-1	-1	0.07	19652	1	0.04	-1	-1	31644	-1	-1	2	6	0	0	success	v8.0.0-14178-g4818739e3-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-71-generic x86_64	2025-10-15T12:13:40	betzgrp-wintermute	/home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow	67340	6	1	16	17	2	10	9	17	17	289	-1	auto	27.2 MiB	0.01	118	30	360	97	253	10	65.8 MiB	0.00	0.00	2.15593	1.39165	-4.15326	-1.39165	0.805	0.24	2.2515e-05	1.8288e-05	0.00112145	0.000876733	-1	-1	-1	-1	26	581	2	1.34605e+07	107788	532630.	1843.01	0.53	0.00720391	0.00558625	25250	102506	-1	572	2	13	13	9421	5720	3.3102	0.805	-7.11635	-3.3102	-3.12689	-1.564	653825.	2262.37	0.02	0.10	0.06	-1	-1	0.02	0.00140214	0.00132827	1	9	
timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml	verilog/and_latch.v	common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network	0.99	vpr	65.82 MiB		-1	-1	0.06	19656	1	0.02	-1	-1	29324	-1	-1	1	3	0	0	success	v8.0.0-14178-g4818739e3-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-71-generic x86_64	2025-10-15T12:13:40	betzgrp-wintermute	/home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow	67404	3	1	5	6	1	4	5	13	13	169	-1	auto	27.1 MiB	0.00	38	14	116	17	99	0	65.8 MiB	0.00	0.00	1.29226	0.764009	-1.29997	-0.764009	0.764009	0.13	1.0048e-05	6.686e-06	0.000365845	0.000251046	-1	-1	-1	-1	20	172	1	6.63067e+06	53894	225153.	1332.26	0.10	0.0014209	0.00124837	13251	44463	-1	172	1	4	4	874	302	2.20504	2.20504	-2.20504	-2.20504	-1.12659	-1.12659	292904.	1733.16	0.01	0.04	0.03	-1	-1	0.01	0.00106969	0.00103514	0	4	
