arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	total_power	routing_power_perc	clock_power_perc	tile_power_perc	
k6_frac_N10_mem32K_40nm.xml	ch_intrinsics.v	common	2.13	vpr	67.64 MiB		-1	-1	0.19	21292	3	0.07	-1	-1	32744	-1	52608	68	99	1	0	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	69268	99	130	344	474	1	227	298	12	12	144	clb	auto	27.9 MiB	0.11	1668.56	665	69948	18463	40736	10749	67.6 MiB	0.13	0.00	2.39772	1.84453	-121.764	-1.84453	1.84453	0.11	0.000590133	0.000550581	0.0447134	0.0416506	-1	-1	-1	-1	38	1340	9	5.66058e+06	4.21279e+06	319130.	2216.18	0.29	0.123165	0.112881	12522	62564	-1	1231	11	468	704	35867	11125	2.02209	2.02209	-137.314	-2.02209	-0.587246	-0.200829	406292.	2821.48	0.01	0.03	0.09	-1	-1	0.01	0.0196096	0.0183457	0.01099	0.2177	0.06598	0.7163	
k6_frac_N10_mem32K_40nm.xml	diffeq1.v	common	7.31	vpr	70.69 MiB		-1	-1	0.23	25508	15	0.28	-1	-1	33568	-1	54332	37	162	0	5	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	72388	162	96	998	939	1	692	300	16	16	256	mult_36	auto	30.9 MiB	0.21	9191.96	5363	60480	16806	43450	224	70.7 MiB	0.31	0.01	23.0432	20.7858	-1618.3	-20.7858	20.7858	0.22	0.00189667	0.00176782	0.126969	0.118374	-1	-1	-1	-1	44	11925	32	1.21132e+07	3.97408e+06	694168.	2711.59	3.40	0.722689	0.668476	24716	140770	-1	9459	19	2979	5990	814291	231327	22.2973	22.2973	-1770.76	-22.2973	0	0	904549.	3533.39	0.03	0.23	0.10	-1	-1	0.03	0.0997883	0.09394	0.007738	0.3442	0.01625	0.6396	
