arch	circuit	noc_flow	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	NoC_agg_bandwidth	NoC_latency	NoC_n_met_latency_constraints	NoC_latency_overrun	NoC_congested_bw	NoC_congestion_ratio	NoC_n_congested_links	SAT_agg_bandwidth	SAT_latency	SAT_n_met_latency_constraints	SAT_latency_overrun	SAT_congested_bw	SAT_congestion_ratio	SAT_n_congested_links	
stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml	complex_2_noc_1D_chain.blif	complex_2_noc_1D_chain.flows	common	48.31	vpr	1.07 GiB		-1	2	-1	-1	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	1124852	2	32	2204	1661	1	1104	108	36	20	720	-1	EP4SGX110	955.1 MiB	2.49	15097	6528	12701	2873	9277	551	1098.5 MiB	0.50	0.01	8.01944	7.321	-4773.2	-7.321	7.321	7.18	0.00304234	0.00264121	0.187393	0.163887	154	9039	13	0	0	6.94291e+06	9642.93	10.59	1.27047	1.12481	176404	1494154	-1	8797	13	2508	4935	954400	247839	7.47679	7.47679	-5061.93	-7.47679	0	0	8.91809e+06	12386.2	0.61	0.39	1.74	-1	-1	0.61	0.187704	0.174816	400000	3e-09	1	4.1359e-25	0	0	0 	-1	-1	-1	-1	-1	-1	-1	
