 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 EArch.xml	  diffeq2.v	  common_--cluster_seed_type_blend	  8.07	  vpr	  71.94 MiB	  	  -1	  -1	  0.20	  31548	  4	  0.10	  -1	  -1	  37540	  -1	  -1	  22	  66	  0	  5	  success	  v8.0.0-14013-ge1496c441d	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-63-generic x86_64	  2025-10-06T15:12:57	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong	  73664	  66	  96	  778	  595	  1	  467	  189	  16	  16	  256	  mult_36	  auto	  32.7 MiB	  0.28	  6722.15	  3855	  63603	  30270	  32720	  613	  71.9 MiB	  0.54	  0.01	  13.5168	  11.8115	  -731.759	  -11.8115	  11.8115	  0.34	  0.0015838	  0.00142881	  0.189035	  0.169355	  -1	  -1	  -1	  -1	  54	  8913	  24	  1.21132e+07	  3.16567e+06	  903890.	  3530.82	  5.05	  0.762472	  0.688551	  28908	  188420	  -1	  7917	  21	  3895	  8403	  1514469	  426032	  13.1113	  13.1113	  -856.802	  -13.1113	  0	  0	  1.17254e+06	  4580.24	  0.05	  0.35	  0.18	  -1	  -1	  0.05	  0.0837341	  0.0771874	 
 EArch.xml	  diffeq2.v	  common_--cluster_seed_type_timing	  9.87	  vpr	  71.59 MiB	  	  -1	  -1	  0.16	  31552	  4	  0.15	  -1	  -1	  37264	  -1	  -1	  22	  66	  0	  5	  success	  v8.0.0-14013-ge1496c441d	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-63-generic x86_64	  2025-10-06T15:12:57	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong	  73304	  66	  96	  778	  595	  1	  467	  189	  16	  16	  256	  mult_36	  auto	  32.5 MiB	  0.27	  6551.83	  3904	  63603	  31409	  31601	  593	  71.6 MiB	  0.61	  0.01	  12.92	  12.0365	  -737.339	  -12.0365	  12.0365	  0.37	  0.00162625	  0.00147101	  0.215151	  0.193092	  -1	  -1	  -1	  -1	  50	  10262	  48	  1.21132e+07	  3.16567e+06	  843554.	  3295.13	  6.63	  0.938708	  0.849562	  28144	  172338	  -1	  8195	  33	  4664	  9420	  1629662	  473055	  13.4994	  13.4994	  -864.126	  -13.4994	  0	  0	  1.08719e+06	  4246.82	  0.05	  0.41	  0.16	  -1	  -1	  0.05	  0.114475	  0.10514	 
 EArch.xml	  diffeq2.v	  common_--cluster_seed_type_max_inputs	  8.85	  vpr	  71.66 MiB	  	  -1	  -1	  0.20	  31548	  4	  0.10	  -1	  -1	  37400	  -1	  -1	  22	  66	  0	  5	  success	  v8.0.0-14013-ge1496c441d	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-63-generic x86_64	  2025-10-06T15:12:57	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong	  73380	  66	  96	  778	  595	  1	  464	  189	  16	  16	  256	  mult_36	  auto	  32.4 MiB	  0.39	  6680.33	  3675	  61977	  28764	  32440	  773	  71.7 MiB	  0.51	  0.01	  13.2078	  12.0862	  -739.95	  -12.0862	  12.0862	  0.33	  0.00166237	  0.00151104	  0.188912	  0.169672	  -1	  -1	  -1	  -1	  52	  9408	  28	  1.21132e+07	  3.16567e+06	  870783.	  3401.49	  5.76	  0.645028	  0.586431	  28652	  182587	  -1	  7769	  20	  2996	  5953	  1014691	  299790	  12.9839	  12.9839	  -840.047	  -12.9839	  0	  0	  1.14646e+06	  4478.35	  0.07	  0.27	  0.22	  -1	  -1	  0.07	  0.0854521	  0.07925	 
 EArch.xml	  diffeq2.v	  common_--cluster_seed_type_max_pins	  7.43	  vpr	  71.88 MiB	  	  -1	  -1	  0.17	  31680	  4	  0.10	  -1	  -1	  37652	  -1	  -1	  22	  66	  0	  5	  success	  v8.0.0-14013-ge1496c441d	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-63-generic x86_64	  2025-10-06T15:12:57	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong	  73600	  66	  96	  778	  595	  1	  464	  189	  16	  16	  256	  mult_36	  auto	  32.7 MiB	  0.34	  6732.23	  4026	  59809	  29376	  29931	  502	  71.9 MiB	  0.54	  0.01	  13.2056	  11.7679	  -727.861	  -11.7679	  11.7679	  0.33	  0.00150878	  0.0013486	  0.195454	  0.175407	  -1	  -1	  -1	  -1	  52	  9475	  24	  1.21132e+07	  3.16567e+06	  870783.	  3401.49	  4.40	  0.626474	  0.568593	  28652	  182587	  -1	  7894	  20	  2631	  5265	  944725	  272999	  12.7564	  12.7564	  -822.429	  -12.7564	  0	  0	  1.14646e+06	  4478.35	  0.07	  0.29	  0.18	  -1	  -1	  0.07	  0.0966458	  0.0896055	 
 EArch.xml	  diffeq2.v	  common_--cluster_seed_type_max_input_pins	  14.87	  vpr	  71.53 MiB	  	  -1	  -1	  0.18	  31296	  4	  0.10	  -1	  -1	  37396	  -1	  -1	  22	  66	  0	  5	  success	  v8.0.0-14013-ge1496c441d	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-63-generic x86_64	  2025-10-06T15:12:57	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong	  73248	  66	  96	  778	  595	  1	  464	  189	  16	  16	  256	  mult_36	  auto	  32.5 MiB	  0.36	  6715.25	  3787	  72817	  33489	  37980	  1348	  71.5 MiB	  0.58	  0.01	  13.2056	  11.9984	  -739.722	  -11.9984	  11.9984	  0.33	  0.00151917	  0.00136213	  0.218433	  0.195989	  -1	  -1	  -1	  -1	  60	  9604	  40	  1.21132e+07	  3.16567e+06	  1.01260e+06	  3955.47	  11.81	  0.980752	  0.888523	  29928	  206364	  -1	  7473	  20	  2992	  5911	  984789	  307180	  12.937	  12.937	  -830.995	  -12.937	  0	  0	  1.26536e+06	  4942.82	  0.05	  0.25	  0.20	  -1	  -1	  0.05	  0.0806253	  0.0745171	 
 EArch.xml	  diffeq2.v	  common_--cluster_seed_type_blend2	  11.86	  vpr	  71.72 MiB	  	  -1	  -1	  0.20	  31420	  4	  0.10	  -1	  -1	  37652	  -1	  -1	  22	  66	  0	  5	  success	  v8.0.0-14013-ge1496c441d	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-63-generic x86_64	  2025-10-06T15:12:57	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong	  73440	  66	  96	  778	  595	  1	  467	  189	  16	  16	  256	  mult_36	  auto	  32.6 MiB	  0.27	  7184.04	  3802	  65771	  33716	  31433	  622	  71.7 MiB	  0.59	  0.01	  13.8986	  11.8837	  -729.396	  -11.8837	  11.8837	  0.32	  0.00160062	  0.00144479	  0.201891	  0.181485	  -1	  -1	  -1	  -1	  48	  9779	  43	  1.21132e+07	  3.16567e+06	  817991.	  3195.28	  8.86	  0.859511	  0.778772	  27888	  167588	  -1	  8156	  24	  3768	  7670	  1371126	  380977	  13.4414	  13.4414	  -868.472	  -13.4414	  0	  0	  1.04918e+06	  4098.38	  0.05	  0.34	  0.15	  -1	  -1	  0.05	  0.0927116	  0.0854742	 
