##############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog

# Path to directory of architectures to use
archs_dir=arch/timing

# Add circuits to list to sweep
circuit_list_add=raygentop.v

# Add architectures to list to sweep
arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
arch_list_add=k6_frac_N10_mem32K_40nm.xml
arch_list_add=k6_N10_mem32K_40nm.xml

# Parse info and how to parse
parse_file=vpr_fixed_chan_width.txt
parse_file=vpr_parse_second_file.txt

# How to parse QoR info
qor_parse_file=qor_rr_graph.txt

# Pass requirements
pass_requirements_file=pass_requirements_verify_rr_graph.txt

# Script parameters
script_params = -verify_rr_graph --route_chan_width 130 --flat_routing on
