 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  routed_wirelength	  avg_routed_wirelength	  routed_wiresegment	  avg_routed_wiresegment	  total_nets_routed	  total_connections_routed	  total_heap_pushes	  total_heap_pops	  logic_block_area_total	  logic_block_area_used	  routing_area_total	  routing_area_per_tile	  crit_path_route_success_iteration	  num_rr_graph_nodes	  num_rr_graph_edges	  collapsed_nodes	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  create_rr_graph_time	  create_intra_cluster_rr_graph_time	  adding_internal_edges	  route_mem	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  router_lookahead_mem	  tile_lookahead_computation_time	  router_lookahead_computation_time	 
 soft_fpu_arch_timing.xml	  bfly.v	  common	  27.66	  parmys	  118.17 MiB	  	  -1	  -1	  14.13	  121008	  23	  4.48	  -1	  -1	  43604	  -1	  -1	  1066	  193	  -1	  -1	  success	  5160a12-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-47-generic x86_64	  2025-06-17T12:01:36	  agent-2	  /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing	  87260	  193	  64	  3952	  4016	  1	  2618	  1323	  35	  35	  1225	  clb	  auto	  45.7 MiB	  0.74	  83904.4	  23873	  524043	  167772	  353800	  2471	  85.2 MiB	  3.85	  0.05	  28.1172	  15.0385	  -3619.75	  -15.0385	  15.0385	  0.00	  0.00768565	  0.00692548	  0.630424	  0.561566	  -1	  -1	  -1	  -1	  41953	  16.0310	  10736	  4.10241	  20993	  73379	  5061576	  743299	  2.49624e+06	  2.44352e+06	  2.83731e+06	  2316.17	  22	  66042	  566079	  -1	  13.8778	  13.8778	  -3344.6	  -13.8778	  -32.8132	  -0.0851	  0.62	  -1	  -1	  85.2 MiB	  1.64	  1.05787	  0.950479	  85.2 MiB	  -1	  0.20	 
 soft_fpu_arch_timing.xml	  bgm.v	  common	  60.53	  parmys	  235.27 MiB	  	  -1	  -1	  34.72	  240920	  18	  11.36	  -1	  -1	  51200	  -1	  -1	  1472	  257	  -1	  -1	  success	  5160a12-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-47-generic x86_64	  2025-06-17T12:01:36	  agent-2	  /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing	  100236	  257	  32	  6056	  6088	  1	  3850	  1761	  41	  41	  1681	  clb	  auto	  58.1 MiB	  1.10	  141475	  31923	  862791	  289060	  570213	  3518	  97.9 MiB	  6.70	  0.08	  28.1556	  12.5801	  -5390.91	  -12.5801	  12.5801	  0.00	  0.0106658	  0.00955948	  0.973841	  0.859612	  -1	  -1	  -1	  -1	  53621	  13.9348	  13762	  3.57640	  25082	  81149	  5265371	  809785	  3.48649e+06	  3.37417e+06	  3.92715e+06	  2336.20	  22	  90666	  782499	  -1	  11.7149	  11.7149	  -5042.11	  -11.7149	  -30.9772	  -0.0851	  0.86	  -1	  -1	  97.9 MiB	  1.88	  1.5762	  1.40892	  97.9 MiB	  -1	  0.29	 
 soft_fpu_arch_timing.xml	  dscg.v	  common	  21.90	  parmys	  116.05 MiB	  	  -1	  -1	  15.27	  118836	  23	  1.80	  -1	  -1	  41824	  -1	  -1	  604	  129	  -1	  -1	  success	  5160a12-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-47-generic x86_64	  2025-06-17T12:01:36	  agent-2	  /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing	  75100	  129	  64	  2180	  2244	  1	  1511	  797	  27	  27	  729	  clb	  auto	  33.5 MiB	  0.42	  37375.4	  13132	  233456	  63798	  161614	  8044	  73.3 MiB	  1.58	  0.02	  26.6309	  16.2433	  -1873.68	  -16.2433	  16.2433	  0.00	  0.00436646	  0.00395084	  0.310192	  0.277201	  -1	  -1	  -1	  -1	  22955	  15.6369	  5922	  4.03406	  10719	  38121	  2623096	  390043	  1.43263e+06	  1.3845e+06	  1.65895e+06	  2275.65	  20	  39258	  331839	  -1	  15.0482	  15.0482	  -1745.07	  -15.0482	  -8.43157	  -0.0851	  0.36	  -1	  -1	  73.3 MiB	  0.81	  0.527064	  0.475607	  73.3 MiB	  -1	  0.12	 
 soft_fpu_arch_timing.xml	  fir.v	  common	  16.81	  parmys	  104.71 MiB	  	  -1	  -1	  12.53	  107224	  16	  0.97	  -1	  -1	  40836	  -1	  -1	  477	  161	  -1	  -1	  success	  5160a12-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-47-generic x86_64	  2025-06-17T12:01:36	  agent-2	  /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing	  72948	  161	  32	  2044	  2076	  1	  1161	  670	  24	  24	  576	  clb	  auto	  31.5 MiB	  0.27	  22669.1	  7166	  179400	  47868	  128994	  2538	  71.2 MiB	  1.01	  0.02	  16.9169	  10.9809	  -1594.34	  -10.9809	  10.9809	  0.00	  0.00302947	  0.00270243	  0.214083	  0.187844	  -1	  -1	  -1	  -1	  10765	  9.28818	  2792	  2.40897	  5365	  14365	  894406	  138378	  1.10943e+06	  1.09338e+06	  1.29802e+06	  2253.51	  20	  30996	  260004	  -1	  10.2137	  10.2137	  -1485.34	  -10.2137	  -40.92	  -0.0851	  0.28	  -1	  -1	  71.2 MiB	  0.35	  0.365897	  0.325466	  71.2 MiB	  -1	  0.10	 
 soft_fpu_arch_timing.xml	  mm3.v	  common	  11.02	  parmys	  79.82 MiB	  	  -1	  -1	  9.12	  81736	  12	  0.29	  -1	  -1	  37880	  -1	  -1	  188	  193	  -1	  -1	  success	  5160a12-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-47-generic x86_64	  2025-06-17T12:01:36	  agent-2	  /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing	  64456	  193	  32	  898	  930	  1	  553	  413	  21	  21	  441	  io	  auto	  23.4 MiB	  0.11	  8625.64	  2803	  78800	  19553	  56674	  2573	  62.9 MiB	  0.33	  0.01	  10.8779	  8.00277	  -551.634	  -8.00277	  8.00277	  0.00	  0.001583	  0.00143182	  0.083494	  0.0748192	  -1	  -1	  -1	  -1	  4138	  7.49638	  1100	  1.99275	  2147	  4623	  291073	  46671	  827486	  430936	  981244.	  2225.04	  19	  23706	  196899	  -1	  7.21113	  7.21113	  -510.699	  -7.21113	  -7.41122	  -0.0851	  0.20	  -1	  -1	  62.9 MiB	  0.14	  0.152289	  0.13775	  62.9 MiB	  -1	  0.06	 
 soft_fpu_arch_timing.xml	  ode.v	  common	  30.29	  parmys	  118.09 MiB	  	  -1	  -1	  11.37	  120928	  24	  5.92	  -1	  -1	  48264	  -1	  -1	  1438	  130	  -1	  -1	  success	  5160a12-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-47-generic x86_64	  2025-06-17T12:01:36	  agent-2	  /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing	  103044	  130	  72	  5272	  5344	  1	  3421	  1640	  40	  40	  1600	  clb	  auto	  55.1 MiB	  1.04	  126807	  36004	  765333	  248369	  513482	  3482	  100.6 MiB	  5.95	  0.07	  33.0772	  16.1107	  -5213.26	  -16.1107	  16.1107	  0.00	  0.00960841	  0.00863027	  0.878961	  0.776562	  -1	  -1	  -1	  -1	  61402	  17.9696	  15728	  4.60287	  28208	  99328	  7061757	  1040792	  3.30999e+06	  3.29623e+06	  3.73324e+06	  2333.28	  24	  86292	  744004	  -1	  14.8905	  14.8905	  -4876.52	  -14.8905	  -57.5886	  -0.0851	  0.81	  -1	  -1	  100.6 MiB	  2.30	  1.47067	  1.31356	  100.6 MiB	  -1	  0.27	 
 soft_fpu_arch_timing.xml	  syn2.v	  common	  52.86	  parmys	  144.09 MiB	  	  -1	  -1	  14.47	  147548	  22	  11.40	  -1	  -1	  47592	  -1	  -1	  2457	  161	  -1	  -1	  success	  5160a12-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-47-generic x86_64	  2025-06-17T12:01:36	  agent-2	  /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing	  145100	  161	  128	  8510	  8638	  1	  6072	  2746	  52	  52	  2704	  clb	  auto	  79.4 MiB	  1.88	  282197	  67436	  1674973	  609921	  1045583	  19469	  141.7 MiB	  15.76	  0.17	  38.8078	  17.2328	  -8053.94	  -17.2328	  17.2328	  0.00	  0.0182018	  0.0164756	  1.80752	  1.58456	  -1	  -1	  -1	  -1	  115256	  19.1678	  29302	  4.87311	  41573	  148441	  10663309	  1551843	  5.73043e+06	  5.63188e+06	  6.38377e+06	  2360.86	  19	  145908	  1269964	  -1	  16.6118	  16.6118	  -7586.67	  -16.6118	  -26.8228	  -0.0851	  1.46	  -1	  -1	  141.7 MiB	  3.58	  2.72681	  2.41142	  141.7 MiB	  -1	  0.49	 
