#
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# Configuration file for running experiments
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#This task checks for logical equivalency of a netlist before and after VPR using ABC. It performs a formal equivalence check but tests the same 
#benchmarks as vtr_reg_mcnc. 

# Path to directory of circuits to use
circuits_dir=benchmarks/blif/wiremap6

# Path to directory of architectures to use
archs_dir=arch/timing

# Add circuits to list to sweep
circuit_list_add=alu4.pre-vpr.blif
circuit_list_add=apex2.pre-vpr.blif
circuit_list_add=apex4.pre-vpr.blif
circuit_list_add=bigkey.pre-vpr.blif
circuit_list_add=clma.pre-vpr.blif
circuit_list_add=des.pre-vpr.blif
circuit_list_add=diffeq.pre-vpr.blif
circuit_list_add=dsip.pre-vpr.blif
circuit_list_add=elliptic.pre-vpr.blif
circuit_list_add=ex1010.pre-vpr.blif
circuit_list_add=ex5p.pre-vpr.blif
circuit_list_add=frisc.pre-vpr.blif
circuit_list_add=misex3.pre-vpr.blif
circuit_list_add=pdc.pre-vpr.blif
circuit_list_add=s298.pre-vpr.blif
#The test appears to reach a time-limit and exits. Logical equivalence is UNDECIDED (not false). Tried running combinational verification instead of sequential verification manually on ABC. Since VPR changes the names of elements, this is not an appropriate verification method. 
#circuit_list_add=s38417.pre-vpr.blif
circuit_list_add=s38584.1.pre-vpr.blif
circuit_list_add=seq.pre-vpr.blif
circuit_list_add=spla.pre-vpr.blif
circuit_list_add=tseng.pre-vpr.blif

# Add architectures to list to sweep
arch_list_add=k6_N10_40nm.xml

# Parse info and how to parse
parse_file=vpr_standard.txt

# Pass requirements
pass_requirements_file=pass_requirements.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

script_params=-starting_stage vpr --gen_post_synthesis_netlist on -check_equivalent --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --absorb_buffer_luts off 

