arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
k6_frac_N10_mem32K_40nm.xml	multiclock_output_and_latch.v	common	0.58	vpr	65.42 MiB		-1	-1	0.06	20016	1	0.04	-1	-1	31872	-1	-1	2	6	0	0	success	v8.0.0-14178-g4818739e3-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-71-generic x86_64	2025-10-15T12:13:40	betzgrp-wintermute	/home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow	66992	6	1	13	14	2	8	9	4	4	16	clb	auto	27.2 MiB	0.00	23	18	432	135	191	106	65.4 MiB	0.00	0.00	1.02737	1.02737	-3.59667	-1.02737	0.545	0.00	2.1632e-05	1.464e-05	0.00123361	0.00095388	-1	-1	-1	-1	20	12	8	107788	107788	10441.3	652.579	0.01	0.00270418	0.00228652	742	1670	-1	13	3	11	11	148	85	1.2939	0.545	-4.03651	-1.2939	0	0	13748.8	859.301	0.00	0.00	0.00	-1	-1	0.00	0.00131752	0.00124065	
k6_frac_N10_mem32K_40nm.xml	multiclock_reader_writer.v	common	0.58	vpr	65.42 MiB		-1	-1	0.08	20016	1	0.04	-1	-1	31584	-1	-1	2	3	0	0	success	v8.0.0-14178-g4818739e3-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-71-generic x86_64	2025-10-15T12:13:40	betzgrp-wintermute	/home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow	66992	3	-1	23	23	2	3	5	4	4	16	clb	auto	27.2 MiB	0.01	5	5	12	3	1	8	65.4 MiB	0.00	0.00	0.620233	0.620233	-7.93093	-0.620233	0.545	0.00	4.0393e-05	3.3794e-05	0.000379225	0.000343741	-1	-1	-1	-1	4	3	1	107788	107788	2525.47	157.842	0.01	0.00233574	0.00213556	594	690	-1	4	1	1	1	12	8	0.658498	0.545	-8.08399	-0.658498	0	0	3500.90	218.806	0.00	0.00	0.00	-1	-1	0.00	0.00152267	0.0014593	
