# Xilinx specific requirements for VTR pass
%include "common/pass_requirements.vpr_status.txt"
%include "timing/pass_requirements.vpr_pack_place.txt"

#Routing Metrics
routed_wirelength;RangeAbs(0.50,1.50,5)

#Area metrics
logic_block_area_total;Range(0.5,1.6)
logic_block_area_used;Range(0.5,1.6)
routing_area_total;Range(0.5,1.6)
routing_area_per_tile;Range(0.5,1.6)

#Run-time metrics
crit_path_route_time;RangeAbs(0.10,10.0,2)


#Peak memory
max_vpr_mem;RangeAbs(0.5,2.0,102400)