YES: as in actually attempted (total LEs from quartus)
	md5_piplined
		ready-for-preprocessing file: Md5Core.v
		18.7k total logic elements
		source:
			http://opencores.org/project,md5_pipelined

		At the time of commit, this circuit causes ODIN to segfault (bug is reported). The last
		know version of ODIN for it to pass is the one in r4443

	piplined_fft_64 - {forward, inverse} fast fourier transform - 128 & 256 bits available, also
		ready-for-preprocessing file: pipelined_fft_64.v
		4.8k total logic elements
		source:
			http://opencores.org/project,pipelined_fft_64
			or https://github.com/freecores/pipelined_fft_64

		Never got this one to go through, ODIN segfaults in the AST->netlist converter

	verilog_cordic_core - calcs trig functions using Volder's algorithm
		1.1k total logic elements
		source:
			http://opencores.org/project,verilog_cordic_core
			or https://github.com/freecores/verilog_cordic_core

		turned out to be a bit small, but this is becasue I decided to make the "ITERATE" mode of
		the circuit pass ODIN, as the other modes require a generate loop, and support for them
		(or something like them) was not added to my processor. The loop could be unrolled
		manually, but that's a bit tedious.

	rc4-prbs - generates a pseudo random byte stream using rc4
		source:
			http://opencores.org/project,rc4-prbs
			or https://github.com/freecores/rc4-prbs
		7.1k total logic elements




Some other circuits on opencores that I looked at:

YES, BUT NO (TO SMALL):
	ima_adpcm_enc_dec - IMA Adaptive differential pulse-code modulation
		enc: 0.38k total logic elements
		dec: 0.21k total logic elements 
	fht
		fast hadamard transform
		0.039k total logic elements
		*tiny*

MAYBE:
	cavlc - Context-adaptive variable-length coding
		very few add/sub
	dvb_s2_ldpc_decoder - Digital Video Broadcasting - Satellite - Second Generation, Low-Density Parity-Check decoder
		a few adders
		huge circuit
		but many generate loops
	vitdec - Configurable High Speed Viterbi Decoder
		39.9k total logic elements
		but many arrays and generate loops

NO:
	pid_controller - has mult and add, but it's defined combinationally
	sha3 - mostly xors
	fpga-median - no adding

