arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
k6_frac_N10_frac_chain_mem32K_40nm.xml	ch_intrinsics.v	common	239.31	-	-		-1	-1	-1	-1	3	17.61	-1	-1	-1	-1	-1	68	99	1	0	success	v8.0.0-11925-ga544f5fea-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2025-01-14T21:35:49	betzgrp-wintermute.eecg.utoronto.ca	/home/elgamma8/research/release/vtr-verilog-to-routing	-1	99	130	344	474	1	227	298	12	12	144	clb	auto	322.7 MiB	20.06	749	71938	22933	33485	15520	381.0 MiB	16.97	0.33	1.86413	-118.59	-1.86413	1.86413	11.65	0.0732576	0.068454	5.52499	5.15173	-1	-1	-1	-1	42	1520	10	5.66058e+06	4.21279e+06	345696.	2400.67	36.36	14.4547	13.0534	13090	66981	-1	1349	11	399	648	28156	8528	2.01841	2.01841	-138.411	-2.01841	0	0	434636.	3018.30	1.10	3.62	6.08	-1	-1	1.10	2.02601	1.79237	
k6_frac_N10_frac_chain_mem32K_40nm.xml	stereovision3.v	common	253.64	-	-		-1	-1	-1	-1	4	20.25	-1	-1	-1	-1	-1	15	11	0	0	success	v8.0.0-11925-ga544f5fea-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2025-01-14T21:35:49	betzgrp-wintermute.eecg.utoronto.ca	/home/elgamma8/research/release/vtr-verilog-to-routing	-1	11	2	303	283	2	78	28	7	7	49	clb	auto	317.6 MiB	15.14	262	1078	238	765	75	376.4 MiB	3.35	0.07	2.0391	-163.079	-2.0391	1.90116	2.96	0.058501	0.053558	1.68082	1.53185	-1	-1	-1	-1	28	333	12	1.07788e+06	808410	72669.7	1483.05	25.62	14.1524	12.0861	3564	12808	-1	288	8	200	345	4799	1871	2.11979	1.94261	-165.174	-2.11979	0	0	87745.0	1790.71	0.23	2.68	1.60	-1	-1	0.23	1.45763	1.25544	
