arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_le	num_luts	num_add_blocks	max_add_chain_length	num_sub_blocks	max_sub_chain_length	
k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml	diffeq2.v	common	6.72	vpr	69.11 MiB		-1	-1	0.17	24288	5	0.10	-1	-1	33760	-1	-1	16	66	0	-1	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	70768	66	96	979	693	1	551	190	16	16	256	mult_27	auto	29.3 MiB	0.57	8030.03	4494	40594	12369	27477	748	69.1 MiB	0.28	0.00	19.1915	17.0319	-960.71	-17.0319	17.0319	0.29	0.00130328	0.00121213	0.116459	0.10872	-1	-1	-1	-1	62	11096	33	4.83877e+06	1.00808e+06	1.31386e+06	5132.27	3.70	0.510249	0.472622	39852	267778	-1	9784	19	3259	6633	1558092	458525	17.1336	17.1336	-1044.15	-17.1336	0	0	1.60318e+06	6262.42	0.05	0.31	0.17	-1	-1	0.05	0.0771053	0.0727379	134	198	-1	-1	-1	-1	
