arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	routed_wirelength	avg_routed_wirelength	routed_wiresegment	avg_routed_wiresegment	total_nets_routed	total_connections_routed	total_heap_pushes	total_heap_pops	logic_block_area_total	logic_block_area_used	routing_area_total	routing_area_per_tile	crit_path_route_success_iteration	num_rr_graph_nodes	num_rr_graph_edges	collapsed_nodes	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	create_rr_graph_time	create_intra_cluster_rr_graph_time	adding_internal_edges	route_mem	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	router_lookahead_mem	tile_lookahead_computation_time	router_lookahead_computation_time	
stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml	2561.37	vpr	2.83 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	5160a12-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-47-generic x86_64	2025-06-17T12:01:36	agent-2	/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing	2964948	42	35	119888	86875	1	53056	3362	129	96	12384	-1	neuron	1857.2 MiB	2219.16	1.20033e+06	693277	2923662	1079880	1509779	334003	2895.5 MiB	149.50	1.22	8.80293	7.66945	-89228.2	-6.66945	5.59958	0.12	0.384931	0.32027	46.7938	39.6651	-1	-1	-1	-1	891861	16.8253	188498	3.55610	109093	186569	126129670	32663933	0	0	2.28639e+08	18462.4	17	3593250	39165143	-1	8.01011	5.90546	-120853	-7.01011	0	0	65.39	-1	-1	2895.5 MiB	46.66	65.4181	56.6187	2895.5 MiB	-1	30.50	
stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml	462.80	vpr	2.82 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	5160a12-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-47-generic x86_64	2025-06-17T12:01:36	agent-2	/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing	2960780	42	35	119888	86875	1	50971	3452	129	96	12384	-1	neuron	1852.7 MiB	137.46	1.86667e+06	572095	3211046	1215763	1834304	160979	2891.4 MiB	142.29	1.10	12.1815	7.95378	-83142.3	-6.95378	6.9595	0.09	0.348595	0.308804	46.97	40.2029	-1	-1	-1	-1	741344	14.5584	158382	3.11029	99557	166785	100872233	26637750	0	0	2.28639e+08	18462.4	15	3593250	39165143	-1	8.18469	7.24942	-119217	-7.18469	0	0	64.32	-1	-1	2891.4 MiB	37.17	63.4337	55.2488	2891.4 MiB	-1	28.28	
stratixiv_arch_neuron.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml	462.04	vpr	2.83 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	5160a12-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-47-generic x86_64	2025-06-17T12:01:36	agent-2	/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing	2962260	42	35	119888	86875	1	50979	3430	129	96	12384	-1	neuron	1854.0 MiB	136.00	2.09977e+06	569255	3080294	1129655	1903045	47594	2892.8 MiB	140.35	1.12	11.1893	7.9572	-81217.2	-6.9572	5.64739	0.09	0.370582	0.311466	46.5755	39.4156	-1	-1	-1	-1	744588	14.6198	159274	3.12731	100521	169111	104708994	27841220	0	0	2.28639e+08	18462.4	16	3593250	39165143	-1	8.31659	6.27019	-111491	-7.31659	0	0	64.24	-1	-1	2892.8 MiB	38.65	63.6117	54.999	2892.8 MiB	-1	28.29	
