 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  routed_wirelength	  avg_routed_wirelength	  routed_wiresegment	  avg_routed_wiresegment	  total_nets_routed	  total_connections_routed	  total_heap_pushes	  total_heap_pops	  logic_block_area_total	  logic_block_area_used	  routing_area_total	  routing_area_per_tile	  crit_path_route_success_iteration	  num_rr_graph_nodes	  num_rr_graph_edges	  collapsed_nodes	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  create_rr_graph_time	  create_intra_cluster_rr_graph_time	  adding_internal_edges	  route_mem	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  router_lookahead_mem	  tile_lookahead_computation_time	  router_lookahead_computation_time	 
 k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml	  ch_intrinsics.v	  common	  1.53	  vpr	  64.00 MiB	  	  0.04	  9216	  -1	  -1	  4	  0.22	  -1	  -1	  33484	  -1	  -1	  80	  99	  1	  0	  success	  v8.0.0-13084-g071ad3865	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-17T09:37:40	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  65532	  99	  130	  378	  508	  1	  307	  310	  15	  15	  225	  memory	  auto	  24.5 MiB	  0.03	  2811.06	  1104	  73670	  25913	  39499	  8258	  64.0 MiB	  0.15	  0.00	  1.90937	  1.68954	  -172.798	  -1.68954	  1.68954	  0.00	  0.000593733	  0.000551982	  0.0439001	  0.0407723	  -1	  -1	  -1	  -1	  1507	  6.15102	  796	  3.24898	  751	  1795	  225767	  57149	  1.16234e+06	  394748	  2.18283e+06	  9701.45	  12	  48952	  428016	  -1	  1.90591	  1.90591	  -183.295	  -1.90591	  -0.0624581	  -0.0378719	  0.38	  -1	  -1	  64.0 MiB	  0.06	  0.0636163	  0.0589693	  64.0 MiB	  -1	  0.18	 
