arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	routed_wirelength	avg_routed_wirelength	routed_wiresegment	avg_routed_wiresegment	total_nets_routed	total_connections_routed	total_heap_pushes	total_heap_pops	logic_block_area_total	logic_block_area_used	routing_area_total	routing_area_per_tile	crit_path_route_success_iteration	num_rr_graph_nodes	num_rr_graph_edges	collapsed_nodes	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	create_rr_graph_time	create_intra_cluster_rr_graph_time	adding_internal_edges	route_mem	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	router_lookahead_mem	tile_lookahead_computation_time	router_lookahead_computation_time	
3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml	453.60	vpr	3.71 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	v8.0.0-14974-g0a49f14d7	release VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-60-generic x86_64	2026-01-20T17:21:14	soheil-pt372	/home/soheil/vtr/vtr-verilog-to-routing/vtr_flow	3893456	42	35	119888	86875	1	50979	3430	92	68	12512	-1	neuron3d	1861.6 MiB	110.80	1.66245e+06	477008	2640742	841670	1761676	37396	3802.2 MiB	138.24	1.16	10.0537	7.80873	-69513.6	-6.80873	6.67145	0.15	0.339856	0.28463	40.0592	33.8721	-1	-1	-1	-1	659413	12.9474	149200	2.92951	102695	170110	112107833	27898391	0	0	3.08020e+08	24618.0	13	4385924	62482500	-1	8.15564	7.29931	-110044	-7.15564	0	0	73.82	-1	-1	3802.2 MiB	37.78	57.1961	49.5254	3802.2 MiB	-1	35.39	
3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml	453.58	vpr	3.71 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	v8.0.0-14974-g0a49f14d7	release VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-60-generic x86_64	2026-01-20T17:21:14	soheil-pt372	/home/soheil/vtr/vtr-verilog-to-routing/vtr_flow	3889916	42	35	119888	86875	1	50971	3452	92	68	12512	-1	neuron3d	1858.4 MiB	111.91	1.41044e+06	501391	2637330	847660	1694161	95509	3798.7 MiB	136.33	1.27	10.473	7.51961	-68918.4	-6.51961	5.97068	0.18	0.334954	0.282874	39.7586	33.798	-1	-1	-1	-1	687426	13.4996	154031	3.02484	103901	174657	122939871	30590805	0	0	3.08020e+08	24618.0	13	4385924	62482500	-1	7.82746	6.1932	-110000	-6.82746	0	0	73.84	-1	-1	3798.7 MiB	40.38	56.201	48.8149	3798.7 MiB	-1	35.06	
3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml	449.60	vpr	3.71 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	v8.0.0-14974-g0a49f14d7	release VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-60-generic x86_64	2026-01-20T17:21:14	soheil-pt372	/home/soheil/vtr/vtr-verilog-to-routing/vtr_flow	3892160	42	35	119888	86875	1	50971	3452	92	68	12512	-1	neuron3d	1860.3 MiB	111.14	1.63087e+06	536565	2872032	946503	1458440	467089	3800.9 MiB	135.13	0.99	9.98409	7.80873	-71278.2	-6.80873	7.08906	0.16	0.337854	0.284652	43.5205	36.8697	-1	-1	-1	-1	716584	14.0722	158648	3.11551	100317	167507	115675748	28057707	0	0	3.08020e+08	24618.0	15	4385924	62482500	-1	7.91556	7.59365	-114731	-6.91556	0	0	75.14	-1	-1	3800.9 MiB	39.27	59.819	51.4759	3800.9 MiB	-1	35.21	
