odin_ii
=======

Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist.

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* **[Quick Start](../doc/src/odin/quickstart.md)**
* **[User Guide](../doc/src/odin/user_guide.md)**
* **[Verilog Support](../doc/src/odin/verilog_support.md)**
* **Developer guide**
  * [Contributing](../doc/src/odin/dev_guide/contributing)
  * [Regression Tests](../doc/src/odin/dev_guide/regression_test)
  * [Regression Tool](../doc/src/odin/dev_guide/verify_script)
  * [Validating Tests](../doc/src/odin/dev_guide/testing)

Maintained by:  [Ph.D. - alirezazd](https://github.com/alirezazd) and [M.Sc. - poname](https://github.com/poname)
Owned by: [KennethKent](https://github.com/kennethkent)
