arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
sub_tiles.xml	sub_tiles.blif	common	4.27	vpr	57.18 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	6	-1	-1	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	58556	6	7	19	26	0	19	26	3	3	9	-1	auto	18.7 MiB	0.00	51	51	216	42	70	104	57.2 MiB	0.00	0.00	3.92819	3.682	-25.774	-3.682	nan	3.55	2.2798e-05	1.8373e-05	0.000224739	0.000180522	-1	-1	-1	-1	6	19	5	14813.4	192574	-1	-1	0.06	0.00172352	0.00156199	1370	14749	-1	19	3	38	41	6204	3125	3.87729	nan	-27.141	-3.87729	0	0	-1	-1	0.00	0.00	0.02	-1	-1	0.00	0.00102049	0.000960552	
