arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
k6_frac_N10_frac_chain_mem32K_40nm.xml	clock.sv	common	1.00	vpr	68.54 MiB		-1	-1	0.14	33892	4	0.07	-1	-1	36424	-1	-1	12	3	0	0	success	v8.0.0-13290-gb84275926-dirty	release IPO VTR_ASSERT_LEVEL=2 debug_logging	GNU 11.4.0 on Linux-6.8.0-60-generic x86_64	2025-07-10T15:38:09	llavign1-OptiPlex-7070	/home/llavign1/Gits/vtr-clone/vtr_flow/scripts	70180	3	12	261	222	1	119	27	6	6	36	clb	auto	29.0 MiB	0.16	535.691	470	107	18	81	8	68.5 MiB	0.01	0.00	2.40548	2.45562	-139.625	-2.45562	2.45562	0.01	0.000220295	0.000194259	0.00283635	0.00272878	-1	-1	-1	-1	26	702	45	646728	646728	45684.2	1269.00	0.19	0.0790139	0.0683134	2404	7935	-1	576	16	443	680	18334	7784	2.53617	2.53617	-149.735	-2.53617	0	0	56055.2	1557.09	0.00	0.02	0.00	-1	-1	0.00	0.0131357	0.0121975	
