 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  routed_wirelength	  avg_routed_wirelength	  routed_wiresegment	  avg_routed_wiresegment	  total_nets_routed	  total_connections_routed	  total_heap_pushes	  total_heap_pops	  logic_block_area_total	  logic_block_area_used	  routing_area_total	  routing_area_per_tile	  crit_path_route_success_iteration	  num_rr_graph_nodes	  num_rr_graph_edges	  collapsed_nodes	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  create_rr_graph_time	  create_intra_cluster_rr_graph_time	  adding_internal_edges	  route_mem	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  router_lookahead_mem	  tile_lookahead_computation_time	  router_lookahead_computation_time	 
 k6_frac_N10_frac_chain_mem32K_40nm.xml	  spree.v	  common	  7.45	  vpr	  81.45 MiB	  	  -1	  -1	  1.54	  41932	  16	  0.45	  -1	  -1	  38736	  -1	  -1	  63	  45	  3	  1	  success	  v8.0.0-15526-g305b62890a	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-79-generic x86_64	  2026-04-09T20:00:05	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router	  83408	  45	  32	  1201	  1160	  1	  783	  144	  14	  14	  196	  memory	  auto	  44.8 MiB	  2.27	  9983.95	  6692	  37844	  15471	  21756	  617	  81.5 MiB	  0.73	  0.01	  13.1742	  11.6008	  -7101.33	  -11.6008	  11.6008	  0.00	  0.00228036	  0.00187265	  0.250721	  0.203362	  -1	  -1	  -1	  -1	  10358	  8.64608	  2785	  2.32471	  3287	  16167	  1512605	  177840	  9.20055e+06	  5.43532e+06	  1.11359e+06	  5681.59	  13	  52300	  435073	  15723	  12.1565	  12.1565	  -7600.65	  -12.1565	  0	  0	  0.15	  0.83	  0.62	  81.5 MiB	  1.41	  0.319142	  0.260786	  81.5 MiB	  0.11	  0.04	 
