arch	circuit	noc_flow	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	routed_wirelength	avg_routed_wirelength	routed_wiresegment	avg_routed_wiresegment	total_nets_routed	total_connections_routed	total_heap_pushes	total_heap_pops	logic_block_area_total	logic_block_area_used	routing_area_total	routing_area_per_tile	crit_path_route_success_iteration	num_rr_graph_nodes	num_rr_graph_edges	collapsed_nodes	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	create_rr_graph_time	create_intra_cluster_rr_graph_time	adding_internal_edges	route_mem	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	router_lookahead_mem	tile_lookahead_computation_time	router_lookahead_computation_time	
stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml	complex_2_noc_1D_chain.blif	complex_2_noc_1D_chain.flows	common	21.50	vpr	1.02 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	-1	-1	success	v8.0.0-15484-g2eed36a7b3-dirty	release VTR_ASSERT_LEVEL=3	GNU 13.3.0 on Linux-6.8.0-79-generic x86_64	2026-04-03T10:10:03	srivatsan-Precision-Tower-5810	/home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/basic_noc	1070068	2	32	1706	0	1	1099	109	36	20	-1	-1	-1	-1	-1	9050.12	6373	23769	8573	14210	986	1045.0 MiB	7.92	0.01	8.372	7.60833	-4620.11	-7.60833	7.60833	0.00	0.00363219	0.0029556	0.373138	0.301666	1045.0 MiB	7.92	1045.0 MiB	3.33	8385	7.65753	2128	1.94338	2533	4801	1134843	323366	0	0	8.91809e+06	12386.2	14	176404	1495954	-1	8.03352	8.03352	-4861.28	-8.03352	0	0	1.69	-1	-1	1045.0 MiB	0.46	0.85246	0.719788	1012.5 MiB	-1	0.66	
