#
############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog/koios

# Path to directory of architectures to use
archs_dir=arch/COFFE_22nm

# Directory containing the verilog includes file(s)
includes_dir=benchmarks/verilog/koios

# Add circuits to list to sweep
circuit_list_add=lenet.v
circuit_list_add=clstm_like.small.v
circuit_list_add=clstm_like.medium.v
circuit_list_add=clstm_like.large.v
circuit_list_add=lstm.v
circuit_list_add=gemm_layer.v
circuit_list_add=tpu_like.large.os.v
circuit_list_add=tpu_like.large.ws.v
circuit_list_add=tdarknet_like.large.v
circuit_list_add=dla_like.medium.v

# Add architectures to list to sweep
arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml

# Add include files to the list.
# Some benchmarks instantiate hard dsp and memory blocks 
# This functionality is guarded under the `complex_dsp` and `hard_mem` macros. 
# The hard_block_include.v file 
# defines this macros, thereby enabling instantiations of the hard blocks
include_list_add=hard_block_include.v

# Parse info and how to parse
parse_file=vpr_fixed_chan_width.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

# Pass requirements
pass_requirements_file=pass_requirements_fixed_chan_width.txt

#Script parameters
script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300
