#
############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config

# Path to directory of architectures to use
archs_dir=tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config

# Add circuits to list to sweep
circuit_list_add=multiclock_buf.blif

# Add architectures to list to sweep
arch_list_add=k6_frac_N10_mem32K_40nm_clk_pll_valid.xml
arch_list_add=k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml #Expect to fail

# Parse info and how to parse
parse_file=vpr_fixed_chan_width.txt

# Pass requirements
pass_requirements_file=pass_requirements_fixed_chan_width.txt

# How to parse QoR info
qor_parse_file=qor_fixed_chan_width.txt

#
# 1. Disable buffer LUT absorbtion to allow testing of .names clock buffers
# 2. For reasons that are unclear, the test architecture won't pack unless the pin feasibility filter is turned off...
#
script_params=-starting_stage vpr --absorb_buffer_luts off --clustering_pin_feasibility_filter off --route_chan_width 40

