arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
shorted_flyover_wires.xml	raygentop.v	common	13.36	vpr	84.38 MiB		-1	-1	1.80	42324	4	0.56	-1	-1	36980	-1	-1	127	236	1	6	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	86400	236	305	3177	2989	1	1517	675	19	19	361	io clb	auto	45.5 MiB	2.11	26256.7	13676	228518	71571	152602	4345	84.4 MiB	1.29	0.02	6.15359	4.52707	-2922.27	-4.52707	4.52707	0.27	0.00520014	0.00463389	0.491586	0.450976	-1	-1	-1	-1	66	27389	31	1.65001e+07	9.76854e+06	1.15238e+06	3192.19	4.57	1.78167	1.6294	36241	234685	-1	23447	15	6499	17752	2051654	539961	5.15647	5.15647	-3257.15	-5.15647	0	0	1.43513e+06	3975.42	0.05	0.59	0.18	-1	-1	0.05	0.245956	0.232946	
buffered_flyover_wires.xml	raygentop.v	common	17.92	vpr	85.62 MiB		-1	-1	1.85	42100	4	0.56	-1	-1	36740	-1	-1	127	236	1	6	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	87672	236	305	3177	2989	1	1517	675	19	19	361	io clb	auto	46.7 MiB	2.12	26863.5	14026	234436	75913	153932	4591	85.6 MiB	1.28	0.02	6.6612	4.81568	-2978.16	-4.81568	4.81568	0.27	0.00504695	0.00463605	0.478542	0.4374	-1	-1	-1	-1	70	27063	33	1.65001e+07	9.76854e+06	1.25135e+06	3466.35	9.03	2.84084	2.59043	37321	246261	-1	23419	18	7411	20094	2116596	564020	5.07139	5.07139	-3162.9	-5.07139	0	0	1.57792e+06	4370.98	0.05	0.61	0.18	-1	-1	0.05	0.266876	0.250615	
