 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_global_nets	  num_routed_nets	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_dedicated_network	  11.98	  vpr	  79.67 MiB	  	  -1	  -1	  0.64	  28200	  2	  0.09	  -1	  -1	  34364	  -1	  -1	  32	  311	  15	  0	  success	  v8.0.0-13084-g071ad3865	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-17T09:37:40	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  81584	  311	  156	  1015	  1158	  1	  965	  514	  28	  28	  784	  memory	  auto	  34.9 MiB	  0.53	  20286.3	  9613	  179560	  60507	  117014	  2039	  75.2 MiB	  0.68	  0.01	  5.38412	  4.09707	  -3737.16	  -4.09707	  4.09707	  0.83	  0.00326093	  0.00271206	  0.302492	  0.261169	  -1	  -1	  -1	  -1	  40	  15046	  14	  4.25198e+07	  9.94461e+06	  2.15543e+06	  2749.27	  6.14	  1.23514	  1.09581	  78831	  435646	  -1	  14262	  13	  2947	  3385	  1004969	  377576	  3.98177	  3.98177	  -4312.01	  -3.98177	  -483.62	  -1.59367	  2.69266e+06	  3434.52	  0.11	  0.74	  0.28	  -1	  -1	  0.11	  0.125372	  0.115519	  15	  950	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_dedicated_network	  11.86	  vpr	  80.78 MiB	  	  -1	  -1	  0.67	  28204	  2	  0.09	  -1	  -1	  34368	  -1	  -1	  32	  311	  15	  0	  success	  v8.0.0-13084-g071ad3865	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-17T09:37:40	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  82716	  311	  156	  1015	  1158	  1	  965	  514	  28	  28	  784	  memory	  auto	  34.9 MiB	  0.53	  20286.3	  9613	  179560	  60507	  117014	  2039	  75.5 MiB	  0.79	  0.01	  5.38412	  4.09707	  -3737.16	  -4.09707	  4.09707	  0.79	  0.00366526	  0.00314097	  0.367984	  0.317607	  -1	  -1	  -1	  -1	  40	  15166	  15	  4.25198e+07	  9.94461e+06	  2.19000e+06	  2793.37	  5.74	  1.58157	  1.40878	  78831	  446382	  -1	  14296	  12	  2596	  3005	  709394	  208143	  4.25492	  4.25492	  -4414.93	  -4.25492	  -255.239	  -1.60176	  2.74289e+06	  3498.59	  0.12	  0.76	  0.32	  -1	  -1	  0.12	  0.150287	  0.139155	  15	  950	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_dedicated_network	  15.93	  vpr	  78.04 MiB	  	  -1	  -1	  0.67	  28116	  2	  0.09	  -1	  -1	  34368	  -1	  -1	  32	  311	  15	  0	  success	  v8.0.0-13084-g071ad3865	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-17T09:37:40	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  79908	  311	  156	  1015	  1158	  1	  965	  514	  28	  28	  784	  memory	  auto	  35.0 MiB	  0.52	  20286.3	  8607	  175444	  58304	  115333	  1807	  77.1 MiB	  0.62	  0.01	  5.38412	  4.52468	  -3736.56	  -4.52468	  4.52468	  0.77	  0.00383382	  0.00345466	  0.273565	  0.237734	  -1	  -1	  -1	  -1	  40	  15845	  16	  4.25198e+07	  9.94461e+06	  2.15085e+06	  2743.43	  9.70	  1.39294	  1.2409	  78831	  435812	  -1	  14789	  11	  2612	  2946	  1904188	  1392265	  5.60707	  5.60707	  -4516.37	  -5.60707	  -1572.57	  -3.38058	  2.68809e+06	  3428.68	  0.11	  1.26	  0.29	  -1	  -1	  0.11	  0.115901	  0.10768	  15	  950	 
