arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	0.31	vpr	58.85 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	v8.0.0-14178-g4818739e3-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-71-generic x86_64	2025-10-15T12:13:40	betzgrp-wintermute	/home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow	60260	2	2	22	24	2	4	6	4	4	16	clb	auto	20.3 MiB	0.00	8	6	15	6	5	4	58.8 MiB	0.00	0.00	1.297	1.297	0	0	1.297	0.01	3.4304e-05	2.866e-05	0.000249886	0.000220985	-1	-1	-1	-1	6	3	2	72000	36000	4025.56	251.598	0.01	0.00160045	0.00148064	660	1032	-1	13	4	7	7	476	362	1.297	1.297	0	0	0	0	5593.62	349.601	0.00	0.00	0.00	-1	-1	0.00	0.00156966	0.00146035	
