#
############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog

# Path to directory of architectures to use
archs_dir=arch/timing

# Turned off the largest circuits since they sometimes cause the runtime of this
# test to take too long.
# circuit_list_add=LU32PEEng.v
# circuit_list_add=mcml.v

# Add circuits to list to sweep
circuit_list_add=arm_core.v
circuit_list_add=bgm.v
circuit_list_add=blob_merge.v
circuit_list_add=boundtop.v
circuit_list_add=ch_intrinsics.v
circuit_list_add=diffeq1.v
circuit_list_add=diffeq2.v
circuit_list_add=LU8PEEng.v
circuit_list_add=mkDelayWorker32B.v
circuit_list_add=mkPktMerge.v
circuit_list_add=mkSMAdapter4B.v
circuit_list_add=or1200.v
circuit_list_add=raygentop.v
circuit_list_add=sha.v
circuit_list_add=spree.v
circuit_list_add=stereovision0.v
circuit_list_add=stereovision1.v
circuit_list_add=stereovision2.v
circuit_list_add=stereovision3.v

# Add architectures to list to sweep
arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml

# Parse info and how to parse
parse_file=vpr_standard.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

# Pass requirements
pass_requirements_file=pass_requirements.txt

# Script Parameters
# Increase relaxed channel width routing iterations to avoid potential unroutes due to RR graph changes
script_params=-track_memory_usage -crit_path_router_iterations 80 --routing_failure_predictor off --seed 3
