##############################################
# Configuration file for running experiments
##############################################

script_params=-power

cmos_tech_behavior=PTM_22nm/22nm.xml

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog

# Path to directory of architectures to use
archs_dir=arch/power

# Add circuits to list to sweep
circuit_list_add=bgm.v
circuit_list_add=blob_merge.v
circuit_list_add=boundtop.v
circuit_list_add=ch_intrinsics.v
circuit_list_add=diffeq1.v
circuit_list_add=diffeq2.v
circuit_list_add=LU8PEEng.v
circuit_list_add=LU32PEEng.v
#circuit_list_add=LU64PEEng.v
circuit_list_add=mcml.v
circuit_list_add=mkDelayWorker32B.v
circuit_list_add=mkPktMerge.v
circuit_list_add=mkSMAdapter4B.v
circuit_list_add=or1200.v
circuit_list_add=raygentop.v
circuit_list_add=sha.v
#These circuits do not go through ACE2. It falsely thinks there are multiple clocks in the circuit. There is a bug with using module instantiation by port when two modules have different names for their clocks, in this case instantiation by name must be used. Tried altering the instantiation method & clock names but did not work. This fixed the error for raygentop.v
#circuit_list_add=stereovision0.v
#circuit_list_add=stereovision1.v
#circuit_list_add=stereovision2.v

#circuit_list_add=stereovision3.v

# Add architectures to list to sweep
arch_list_add=k6_N10_I40_Fi6_L4_frac0_ff1_22nm.xml

# Parse info and how to parse
#vpr_power_detailed.txt produces incompelete QoR results. (Issue #1749)
#parse_file=vpr_power_detailed.txt
parse_file=vpr_power.txt

# Pass requirements
pass_requirements_file=pass_requirements_power.txt
