##############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog

# Path to directory of architectures to use
archs_dir=arch/timing

# Add circuits to list to sweep
circuit_list_add=stereovision3.v

# Add architectures to list to sweep
arch_list_add=k6_N10_mem32K_40nm.xml

# Parse info and how to parse
parse_file=vpr_fixed_chan_width.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

# Pass requirements
pass_requirements_file=pass_requirements_fixed_chan_width.txt

# Script parameters
script_params = --route_chan_width 100 --graphics_commands "set_draw_block_outlines 0; set_draw_block_text 0; set_draw_block_internals 2; set_draw_net_max_fanout 128; save_graphics place.png; set_nets 1; save_graphics nets1.png; set_nets 2; save_graphics nets2.png; set_nets 0; set_cpd 1; save_graphics cpd1.png;"
