arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
stratixiv_arch.timing.xml	styr.blif	common_--place_delay_model_delta	23.28	vpr	981.05 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	10	-1	-1	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	1004596	10	10	168	178	1	65	30	11	8	88	io	auto	954.9 MiB	0.41	530.545	354	720	98	607	15	981.1 MiB	0.07	0.00	6.8164	6.24473	-69.3994	-6.24473	6.24473	1.21	0.000321906	0.00028721	0.00819273	0.00763634	-1	-1	-1	-1	20	809	18	0	0	100248.	1139.18	0.31	0.0548304	0.048772	11180	23751	-1	686	13	300	1211	67093	34049	6.82928	6.82928	-75.2585	-6.82928	0	0	125464.	1425.72	0.00	0.06	0.03	-1	-1	0.00	0.0173778	0.0161622	
stratixiv_arch.timing.xml	styr.blif	common_--place_delay_model_delta_override	23.39	vpr	980.55 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	10	-1	-1	success	v8.0.0-13084-g071ad3865	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	2025-06-17T09:37:40	betzgrp-wintermute	/home/pooladam/vtr-verilog-to-routing	1004080	10	10	168	178	1	65	30	11	8	88	io	auto	954.8 MiB	0.41	530.545	354	720	99	604	17	980.5 MiB	0.07	0.00	6.8164	6.3238	-69.3132	-6.3238	6.3238	1.21	0.000311467	0.000283226	0.00849472	0.00791892	-1	-1	-1	-1	20	869	29	0	0	100248.	1139.18	0.74	0.102195	0.0886909	11180	23751	-1	747	20	502	2158	118628	62327	6.88229	6.88229	-76.2984	-6.88229	0	0	125464.	1425.72	0.00	0.07	0.03	-1	-1	0.00	0.0208801	0.0191175	
