 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml	  mkSMAdapter4B.v	  common	  14.37	  vpr	  86.33 MiB	  	  0.22	  29184	  -1	  -1	  4	  1.60	  -1	  -1	  37456	  -1	  -1	  165	  193	  5	  0	  success	  v8.0.0-13084-g071ad3865	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-17T09:37:40	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  88404	  193	  205	  2863	  2789	  1	  1378	  568	  20	  20	  400	  memory	  auto	  45.9 MiB	  1.18	  23047.3	  11184	  247423	  82212	  147539	  17672	  86.3 MiB	  1.43	  0.02	  6.47551	  5.31013	  -2667.2	  -5.31013	  5.31013	  0.39	  0.00500278	  0.00458173	  0.586564	  0.530731	  -1	  -1	  -1	  -1	  72	  22713	  35	  2.07112e+07	  1.16325e+07	  1.95196e+06	  4879.90	  6.39	  2.09174	  1.90508	  51278	  406530	  -1	  19691	  16	  5374	  14887	  1195826	  264156	  5.65479	  5.65479	  -2950.38	  -5.65479	  -9.24998	  -0.341744	  2.43434e+06	  6085.85	  0.08	  0.50	  0.29	  -1	  -1	  0.08	  0.290842	  0.272211	 
