arch	circuit	noc_flow	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	NoC_agg_bandwidth	NoC_latency	NoC_n_met_latency_constraints	NoC_latency_overrun	NoC_congested_bw	NoC_congestion_ratio	NoC_n_congested_links	SAT_agg_bandwidth	SAT_latency	SAT_n_met_latency_constraints	SAT_latency_overrun	SAT_congested_bw	SAT_congestion_ratio	SAT_n_congested_links	
stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml	complex_64_noc_clique.blif	complex_64_noc_clique.flows	common	5293.76	vpr	8.45 GiB		-1	2	-1	-1	success	5160a12-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-47-generic x86_64	2025-06-17T12:01:36	agent-2	/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing	8865576	2	64	249332	210540	1	124682	8273	220	162	35640	-1	EP4SE820	2735.5 MiB	621.26	1.09982e+07	1066910	9709933	4010530	5615053	84350	8657.8 MiB	2209.77	6.08	24.8441	7.23069	-912320	-7.23069	7.23069	551.90	0.69318	0.592079	89.6507	73.2677	154	1282524	50	0	0	3.59543e+08	10088.2	1360.83	358.192	298.628	8640214	77173879	-1	1289660	18	292331	690471	133166963	30869962	7.4707	7.4707	-1.06341e+06	-7.4707	0	0	4.57197e+08	12828.2	69.46	69.20	122.50	-1	-1	69.46	35.7196	31.3382	8.4448e+09	4.6256e-05	220	3.416e-05	8190.8	8190.8	254 	-1	-1	-1	-1	-1	-1	-1	
