 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 fixed_grid.xml	  raygentop.v	  common	  18.46	  vpr	  87.04 MiB	  	  0.27	  31488	  -1	  -1	  3	  0.97	  -1	  -1	  40040	  -1	  -1	  123	  214	  0	  8	  success	  v8.0.0-13084-g071ad3865	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-17T09:37:40	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  89128	  214	  305	  2963	  2869	  1	  1441	  650	  25	  25	  625	  -1	  25x25	  47.0 MiB	  2.55	  25907.4	  12547	  220142	  66436	  150269	  3437	  87.0 MiB	  1.01	  0.02	  5.35403	  4.41932	  -2697.98	  -4.41932	  4.41932	  0.58	  0.00444414	  0.00409095	  0.381975	  0.350292	  -1	  -1	  -1	  -1	  48	  25900	  48	  3.19446e+07	  9.79696e+06	  1.97188e+06	  3155.02	  9.57	  1.81783	  1.67396	  64995	  397836	  -1	  21571	  17	  6896	  16934	  2225922	  559049	  4.89967	  4.89967	  -3107.62	  -4.89967	  0	  0	  2.52596e+06	  4041.53	  0.08	  0.52	  0.25	  -1	  -1	  0.08	  0.21427	  0.202465
