arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
k6_frac_N10_frac_chain_mem32K_40nm.xml	flattened_pulse_width_led.sv	common	0.56	vpr	67.34 MiB		-1	-1	0.10	34020	2	0.02	-1	-1	35132	-1	-1	3	9	0	0	success	v8.0.0-13290-gb84275926-dirty	release IPO VTR_ASSERT_LEVEL=2 debug_logging	GNU 11.4.0 on Linux-6.8.0-60-generic x86_64	2025-07-10T15:38:09	llavign1-OptiPlex-7070	/home/llavign1/Gits/vtr-clone/vtr_flow/tasks	68956	9	3	145	109	1	14	15	5	5	25	clb	auto	28.4 MiB	0.02	55	43	51	16	34	1	67.3 MiB	0.00	0.00	1.225	1.225	-51.8382	-1.225	1.225	0.01	0.000107511	9.5853e-05	0.00103186	0.00097788	-1	-1	-1	-1	18	38	1	323364	161682	19301.3	772.054	0.05	0.00741415	0.00671207	1386	3298	-1	36	1	11	11	135	79	1.225	1.225	-51.9895	-1.225	0	0	24611.1	984.442	0.00	0.00	0.00	-1	-1	0.00	0.00313839	0.00304238	
