 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 k6_frac_N10_40nm.xml	  apex4.pre-vpr.blif	  common	  8.13	  vpr	  74.18 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  82	  9	  -1	  -1	  success	  v8.0.0-15501-g59ac66b815-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-79-generic x86_64	  2026-04-05T14:33:22	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing	  75956	  9	  19	  896	  916	  0	  601	  110	  12	  12	  144	  clb	  auto	  -1	  -1	  6632.65	  6174	  12471	  2667	  9458	  346	  74.2 MiB	  2.66	  0.01	  5.34702	  4.8936	  -81.0562	  -4.8936	  nan	  0.00	  0.00209058	  0.00173357	  0.111681	  0.0938069	  74.2 MiB	  2.66	  74.2 MiB	  1.40	  64	  10795	  31	  5.3894e+06	  4.41931e+06	  575115.	  3993.85	  2.12	  0.7532	  0.635809	  13491	  94197	  -1	  8611	  19	  4439	  21392	  643448	  116140	  5.09226	  nan	  -82.826	  -5.09226	  0	  0	  588633.	  4864.74	  0.02	  0.26	  0.07	  -1	  -1	  0.02	  0.333291	  0.288456	 
 k6_frac_N10_40nm.xml	  des.pre-vpr.blif	  common	  6.24	  vpr	  80.37 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  63	  256	  -1	  -1	  success	  v8.0.0-15501-g59ac66b815-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-79-generic x86_64	  2026-04-05T14:33:22	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing	  82300	  256	  245	  954	  1199	  0	  598	  564	  18	  18	  324	  io	  auto	  -1	  -1	  6401.81	  5693	  98382	  19565	  78434	  383	  80.4 MiB	  1.87	  0.01	  4.98976	  4.05772	  -718.04	  -4.05772	  nan	  0.00	  0.00209266	  0.001875	  0.104324	  0.0937235	  80.4 MiB	  1.87	  80.4 MiB	  0.33	  36	  10023	  37	  1.37969e+07	  3.39532e+06	  824466.	  2544.65	  2.04	  0.836156	  0.763272	  31748	  166456	  -1	  8398	  11	  2142	  4786	  224918	  52868	  4.54294	  nan	  -801.65	  -4.54294	  0	  0	  1.01518e+06	  3133.28	  0.05	  0.13	  0.12	  -1	  -1	  0.05	  0.307901	  0.281387	 
 k6_frac_N10_40nm.xml	  ex1010.pre-vpr.blif	  common	  34.70	  vpr	  99.75 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  302	  10	  -1	  -1	  success	  v8.0.0-15501-g59ac66b815-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-79-generic x86_64	  2026-04-05T14:33:22	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing	  102148	  10	  10	  2655	  2669	  0	  1379	  322	  20	  20	  400	  clb	  auto	  -1	  -1	  27249.1	  25039	  65399	  18710	  45272	  1417	  99.8 MiB	  8.77	  0.03	  8.00827	  6.68437	  -64.687	  -6.68437	  nan	  0.46	  0.00738472	  0.00611316	  0.476573	  0.401114	  99.8 MiB	  8.77	  99.8 MiB	  3.96	  80	  44804	  37	  1.74617e+07	  1.6276e+07	  2.09990e+06	  5249.75	  15.07	  3.32004	  2.80176	  51096	  442316	  -1	  38128	  19	  9651	  60450	  2608079	  354629	  7.15969	  nan	  -68.3301	  -7.15969	  0	  0	  2.64110e+06	  6602.75	  0.10	  0.92	  0.36	  -1	  -1	  0.10	  1.0479	  0.896774	 
 k6_frac_N10_40nm.xml	  seq.pre-vpr.blif	  common	  8.38	  vpr	  75.32 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  86	  41	  -1	  -1	  success	  v8.0.0-15501-g59ac66b815-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-79-generic x86_64	  2026-04-05T14:33:22	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing	  77124	  41	  35	  1006	  1041	  0	  637	  162	  12	  12	  144	  clb	  auto	  -1	  -1	  7116.66	  6347	  24417	  6380	  16970	  1067	  75.3 MiB	  2.73	  0.01	  5.49	  4.851	  -139.583	  -4.851	  nan	  0.00	  0.00228337	  0.00191394	  0.152823	  0.129121	  75.3 MiB	  2.73	  75.3 MiB	  1.22	  62	  10266	  25	  5.3894e+06	  4.63488e+06	  554770.	  3852.57	  2.20	  0.838551	  0.709115	  15940	  110000	  -1	  9429	  17	  3975	  18466	  544256	  99694	  5.09346	  nan	  -143.239	  -5.09346	  0	  0	  687181.	  4772.09	  0.03	  0.23	  0.08	  -1	  -1	  0.03	  0.379764	  0.325819	 
