#
############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/arithmetic/generated_circuits/adder_trees/verilog

# Path to directory of architectures to use
archs_dir=arch/timing/fixed_size

# Add circuits to list to sweep

circuit_list_add=adder_tree_2L_004bits.v
circuit_list_add=adder_tree_3L_004bits.v
circuit_list_add=adder_tree_2L_005bits.v
circuit_list_add=adder_tree_3L_005bits.v
circuit_list_add=adder_tree_2L_006bits.v
circuit_list_add=adder_tree_3L_006bits.v
circuit_list_add=adder_tree_2L_007bits.v
circuit_list_add=adder_tree_3L_007bits.v
circuit_list_add=adder_tree_2L_008bits.v
circuit_list_add=adder_tree_3L_008bits.v
circuit_list_add=adder_tree_2L_009bits.v
circuit_list_add=adder_tree_3L_009bits.v
circuit_list_add=adder_tree_2L_010bits.v
circuit_list_add=adder_tree_3L_010bits.v
circuit_list_add=adder_tree_2L_011bits.v
circuit_list_add=adder_tree_3L_011bits.v
circuit_list_add=adder_tree_2L_012bits.v
circuit_list_add=adder_tree_3L_012bits.v
circuit_list_add=adder_tree_2L_013bits.v
circuit_list_add=adder_tree_3L_013bits.v
circuit_list_add=adder_tree_2L_014bits.v
circuit_list_add=adder_tree_3L_014bits.v
circuit_list_add=adder_tree_2L_015bits.v
circuit_list_add=adder_tree_3L_015bits.v
circuit_list_add=adder_tree_2L_016bits.v
circuit_list_add=adder_tree_3L_016bits.v
circuit_list_add=adder_tree_2L_017bits.v
circuit_list_add=adder_tree_3L_017bits.v
circuit_list_add=adder_tree_2L_018bits.v
circuit_list_add=adder_tree_3L_018bits.v
circuit_list_add=adder_tree_2L_019bits.v
circuit_list_add=adder_tree_3L_019bits.v
circuit_list_add=adder_tree_2L_020bits.v
circuit_list_add=adder_tree_3L_020bits.v
circuit_list_add=adder_tree_2L_021bits.v
circuit_list_add=adder_tree_3L_021bits.v
circuit_list_add=adder_tree_2L_022bits.v
circuit_list_add=adder_tree_3L_022bits.v
circuit_list_add=adder_tree_2L_023bits.v
circuit_list_add=adder_tree_3L_023bits.v
circuit_list_add=adder_tree_2L_024bits.v
circuit_list_add=adder_tree_3L_024bits.v
circuit_list_add=adder_tree_2L_028bits.v
circuit_list_add=adder_tree_3L_028bits.v
circuit_list_add=adder_tree_2L_032bits.v
circuit_list_add=adder_tree_3L_032bits.v
circuit_list_add=adder_tree_2L_048bits.v
circuit_list_add=adder_tree_3L_048bits.v
circuit_list_add=adder_tree_2L_064bits.v
circuit_list_add=adder_tree_3L_064bits.v
circuit_list_add=adder_tree_2L_096bits.v
circuit_list_add=adder_tree_3L_096bits.v
circuit_list_add=adder_tree_2L_128bits.v
circuit_list_add=adder_tree_3L_128bits.v

# Add architectures to list to sweep
arch_list_add=fixed_k6_N8_gate_boost_0.2V_22nm.xml
arch_list_add=fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml
arch_list_add=fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml
arch_list_add=fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml
arch_list_add=fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml
arch_list_add=fixed_k6_frac_2ripple_N8_22nm.xml
arch_list_add=fixed_k6_frac_2uripple_N8_22nm.xml
arch_list_add=fixed_k6_frac_N8_22nm.xml
arch_list_add=fixed_k6_frac_ripple_N8_22nm.xml
arch_list_add=fixed_k6_frac_uripple_N8_22nm.xml

# Parse info and how to parse
parse_file=vpr_chain.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

# Pass requirements
pass_requirements_file=pass_requirements_chain_small.txt

script_params=-lut_size 6 -routing_failure_predictor off
