
############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog

# Path to directory of architectures to use
archs_dir=arch/

# Add circuits to list to sweep
circuit_list_add=mkSMAdapter4B.v
circuit_list_add=or1200.v
circuit_list_add=raygentop.v
circuit_list_add=sha.v

# The boundtop.v circuit will not work with architectures without ram blocks. Odin will synthesize large LUTs that will cause a variable to overflow in current version of abc
# It should work with the updated version (change from "char" to "int" which solves overflow problem) 
#circuit_list_add=boundtop.v

# Add architectures to list to sweep
arch_list_add=timing/k6_frac_N10_frac_chain_mem32K_40nm.xml
arch_list_add=bidir/k4_n4_v7_bidir.xml
arch_list_add=complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml

# Parse info and how to parse
parse_file=vpr_fixed_chan_width.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

# Pass requirements
pass_requirements_file= #No pass requirements, since we only care about valgrind results

script_params=-valgrind --route_chan_width 200
