#
############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/system_verilog/f4pga/timer
includes_dir=benchmarks/system_verilog/f4pga/timer

# Path to directory of architectures to use
archs_dir=arch/timing


# Add circuits to list to sweep
include_list_add=modify_count.sv
include_list_add=display_control.sv
include_list_add=time_counter.sv
include_list_add=timer.sv

# Add circuits to list to sweep
#circuit_list_add=flattened_timer.sv
circuit_list_add=clock.sv


# Add architectures to list to sweep
arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml

# Parse info and how to parse
parse_file=vpr_standard.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

# Pass requirements
pass_requirements_file=pass_requirements.txt

#Script parameters
script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang
