%We must be the last document processed by sphinx (to resolve all citations), hence
%the z_ prefix to the filename

@book{betz_arch_cad,
    author = {Betz, Vaughn and Rose, Jonathan and Marquardt, Alexander},
    isbn = {0792384601},
    month = {mar},
    publisher = {Kluwer Academic Publishers},
    title = {Architecture and CAD for Deep-Submicron FPGAs},
    year = {1999},
}

@inproceedings{betz_vpr,
    author = {Betz, Vaughn and Rose, Jonathan},
    title = {VPR: A New Packing, Placement and Routing Tool for FPGA Research},
    booktitle = {Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications},
    series = {FPL '97},
    year = {1997},
    isbn = {3-540-63465-7},
    pages = {213--222},
    numpages = {10},
    doi = {10.1007/3-540-63465-7_226},
    acmid = {738755},
    publisher = {Springer-Verlag},
    address = {London, UK},
}

@phdthesis{betz_phd,
    author = {Betz, Vaughn},
    title = {Architecture and CAD for the Speed and Area Optimization of FPGAs},
    year = {1998},
    school = {University of Toronto},
}

@inproceedings{marquardt_timing_driven_placement,
    author = {Marquardt, Alexander and Betz, Vaughn and Rose, Jonathan},
    title = {Timing-driven Placement for FPGAs},
    booktitle = {Proceedings of the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays},
    series = {FPGA '00},
    year = {2000},
    isbn = {1-58113-193-3},
    location = {Monterey, California, USA},
    pages = {203--213},
    numpages = {11},
    doi = {10.1145/329166.329208},
    acmid = {329208},
    publisher = {ACM},
    address = {New York, NY, USA},
}

@inproceedings{betz_cluster_based_logic_blocks,
    author = {Betz, V. and Rose, J.},
    title = {Cluster-Based Logic Blocks for FPGAs:  Area-Efficiency vs. Input Sharing and Size},
    booktitle={Custom Integrated Circuits Conference},
    pages = {551--554},
    year = {1997},
    doi={10.1109/CICC.1997.606687},
}

@inproceedings{marquardt_timing_driven_packing,
    author = {Marquardt, A and Betz, V. and Rose, J.},
    title = {Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density},
    booktitle = {FPGA},
    pages = {37--46},
    year = {1999},
    doi = {10.1145/296399.296426},
}

@inproceedings{betz_directional_bias_routing_arch,
    author = {Betz, Vaughn and Rose, Jonathan},
    title = {Directional Bias and Non-uniformity in FPGA Global Routing Architectures},
    booktitle = {Proceedings of the 1996 IEEE/ACM International Conference on Computer-aided Design},
    series = {ICCAD '96},
    year = {1996},
    isbn = {0-8186-7597-7},
    location = {San Jose, California, USA},
    pages = {652--659},
    numpages = {8},
    doi = {10.1109/ICCAD.1996.571342},
    acmid = {244948},
    publisher = {IEEE Computer Society},
    address = {Washington, DC, USA},
    keywords = {Field-Programmable Gate Arrays (FPGAs), Global Routing, Placement},
}

@techreport{betz_biased_global_routing_tech_report,
    author = {Betz, Vaughn and Rose, Jonathan},
    title = {On Biased and Non-Uniform Global Routing Architectures and CAD Tools for FPGAs},
    institution = {University of Toronto},
    type = {CSRI Technical Report},
    number = {358},
    year = {1996},
    url = {http://www.eecg.toronto.edu/~vaughn/papers/techrep.pdf},
}

@inproceedings{betz_automatic_generation_of_fpga_routing,
    author = {Betz, Vaughn and Rose, Jonathan},
    title = {Automatic Generation of FPGA Routing Architectures from High-level Descriptions},
    booktitle = {Int. Symp. on Field Programmable Gate Arrays},
    series = {FPGA},
    year = {2000},
    isbn = {1-58113-193-3},
    location = {Monterey, California, USA},
    pages = {175--184},
    numpages = {10},
    doi = {10.1145/329166.329203},
    acmid = {329203},
    publisher = {ACM},
    address = {New York, NY, USA},
}

@book{brown_fpgas,
    author = {Brown, S. and Francis, R. and Rose, J. and Vranesic, Z.},
    title = {Field-Programmable Gate Arrays},
    publisher = {Kluwer Academic Publishers},
    year = {1992},
    isbn = {978-0-7923-9248-4},
}

@phdthesis{wilton_phd,
    author = {Wilton, S.},
    title = {Architectures and Algorithms for Field-Programmable Gate Arrays with Embedded Memories},
    year = {1997},
    school = {University of Toronto},
    url = {http://www.ece.ubc.ca/~stevew/publications.html},
}

@article{chang_universal_switch_modules,
    author = {Chang, Yao-Wen and Wong, D. F. and Wong, C. K.},
    title = {Universal Switch Modules for FPGA Design},
    journal = {ACM Trans. Des. Autom. Electron. Syst.},
    issue_date = {Jan. 1996},
    volume = {1},
    number = {1},
    month = jan,
    year = {1996},
    issn = {1084-4309},
    pages = {80--101},
    numpages = {22},
    doi = {10.1145/225871.225886},
    acmid = {225886},
    publisher = {ACM},
    address = {New York, NY, USA},
}

@inproceedings{lemieux_directional_and_singale_driver_wires,
    author = {Lemieux, G. and Lee, E. and Tom, M. and Yu, A.},
    title = {Direction and Single-Driver Wires in FPGA Interconnect},
    booktitle = {International Conference on Field-Programmable Technology},
    pages = {41--48},
    year = {2004},
    doi = {10.1109/FPT.2004.1393249},
}


@inproceedings{jamieson_odin_II,
    author = {Jamieson, P. and Kent, K. and Gharibian, F. and Shannon, L.},
    title = {Odin II-An Open-Source Verilog HDL Synthesis Tool for CAD Research},
    booktitle = {International Symposium on Field-Programmable Custom Computing Machines},
    pages = {149--156},
    year = {2010},
    doi = {10.1109/FCCM.2010.31},
}

@inproceedings{luu_vtr,
    author = {Rose, Jonathan and Luu, Jason and Yu, Chi Wai and Densmore, Opal and Goeders, Jeffrey and Somerville, Andrew and Kent, Kenneth B. and Jamieson, Peter and Anderson, Jason},
    title = {The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing},
    booktitle = {Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays},
    series = {FPGA '12},
    year = {2012},
    isbn = {978-1-4503-1155-7},
    location = {Monterey, California, USA},
    pages = {77--86},
    numpages = {10},
    doi = {10.1145/2145694.2145708},
    acmid = {2145708},
    publisher = {ACM},
    address = {New York, NY, USA},
}

@article{luu_vtr_7,
    author = {Luu, Jason and Ahmed, Nooruddin and Kent, Kenneth B. and Anderson, Jason and Rose, Jonathan and Betz, Vaughn and Goeders, Jeffrey and Wainberg, Michael and Somerville, Andrew and Yu, Thien and Nasartschuk, Konstantin and Nasr, Miad and Wang, Sen and Liu, Tim},
    doi = {10.1145/2617593},
    issn = {19367406},
    journal = {ACM Transactions on Reconfigurable Technology and Systems},
    keywords = {CAD,FPGA,architecture modeling},
    month = {jun},
    number = {2},
    pages = {1--30},
    publisher = {ACM},
    title = {{VTR 7.0: Next Generation Architecture and CAD System for FPGAs}},
    volume = {7},
    year = {2014},
}

@inproceedings{pistorius_benchmarking_method_fpga_synthesis,
    author = {Pistorius, J. and Hutton, M. and Mishcenko, A. and Brayton, R.},
    title = {Benchmarking method and designs targeting logic synthesis for FPGAs},
    booktitle = {IWLS},
    pages = {230--237},
    year = {2007},
}

@inproceedings{cho_priority_cuts,
    author = {Cho, S. and Chatterjee, S. and Mishcenko, A. and Brayton, R.},
    title = {Efficient FPGA mapping using priority cuts},
    booktitle = {FPGA},
    year = {2007},
}

@misc{abc_cite,
    author = {Berkeley Logic Synthesis and Verification Group},
    title = {ABC: A System for Sequential Synthesis and Verification},
    url = {http://www.eecs.berkeley.edu/~alanmi/abc/},
}

@misc{yosys_cite,
    author = {Clifford Wolf},
    title = {Yosys Open SyYnthesis Suite},
    url = {http://www.clifford.at/yosys/about.html},
}

@inproceedings{lamoureux_activity_estimation,
    author = {Lamoureux, Julien and Wilton, Steven J. E.},
    title = {Activity Estimation for Field-Programmable Gate Arrays},
    booktitle = {International Conference on Field Programmable Logic and Applications},
    pages = {1--8},
    year = {2006},
    doi = {10.1109/FPL.2006.311199},
}

@article{ho_floating_point_fpga,
    author = {Ho, Chun Hok and Yu, Chi Wai and Leong, Philip and Luk, Wayne and Wilton, Steven J. E.},
    title = {Floating-point FPGA: Architecture and Modeling},
    journal = {IEEE Trans. Very Large Scale Integr. Syst.},
    issue_date = {December 2009},
    volume = {17},
    number = {12},
    month = dec,
    year = {2009},
    issn = {1063-8210},
    pages = {1709--1718},
    numpages = {10},
    doi = {10.1109/TVLSI.2008.2006616},
    acmid = {1721479},
    publisher = {IEEE Educational Activities Department},
    address = {Piscataway, NJ, USA},
    keywords = {Architecture, architecture, embedded blocks, field-programmable gate array (FPGA), floating point, modeling},
}

@article{cong_flowmap,
    author={Cong, J. and Ding, Y.},
    journal={Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
    title={FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs},
    year={1994},
    volume={13},
    number={1},
    pages={1-12},
    doi={10.1109/43.273754},
    ISSN={0278-0070},
    month={Jan},
}

@techreport{mcnc_benchmarks,
    author={S. Yang},
    title={{Logic Synthesis and Optimization Benchmarks User Guide 3.0}},
    institution={MCNC},
    year={1991},
}

@article{murray_timing_driven_titan,
    author = {Murray, Kevin E. and Whitty, Scott and Liu, Suya and Luu, Jason and Betz, Vaughn},
    title = {Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap Between Academic and Commercial CAD},
    journal = {ACM Trans. Reconfigurable Technol. Syst.},
    issue_date = {April 2015},
    volume = {8},
    number = {2},
    month = mar,
    year = {2015},
    issn = {1936-7406},
    pages = {10:1--10:18},
    articleno = {10},
    numpages = {18},
    doi = {10.1145/2629579},
    acmid = {2629579},
    publisher = {ACM},
    address = {New York, NY, USA},
    keywords = {Benchmarks, CAD, FPGA},
}

@article{talaei_titan2,
    author = {K. Talaei Khoozani, A. Ahmadian Dehkordi, V. Betz},
    title = {Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture Capture},
    journal = {International Conference on Field-Programmable Logic and Applications},
    year = {2023},
}

@inproceedings{murray_titan,
    author={Murray, K.E. and Whitty, S. and Liu, S. and Luu, J. and Betz, V.},
    booktitle={Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on},
    title={Titan: Enabling large and complex benchmarks in academic CAD},
    year={2013},
    pages={1-8},
    doi={10.1109/FPL.2013.6645503},
    month={Sept},
}

@manual{xilinx_virtex_6_clb,
    title = {Virtex-6 FPGA Configurable Logic Block User Guide},
    organization = {Xilinx Inc},
    edition = {UG364},
    month = {feb},
    year = {2012},
    url = {http://www.xilinx.com/support/documentation/user_guides/ug364.pdf},
}

@inproceedings{luu_architecture_description_lanage,
    author = {Luu, Jason and Anderson, Jason and Rose, Jonathan},
    title = {Architecture Description and Packing for Logic Blocks with Hierarchy, Modes and Complex Interconnect},
    booktitle = {Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays},
    series = {FPGA '11},
    year = {2011},
    isbn = {978-1-4503-0554-9},
    location = {Monterey, CA, USA},
    pages = {227--236},
    numpages = {10},
    doi = {10.1145/1950413.1950457},
    publisher = {ACM},
    address = {New York, NY, USA},
}

@inproceedings{luu_vpr_5,
     author = {Luu, Jason and Kuon, Ian and Jamieson, Peter and Campbell, Ted and Ye, Andy and Fang, Wei Mark and Rose, Jonathan},
     title = {VPR 5.0: FPGA Cad and Architecture Exploration Tools with Single-driver Routing, Heterogeneity and Process Scaling},
     booktitle = {Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays},
     series = {FPGA '09},
     year = {2009},
     isbn = {978-1-60558-410-2},
     location = {Monterey, California, USA},
     pages = {133--142},
     numpages = {10},
     doi = {10.1145/1508128.1508150},
     acmid = {1508150},
     publisher = {ACM},
     address = {New York, NY, USA},
     keywords = {architecture, cad, fpga},
}

@mastersthesis{petelin_masc,
  author       = {Oleg Petelin}, 
  title        = {CAD Tools and Architectures for Improved FPGA Interconnect},
  school       = {University of Toronto},
  year         = 2016,
  url          = {http://hdl.handle.net/1807/75854}
}

@ARTICLE{minimax_pert, 
	author={H. Youssef and R. B. Lin and E. Shragowitz}, 
	journal={IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing}, 
	title={Bounds on net delays for VLSI circuits}, 
	year={1992}, 
	volume={39}, 
	number={11}, 
	pages={815-824}, 
	keywords={VLSI;convergence of numerical methods;delays;digital integrated circuits;iterative methods;minimax techniques;IMP;MIMP;VLSI circuits;iterative minimax-PERT;net delay bounds;polynomial-time algorithm;time efficiency;Capacitance;Circuit optimization;Clocks;Integrated circuit interconnections;Logic circuits;Logic devices;Propagation delay;Sorting;Timing;Very large scale integration}, 
	doi={10.1109/82.204129}, 
	ISSN={1057-7130}, 
	month={Nov},
}


@ARTICLE{RCV_algorithm, 
	author={R. Fung and V. Betz and W. Chow}, 
	journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, 
	title={Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations}, 
	year={2008}, 
	volume={27}, 
	number={4}, 
	pages={686-697}, 
	keywords={field programmable gate arrays;integrated circuit interconnections;network routing;peripheral interfaces;FPGA timing;circuit connection;connection-delay constraint;field-programmable gate array;long-path timing;peripheral component interconnect;routing cost valley;short-path timing;short-path violation;slack allocation;Circuit testing;Constraint optimization;Cost function;Delay;Design automation;Design optimization;Field programmable gate arrays;Integrated circuit interconnections;Routing;Timing;Field-programmable gate array (FPGA);routing;slack allocation;timing}, 
	doi={10.1109/TCAD.2008.917585}, 
	ISSN={0278-0070}, 
	month={April},
	}

@INPROCEEDINGS{chiasson_coffe,
    author={C. Chiasson and V. Betz},
    booktitle={2013 International Conference on Field-Programmable Technology (FPT)},
    title={COFFE: Fully-automated transistor sizing for FPGAs},
    year={2013},
    volume={},
    number={},
    pages={34-41},
    keywords={circuit CAD;circuit layout CAD;circuit optimisation;field programmable gate arrays;integrated circuit layout;network routing;SPICE;COFFE;circuit optimization;FPGA exploration;fully automated transistor sizing tool;automated transistor level CAD tools;architecture exploration flow;transistor modeling;circuit nonlinearity;HSPICE simulation;delay measurement;layout effect;logic-to-routing interface;Transistors;Field programmable gate arrays;Delays;Integrated circuit modeling;Layout;Resistance;Switching circuits},
    doi={10.1109/FPT.2013.6718327},
    ISSN={},
    month={Dec},
}

@INPROCEEDINGS{murray_air,
    author={K. E. Murray and S. Zhong and V. Betz},
    booktitle={To appear in Asia Pacific Design Automation Conference (ASP-DAC)},
    title={AIR: A Fast but Lazy Timing-Driven FPGA Router},
    year={2020},
    doi={}
}

@mastersthesis{mustafa_masc,
  author       = {Mustafa Abbas}, 
  title        = {System Level Communication Challenges of Large FPGAs},
  school       = {University of Toronto},
  year         = 2019,
  url          = {https://tspace.library.utoronto.ca/bitstream/1807/97807/3/Abbas_Mustafa_S_201911_MSc_thesis.pdf}
}


@ARTICLE{murray_micro_symbiflow,  author={K. E. {Murray} and T. {Ansell} and K. {Rothman} and A. {Comodi} and M. {Elgammal} and V. {Betz}},  
        journal={IEEE Micro},   
	title={Symbiflow & VPR: An Open-Source Design Flow for Commercial and Novel FPGAs},
	year={2020},
	volume={},
	number={},
	pages={1-1}
}

@inproceedings{koios_benchmarks,
  title={Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research},
  author={Arora, Aman and Boutros, Andrew and Rauch, Daniel and Rajen, Aishwarya and Borda, Aatman and Damghani, Seyed A. and Mehta, Samidh and Kate, Sangram and Patel, Pragnesh and Kent, Kenneth B. and Betz, Vaughn and John, Lizy K.},
  booktitle={International Conference on Field Programmable Logic and Applications (FPL)},
  year={2021}
}

@inproceedings{kosar2024parallel,
  title={Parallel FPGA Routing with On-the-Fly Net Decomposition},
  author={Kosar, Fahrican and Stojilovic, Mirjana and Betz, Vaughn},
  booktitle={The 23rd International Conference on Field-Programmable Technology},
  year={2024}
}

@ARTICLE{Viswanathan2005_FastPlace,
    author={Viswanathan, N. and Chu, C.C.-N.},
    journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
    title={{FastPlace}: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model},
    year={2005},
    volume={24},
    number={5},
    month=may,
    pages={722-733},
    keywords={Clustering algorithms;Partitioning algorithms;Algorithm design and analysis;Integrated circuit interconnections;Large-scale systems;Minimization;Delay;Simulated annealing;Iterative algorithms;Acceleration;Analytical placement;computer-aided design;net models;standard cell placement},
    doi={10.1109/TCAD.2005.846365}
}

@article{Kim2013_SimPL,
    author = {Kim, Myung-Chul and Lee, Dong-Jin and Markov, Igor L.},
    journal = {Communications of the ACM},
    title = {{SimPL}: an algorithm for placing {VLSI} circuits},
    year = {2013},
    issue_date = {June 2013},
    publisher = {Association for Computing Machinery},
    address = {New York, NY, USA},
    volume = {56},
    number = {6},
    issn = {0001-0782},
    doi = {10.1145/2461256.2461279},
    month = jun,
    pages = {105–113},
    numpages = {9}
}

@ARTICLE{Spindler2008_Kraftwerk2,
    author={Spindler, Peter and Schlichtmann, Ulf and Johannes, Frank M.},
    journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
    title={Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model},
    year={2008},
    volume={27},
    number={8},
    month=aug,
    pages={1398-1411},
    keywords={Cost function;Central Processing Unit;Runtime;Quality control;Convergence;Computational efficiency;Integrated circuit synthesis;Stochastic processes;Circuit simulation;Bound2Bound;force-directed;half-perimeter wirelength (HPWL);Kraftwerk2;quadratic placement;Kraftwerk2;force-directed;quadratic placement;Bound2Bound;HPWL},
    doi={10.1109/TCAD.2008.925783}
}

@INPROCEEDINGS{XTang_FPT_2019,
    author={X. Tang and E. Giacomin and A. Alacchi and P. Gaillardon},  
    booktitle={2019 International Conference on Field-Programmable Technology (ICFPT)}, 
    title={A Study on Switch Block Patterns for Tileable FPGA Routing Architectures},
    year={2019},
    volume={},
    number={},
    pages={247-250},
    doi={10.1109/ICFPT47387.2019.00039}
}
