arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	
k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml	ch_intrinsics.v	common	2.67	vpr	67.35 MiB		-1	-1	0.20	21084	3	0.07	-1	-1	32716	-1	-1	68	99	1	0	success	v8.0.0-14178-g4818739e3-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-71-generic x86_64	2025-10-15T12:13:40	betzgrp-wintermute	/home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow	68968	99	130	344	474	1	216	298	13	13	169	clb	auto	27.5 MiB	0.76	1801.61	1046	146563	61460	19152	65951	67.4 MiB	0.15	0.00	22	1841	22	0	0	324418.	1919.63	0.75	
