arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
k6_frac_N10_frac_chain_mem32K_40nm.xml	ch_intrinsics.v	common	214.19	-	-		6.74	-1	-1	-1	3	31.59	-1	-1	-1	-1	-1	68	99	1	0	success	v8.0.0-11925-ga544f5fea-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2025-01-14T21:35:49	betzgrp-wintermute.eecg.utoronto.ca	/home/elgamma8/research/release/vtr-verilog-to-routing	-1	99	130	363	493	1	251	298	12	12	144	clb	auto	315.5 MiB	16.63	825	66963	24629	31658	10676	375.0 MiB	16.45	0.29	2.18081	-216.806	-2.18081	2.18081	11.68	0.0738834	0.069041	5.19912	4.84873	-1	-1	-1	-1	42	1542	18	5.66058e+06	4.21279e+06	345696.	2400.67	39.10	15.39	13.8531	13090	66981	-1	1416	8	543	745	35361	11414	2.49575	2.49575	-234.092	-2.49575	0	0	434636.	3018.30	1.10	3.44	6.11	-1	-1	1.10	1.69917	1.5038	
k6_frac_N10_frac_chain_mem32K_40nm.xml	stereovision3.v	common	185.29	-	-		7.24	-1	-1	-1	5	21.35	-1	-1	-1	-1	-1	14	11	0	0	success	v8.0.0-11925-ga544f5fea-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2025-01-14T21:35:49	betzgrp-wintermute.eecg.utoronto.ca	/home/elgamma8/research/release/vtr-verilog-to-routing	-1	11	30	313	321	2	115	55	7	7	49	clb	auto	318.7 MiB	19.99	456	2239	413	1740	86	377.4 MiB	3.57	0.10	2.65898	-171.948	-2.65898	2.30209	2.96	0.064002	0.0582579	1.57937	1.43364	-1	-1	-1	-1	30	934	29	1.07788e+06	754516	77114.5	1573.76	17.77	10.2264	8.76037	3660	13876	-1	783	19	469	889	29198	10184	2.65817	2.36697	-188.291	-2.65817	0	0	95414.1	1947.23	0.24	4.44	1.68	-1	-1	0.24	2.66573	2.27986	
