 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  routed_wirelength	  avg_routed_wirelength	  routed_wiresegment	  avg_routed_wiresegment	  total_nets_routed	  total_connections_routed	  total_heap_pushes	  total_heap_pops	  logic_block_area_total	  logic_block_area_used	  routing_area_total	  routing_area_per_tile	  crit_path_route_success_iteration	  num_rr_graph_nodes	  num_rr_graph_edges	  collapsed_nodes	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  create_rr_graph_time	  create_intra_cluster_rr_graph_time	  adding_internal_edges	  route_mem	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  router_lookahead_mem	  tile_lookahead_computation_time	  router_lookahead_computation_time	 
 k6_frac_N10_40nm.xml	  alu4.pre-vpr.blif	  common_--anneal_auto_init_t_estimator_cost_variance	  1.46	  vpr	  67.86 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  80	  14	  -1	  -1	  success	  v8.0.0-13899-ga7bc5a9ac4-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-63-generic x86_64	  2025-09-15T16:37:21	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_init_t_est	  69488	  14	  8	  926	  934	  0	  489	  102	  11	  11	  121	  clb	  auto	  28.8 MiB	  0.84	  5716.94	  4650	  6290	  949	  5130	  211	  67.9 MiB	  0.16	  0.01	  5.1758	  4.43071	  -31.9321	  -4.43071	  nan	  0.12	  0.00167764	  0.00130992	  0.0602339	  0.0501067	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  14211	  106557	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  0.10	  -1	  -1	  -1	  -1	  0.0630981	  0.052547	  67.9 MiB	  -1	  0.02	 
 k6_frac_N10_40nm.xml	  alu4.pre-vpr.blif	  common_--anneal_auto_init_t_estimator_equilibrium	  1.71	  vpr	  67.98 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  80	  14	  -1	  -1	  success	  v8.0.0-13899-ga7bc5a9ac4-dirty	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-63-generic x86_64	  2025-09-15T16:37:21	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_init_t_est	  69616	  14	  8	  926	  934	  0	  489	  102	  11	  11	  121	  clb	  auto	  28.8 MiB	  0.83	  5716.94	  4541	  17952	  6407	  10914	  631	  68.0 MiB	  0.42	  0.01	  5.1758	  4.4692	  -32.2422	  -4.4692	  nan	  0.13	  0.00161496	  0.00126113	  0.143885	  0.116212	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  14211	  106557	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  0.10	  -1	  -1	  -1	  -1	  0.146786	  0.118689	  68.0 MiB	  -1	  0.02	 
