arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	routed_wirelength	avg_routed_wirelength	routed_wiresegment	avg_routed_wiresegment	total_nets_routed	total_connections_routed	total_heap_pushes	total_heap_pops	logic_block_area_total	logic_block_area_used	routing_area_total	routing_area_per_tile	crit_path_route_success_iteration	num_rr_graph_nodes	num_rr_graph_edges	collapsed_nodes	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	create_rr_graph_time	create_intra_cluster_rr_graph_time	adding_internal_edges	route_mem	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	router_lookahead_mem	tile_lookahead_computation_time	router_lookahead_computation_time	
fix_clusters_multiple_clb.xml	apex2.blif	common	3.33	vpr	102.20 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	38	-1	-1	success	v8.0.0-14974-gfcbd7407d-dirty	release VTR_ASSERT_LEVEL=3	GNU 13.3.0 on Linux-6.14.0-33-generic x86_64	2026-01-21T13:24:46	alex-ThinkPad-X1-Carbon-Gen-9	/home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_lb_constr_floorplan	104648	38	3	1916	1919	0	1539	690	46	46	2116	-1	fixed_device	35.7 MiB	0.16	54457.6	23602	305390	130742	168076	6572	102.2 MiB	1.44	0.01	24.1264	11.3001	-33.0485	-11.3001	nan	0.00	0.00151374	0.00118119	0.188663	0.153114	-1	-1	-1	-1	26791	17.4081	26791	17.4081	10626	37633	3411434	672544	4.31593e+06	1.44684e+06	8.72079e+06	4121.36	15	291456	1125920	-1	11.1406	nan	-32.6427	-11.1406	0	0	0.70	-1	-1	102.2 MiB	0.54	0.277872	0.231444	102.2 MiB	-1	0.17	
