 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 k6_N10_40nm.xml	  stereovision0.v	  common	  84.44	  vpr	  258.36 MiB	  	  -1	  -1	  7.61	  115532	  5	  28.76	  -1	  -1	  64396	  -1	  -1	  1378	  169	  -1	  -1	  success	  v8.0.0-13084-g071ad3865	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-17T09:37:40	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  264556	  169	  197	  21353	  21550	  1	  6641	  1744	  40	  40	  1600	  clb	  auto	  135.1 MiB	  3.48	  196708	  51356	  956607	  332385	  618180	  6042	  258.4 MiB	  7.14	  0.08	  9.18492	  4.32372	  -15503.9	  -4.32372	  4.32372	  3.90	  0.0187118	  0.0161524	  2.08853	  1.72888	  -1	  -1	  -1	  -1	  44	  63796	  30	  2.5992e+07	  2.4804e+07	  5.10802e+06	  3192.51	  23.15	  11.0421	  9.28483	  131640	  1069382	  -1	  60179	  20	  29917	  64027	  2547181	  435178	  4.35716	  4.35716	  -16011.8	  -4.35716	  0	  0	  6.61527e+06	  4134.55	  0.22	  1.62	  0.62	  -1	  -1	  0.22	  1.16804	  1.03413	 
 k6_N10_40nm_diff_switch_for_inc_dec_wires.xml	  stereovision0.v	  common	  72.74	  vpr	  256.24 MiB	  	  -1	  -1	  7.53	  116476	  5	  30.52	  -1	  -1	  64100	  -1	  -1	  1395	  169	  -1	  -1	  success	  v8.0.0-13084-g071ad3865	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-17T09:37:40	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  262388	  169	  197	  21353	  21550	  1	  6728	  1761	  40	  40	  1600	  clb	  auto	  134.8 MiB	  3.61	  205172	  50539	  969091	  336531	  626663	  5897	  256.2 MiB	  6.71	  0.07	  8.95263	  3.6351	  -14948.7	  -3.6351	  3.6351	  3.75	  0.0164354	  0.0141333	  1.86643	  1.55502	  -1	  -1	  -1	  -1	  42	  63541	  25	  7.78246e+07	  7.51837e+07	  4.73427e+06	  2958.92	  10.50	  6.83646	  5.75012	  128444	  955862	  -1	  60652	  21	  31702	  71662	  2611248	  481245	  3.48804	  3.48804	  -15540.5	  -3.48804	  0	  0	  5.90781e+06	  3692.38	  0.21	  1.70	  0.56	  -1	  -1	  0.21	  1.20231	  1.05929	 
