//Verilog generated by VPR 8.1.0-dev+684ecc193 from post-place-and-route implementation
module unconnected (
    input \a[0] ,
    input \a[1] ,
    input \a[2] ,
    input \a[3] ,
    input \b[0] ,
    input \b[1] ,
    input \b[2] ,
    input \b[3] ,
    input \b[4] ,
    input \b[5] ,
    input \b[6] ,
    input \b[7] ,
    output \o[0] ,
    output \o[1] ,
    output \o[2] ,
    output \o[3] ,
    output \o[4] ,
    output \o[5] ,
    output \o[6] ,
    output \o[7] 
);

    //Wires
    wire \a[0]_output_0_0 ;
    wire \a[1]_output_0_0 ;
    wire \a[2]_output_0_0 ;
    wire \a[3]_output_0_0 ;
    wire \b[0]_output_0_0 ;
    wire \b[1]_output_0_0 ;
    wire \b[2]_output_0_0 ;
    wire \b[3]_output_0_0 ;
    wire \b[4]_output_0_0 ;
    wire \b[5]_output_0_0 ;
    wire \b[6]_output_0_0 ;
    wire \b[7]_output_0_0 ;
    wire \dsp_inst_output_0_0 ;
    wire \dsp_inst_output_0_1 ;
    wire \dsp_inst_output_0_2 ;
    wire \dsp_inst_output_0_3 ;
    wire \dsp_inst_output_0_4 ;
    wire \dsp_inst_output_0_5 ;
    wire \dsp_inst_output_0_6 ;
    wire \dsp_inst_output_0_7 ;
    wire \dsp_inst_input_0_0 ;
    wire \dsp_inst_input_0_1 ;
    wire \dsp_inst_input_0_2 ;
    wire \dsp_inst_input_0_3 ;
    wire \dsp_inst_input_1_0 ;
    wire \dsp_inst_input_1_1 ;
    wire \dsp_inst_input_1_2 ;
    wire \dsp_inst_input_1_3 ;
    wire \dsp_inst_input_1_4 ;
    wire \dsp_inst_input_1_5 ;
    wire \dsp_inst_input_1_6 ;
    wire \dsp_inst_input_1_7 ;
    wire \o[0]_input_0_0 ;
    wire \o[1]_input_0_0 ;
    wire \o[2]_input_0_0 ;
    wire \o[3]_input_0_0 ;
    wire \o[4]_input_0_0 ;
    wire \o[5]_input_0_0 ;
    wire \o[6]_input_0_0 ;
    wire \o[7]_input_0_0 ;

    //IO assignments
    assign \o[0]  = \o[0]_input_0_0 ;
    assign \o[1]  = \o[1]_input_0_0 ;
    assign \o[2]  = \o[2]_input_0_0 ;
    assign \o[3]  = \o[3]_input_0_0 ;
    assign \o[4]  = \o[4]_input_0_0 ;
    assign \o[5]  = \o[5]_input_0_0 ;
    assign \o[6]  = \o[6]_input_0_0 ;
    assign \o[7]  = \o[7]_input_0_0 ;
    assign \a[0]_output_0_0  = \a[0] ;
    assign \a[1]_output_0_0  = \a[1] ;
    assign \a[2]_output_0_0  = \a[2] ;
    assign \a[3]_output_0_0  = \a[3] ;
    assign \b[0]_output_0_0  = \b[0] ;
    assign \b[1]_output_0_0  = \b[1] ;
    assign \b[2]_output_0_0  = \b[2] ;
    assign \b[3]_output_0_0  = \b[3] ;
    assign \b[4]_output_0_0  = \b[4] ;
    assign \b[5]_output_0_0  = \b[5] ;
    assign \b[6]_output_0_0  = \b[6] ;
    assign \b[7]_output_0_0  = \b[7] ;

    //Interconnect
    fpga_interconnect \routing_segment_a[0]_output_0_0_to_dsp_inst_input_0_0  (
        .datain(\a[0]_output_0_0 ),
        .dataout(\dsp_inst_input_0_0 )
    );

    fpga_interconnect \routing_segment_a[1]_output_0_0_to_dsp_inst_input_0_1  (
        .datain(\a[1]_output_0_0 ),
        .dataout(\dsp_inst_input_0_1 )
    );

    fpga_interconnect \routing_segment_a[2]_output_0_0_to_dsp_inst_input_0_2  (
        .datain(\a[2]_output_0_0 ),
        .dataout(\dsp_inst_input_0_2 )
    );

    fpga_interconnect \routing_segment_a[3]_output_0_0_to_dsp_inst_input_0_3  (
        .datain(\a[3]_output_0_0 ),
        .dataout(\dsp_inst_input_0_3 )
    );

    fpga_interconnect \routing_segment_b[0]_output_0_0_to_dsp_inst_input_1_0  (
        .datain(\b[0]_output_0_0 ),
        .dataout(\dsp_inst_input_1_0 )
    );

    fpga_interconnect \routing_segment_b[1]_output_0_0_to_dsp_inst_input_1_1  (
        .datain(\b[1]_output_0_0 ),
        .dataout(\dsp_inst_input_1_1 )
    );

    fpga_interconnect \routing_segment_b[2]_output_0_0_to_dsp_inst_input_1_2  (
        .datain(\b[2]_output_0_0 ),
        .dataout(\dsp_inst_input_1_2 )
    );

    fpga_interconnect \routing_segment_b[3]_output_0_0_to_dsp_inst_input_1_3  (
        .datain(\b[3]_output_0_0 ),
        .dataout(\dsp_inst_input_1_3 )
    );

    fpga_interconnect \routing_segment_b[4]_output_0_0_to_dsp_inst_input_1_4  (
        .datain(\b[4]_output_0_0 ),
        .dataout(\dsp_inst_input_1_4 )
    );

    fpga_interconnect \routing_segment_b[5]_output_0_0_to_dsp_inst_input_1_5  (
        .datain(\b[5]_output_0_0 ),
        .dataout(\dsp_inst_input_1_5 )
    );

    fpga_interconnect \routing_segment_b[6]_output_0_0_to_dsp_inst_input_1_6  (
        .datain(\b[6]_output_0_0 ),
        .dataout(\dsp_inst_input_1_6 )
    );

    fpga_interconnect \routing_segment_b[7]_output_0_0_to_dsp_inst_input_1_7  (
        .datain(\b[7]_output_0_0 ),
        .dataout(\dsp_inst_input_1_7 )
    );

    fpga_interconnect \routing_segment_dsp_inst_output_0_0_to_o[0]_input_0_0  (
        .datain(\dsp_inst_output_0_0 ),
        .dataout(\o[0]_input_0_0 )
    );

    fpga_interconnect \routing_segment_dsp_inst_output_0_1_to_o[1]_input_0_0  (
        .datain(\dsp_inst_output_0_1 ),
        .dataout(\o[1]_input_0_0 )
    );

    fpga_interconnect \routing_segment_dsp_inst_output_0_2_to_o[2]_input_0_0  (
        .datain(\dsp_inst_output_0_2 ),
        .dataout(\o[2]_input_0_0 )
    );

    fpga_interconnect \routing_segment_dsp_inst_output_0_3_to_o[3]_input_0_0  (
        .datain(\dsp_inst_output_0_3 ),
        .dataout(\o[3]_input_0_0 )
    );

    fpga_interconnect \routing_segment_dsp_inst_output_0_4_to_o[4]_input_0_0  (
        .datain(\dsp_inst_output_0_4 ),
        .dataout(\o[4]_input_0_0 )
    );

    fpga_interconnect \routing_segment_dsp_inst_output_0_5_to_o[5]_input_0_0  (
        .datain(\dsp_inst_output_0_5 ),
        .dataout(\o[5]_input_0_0 )
    );

    fpga_interconnect \routing_segment_dsp_inst_output_0_6_to_o[6]_input_0_0  (
        .datain(\dsp_inst_output_0_6 ),
        .dataout(\o[6]_input_0_0 )
    );

    fpga_interconnect \routing_segment_dsp_inst_output_0_7_to_o[7]_input_0_0  (
        .datain(\dsp_inst_output_0_7 ),
        .dataout(\o[7]_input_0_0 )
    );


    //Unconnected wires
    wire \__vpr__unconn0 ;
    wire \__vpr__unconn1 ;
    wire \__vpr__unconn2 ;
    wire \__vpr__unconn3 ;
    wire \__vpr__unconn4 ;
    wire \__vpr__unconn5 ;
    wire \__vpr__unconn6 ;
    wire \__vpr__unconn7 ;

    //Cell instances
    dsp \dsp_inst  (
        .a({
            1'b0,
            1'b0,
            1'b0,
            1'b0,
            \dsp_inst_input_0_3 ,
            \dsp_inst_input_0_2 ,
            \dsp_inst_input_0_1 ,
            \dsp_inst_input_0_0 
         }),
        .addsub(1'b0),
        .b({
            \dsp_inst_input_1_7 ,
            \dsp_inst_input_1_6 ,
            \dsp_inst_input_1_5 ,
            \dsp_inst_input_1_4 ,
            \dsp_inst_input_1_3 ,
            \dsp_inst_input_1_2 ,
            \dsp_inst_input_1_1 ,
            \dsp_inst_input_1_0 
         }),
        .carry(),
        .out({
            __vpr__unconn0,
            __vpr__unconn1,
            __vpr__unconn2,
            __vpr__unconn3,
            __vpr__unconn4,
            __vpr__unconn5,
            __vpr__unconn6,
            __vpr__unconn7,
            \dsp_inst_output_0_7 ,
            \dsp_inst_output_0_6 ,
            \dsp_inst_output_0_5 ,
            \dsp_inst_output_0_4 ,
            \dsp_inst_output_0_3 ,
            \dsp_inst_output_0_2 ,
            \dsp_inst_output_0_1 ,
            \dsp_inst_output_0_0 
         })
    );


endmodule
