 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  num_io	  num_LAB	  num_DSP	  num_M9K	  num_M144K	  num_PLL	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  routed_wirelength	  avg_routed_wirelength	  routed_wiresegment	  avg_routed_wiresegment	  total_nets_routed	  total_connections_routed	  total_heap_pushes	  total_heap_pops	  logic_block_area_total	  logic_block_area_used	  routing_area_total	  routing_area_per_tile	  crit_path_route_success_iteration	  num_rr_graph_nodes	  num_rr_graph_edges	  collapsed_nodes	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  create_rr_graph_time	  create_intra_cluster_rr_graph_time	  adding_internal_edges	  route_mem	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  router_lookahead_mem	  tile_lookahead_computation_time	  router_lookahead_computation_time	 
 stratixiv_arch.timing.xml	  neuron_stratixiv_arch_timing.blif	  common	  875.57	  vpr	  2.85 GiB	  	  77	  3136	  89	  136	  0	  0	  success	  v8.0.0-11925-ga544f5fea-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2025-01-14T21:35:49	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  2992920	  42	  35	  119888	  86875	  1	  50816	  3438	  129	  96	  12384	  DSP	  auto	  1747.3 MiB	  113.44	  582667	  3141815	  1177622	  1941316	  22877	  2922.8 MiB	  131.76	  0.97	  8.30634	  -81008.6	  -7.30634	  5.71368	  0.07	  0.390966	  0.330249	  50.2947	  42.4929	  753664	  14.8455	  159283	  3.13753	  108681	  189329	  132420316	  35517631	  0	  0	  2.28639e+08	  18462.4	  18	  3593250	  39165143	  -1	  8.74065	  6.13717	  -112227	  -7.74065	  0	  0	  78.47	  -1	  -1	  2922.8 MiB	  45.38	  68.7408	  59.0089	  2922.8 MiB	  -1	  22.64	 
