arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	routed_wirelength	avg_routed_wirelength	routed_wiresegment	avg_routed_wiresegment	total_nets_routed	total_connections_routed	total_heap_pushes	total_heap_pops	logic_block_area_total	logic_block_area_used	routing_area_total	routing_area_per_tile	crit_path_route_success_iteration	num_rr_graph_nodes	num_rr_graph_edges	collapsed_nodes	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	create_rr_graph_time	create_intra_cluster_rr_graph_time	adding_internal_edges	route_mem	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	router_lookahead_mem	tile_lookahead_computation_time	router_lookahead_computation_time	
7series_BRAM_DSP_carry.xml	tpu_like.small.os.v	common	482.26	vpr	2.65 GiB		-1	-1	12.12	231732	5	68.45	-1	-1	135120	-1	-1	-1	355	32	-1	success	6527d14ed	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.8.0-84-generic x86_64	2026-03-14T16:18:18	KingsLanding	/home/pliebste/vtr-verilog-to-routing	2781900	355	289	47735	39422	2	26399	3216	114	114	12996	DSP	auto	352.3 MiB	99.61	1.26781e+06	431996	2874304	1009148	1848198	16958	2716.7 MiB	51.91	0.48	10.1064	7.32617	-81122.9	-7.32617	7.32617	0.19	0.0323373	0.0264186	4.02422	3.34426	-1	-1	-1	-1	414576	15.7102	130575	4.94808	41818	86740	29364828	6810402	7.77041e+08	2.42946e+08	2.49544e+08	19201.6	8	4332056	104637696	-1	6.6148	6.6148	-103569	-6.6148	-205.508	-0.04	62.45	-1	-1	2716.7 MiB	8.65	5.30371	4.52578	2716.7 MiB	-1	166.90	
