arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	num_io	num_LAB	num_DSP	num_M9K	num_M144K	num_PLL	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	routed_wirelength	avg_routed_wirelength	routed_wiresegment	avg_routed_wiresegment	total_nets_routed	total_connections_routed	total_heap_pushes	total_heap_pops	logic_block_area_total	logic_block_area_used	routing_area_total	routing_area_per_tile	crit_path_route_success_iteration	num_rr_graph_nodes	num_rr_graph_edges	collapsed_nodes	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	create_rr_graph_time	create_intra_cluster_rr_graph_time	adding_internal_edges	route_mem	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	router_lookahead_mem	tile_lookahead_computation_time	router_lookahead_computation_time	
3d_SB_inter_die_stratixiv_arch.timing.xml	ucsb_152_tap_fir_stratixiv_arch_timing.blif	common	58.45	vpr	1.18 GiB		42	749	0	0	0	0	success	v8.0.0-15148-g1c7a53e38-dirty	release VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-60-generic x86_64	2026-01-31T21:09:03	soheil-pt372	/home/soheil/vtr/vtr-verilog-to-routing/vtr_flow	1238720	13	29	26295	20086	1	12646	791	29	21	1218	LAB	auto	1085.8 MiB	12.64	177076	68135	278647	63788	197413	17446	1183.2 MiB	10.65	0.12	5.46831	4.99915	-5435.3	-3.99915	2.82147	0.01	0.0318636	0.0278711	2.49999	2.03773	80107	6.33557	20042	1.58510	26822	37589	10613194	1880768	0	0	2.40334e+07	19731.9	15	361688	4148564	-1	5.24076	2.63649	-5368.26	-4.24076	0	0	5.14	-1	-1	1183.2 MiB	3.65	3.80117	3.20182	1183.2 MiB	-1	7.08	
3d_bidir_SB_inter_die_stratixiv_arch.timing.xml	ucsb_152_tap_fir_stratixiv_arch_timing.blif	common	59.37	vpr	1.18 GiB		42	749	0	0	0	0	success	v8.0.0-15148-g1c7a53e38-dirty	release VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-60-generic x86_64	2026-01-31T21:09:03	soheil-pt372	/home/soheil/vtr/vtr-verilog-to-routing/vtr_flow	1238232	13	29	26295	20086	1	12646	791	29	21	1218	LAB	auto	1084.7 MiB	12.89	177076	64662	282303	64791	202778	14734	1182.5 MiB	10.93	0.13	5.52088	5.10407	-5477.89	-4.10407	2.75992	0.01	0.0266307	0.0230129	2.52487	2.06002	78122	6.17858	19576	1.54824	26918	38240	11847473	2170247	0	0	2.40637e+07	19756.7	15	361688	4175348	-1	5.22462	2.6495	-5469.96	-4.22462	0	0	5.43	-1	-1	1182.5 MiB	4.04	3.85067	3.24382	1182.5 MiB	-1	6.74	
