#
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# Configuration file for running experiments
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# Path to directory of circuits to use
circuits_dir=benchmarks/verilog

# Path to directory of architectures to use
archs_dir=arch/timing

# Add circuits to list to sweep
circuit_list_add=sha.v 
circuit_list_add=stereovision3.v 

# Add architectures to list to sweep
arch_list_add=k6_frac_N10_40nm.xml

# Parse info and how to parse
parse_file=vpr_fixed_chan_width.txt

# How to parse QoR info
qor_parse_file=qor_standard.txt

# Pass requirements
pass_requirements_file=pass_requirements_fixed_chan_width.txt

#Script parameters
script_params= -start odin --route_chan_width 200 --gen_post_synthesis_netlist on -track_memory_usage -check_equivalent --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off
