 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_le	  num_luts	  num_add_blocks	  max_add_chain_length	  num_sub_blocks	  max_sub_chain_length	 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml	  diffeq2.v	  common	  16.79	  vpr	  67.83 MiB	  	  0.08	  9652	  -1	  -1	  6	  0.16	  -1	  -1	  34060	  -1	  -1	  15	  66	  0	  -1	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  69456	  66	  96	  1000	  687	  1	  578	  192	  18	  18	  324	  mult_27	  auto	  28.6 MiB	  1.69	  5343	  48856	  15321	  28109	  5426	  67.8 MiB	  0.58	  0.01	  16.5319	  -985.557	  -16.5319	  16.5319	  1.33	  0.00284838	  0.00269661	  0.271323	  0.256526	  -1	  -1	  -1	  -1	  56	  12644	  31	  6.4517e+06	  1.13409e+06	  1.55150e+06	  4788.57	  8.30	  0.994052	  0.922886	  50684	  323660	  -1	  11612	  24	  4774	  11145	  2601588	  732828	  16.8532	  16.8532	  -1120.15	  -16.8532	  0	  0	  1.95585e+06	  6036.58	  0.72	  0.84	  0.31	  -1	  -1	  0.72	  0.163283	  0.153391	  133	  202	  146	  33	  66	  33	 
