 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 k6_frac_N10_frac_chain_mem32K_40nm.xml	  multiclock.blif	  common_--timing_report_detail_netlist	  0.68	  vpr	  65.00 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  5	  0	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  66556	  5	  3	  11	  14	  2	  9	  10	  4	  4	  16	  clb	  auto	  26.3 MiB	  0.02	  20	  30	  10	  17	  3	  65.0 MiB	  0.01	  0.00	  0.619658	  -3.41326	  -0.619658	  0.545	  0.01	  3.9442e-05	  2.8479e-05	  0.000264801	  0.000213415	  -1	  -1	  -1	  -1	  20	  15	  1	  107788	  107788	  10441.3	  652.579	  0.05	  0.00220927	  0.00202353	  750	  1675	  -1	  15	  1	  7	  7	  94	  62	  0.562699	  0.545	  -3.33969	  -0.562699	  0	  0	  13752.8	  859.551	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00165203	  0.0015765	 
 k6_frac_N10_frac_chain_mem32K_40nm.xml	  multiclock.blif	  common_--timing_report_detail_aggregated	  0.64	  vpr	  64.77 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  5	  0	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  66324	  5	  3	  11	  14	  2	  9	  10	  4	  4	  16	  clb	  auto	  26.0 MiB	  0.02	  20	  30	  10	  17	  3	  64.8 MiB	  0.01	  0.00	  0.619658	  -3.41326	  -0.619658	  0.545	  0.01	  4.7331e-05	  3.4794e-05	  0.000313679	  0.000255977	  -1	  -1	  -1	  -1	  20	  15	  1	  107788	  107788	  10441.3	  652.579	  0.02	  0.00210853	  0.00193266	  750	  1675	  -1	  15	  1	  7	  7	  94	  62	  0.562699	  0.545	  -3.33969	  -0.562699	  0	  0	  13752.8	  859.551	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.0016735	  0.00159778	 
 k6_frac_N10_frac_chain_mem32K_40nm.xml	  multiclock.blif	  common_--timing_report_detail_detailed	  0.70	  vpr	  64.80 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  5	  0	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  66360	  5	  3	  11	  14	  2	  9	  10	  4	  4	  16	  clb	  auto	  26.0 MiB	  0.03	  20	  30	  10	  17	  3	  64.8 MiB	  0.04	  0.00	  0.619658	  -3.41326	  -0.619658	  0.545	  0.01	  5.5384e-05	  4.0883e-05	  0.000339161	  0.000274106	  -1	  -1	  -1	  -1	  20	  15	  1	  107788	  107788	  10441.3	  652.579	  0.02	  0.00305328	  0.00284599	  750	  1675	  -1	  15	  1	  7	  7	  94	  62	  0.562699	  0.545	  -3.33969	  -0.562699	  0	  0	  13752.8	  859.551	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00161855	  0.0015492	 
