 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml	  test.v	  common	  6.81	  vpr	  74.85 MiB	  	  0.09	  7796	  -1	  -1	  1	  0.08	  -1	  -1	  32232	  -1	  -1	  12	  130	  0	  -1	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  76648	  130	  40	  596	  562	  1	  356	  185	  14	  14	  196	  dsp_top	  auto	  35.9 MiB	  0.18	  1873	  36479	  12233	  19905	  4341	  74.9 MiB	  0.21	  0.00	  5.12303	  -652.04	  -5.12303	  5.12303	  0.82	  0.00140021	  0.00130659	  0.105265	  0.098455	  -1	  -1	  -1	  -1	  64	  3939	  11	  4.93594e+06	  1.0962e+06	  976140.	  4980.31	  2.47	  0.398489	  0.366481	  31408	  195022	  -1	  3669	  7	  846	  891	  204483	  79938	  4.57723	  4.57723	  -704.235	  -4.57723	  0	  0	  1.23909e+06	  6321.90	  0.32	  0.09	  0.28	  -1	  -1	  0.32	  0.0391394	  0.037187	 
