 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_le	  num_luts	  num_add_blocks	  max_add_chain_length	  num_sub_blocks	  max_sub_chain_length	 
 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml	  diffeq2.v	  common	  12.97	  vpr	  66.77 MiB	  	  -1	  -1	  0.45	  22600	  5	  0.17	  -1	  -1	  33704	  -1	  -1	  17	  66	  0	  -1	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  68372	  66	  96	  983	  697	  1	  557	  191	  16	  16	  256	  mult_27	  auto	  27.9 MiB	  1.61	  4707	  40817	  12072	  24059	  4686	  66.8 MiB	  0.43	  0.01	  16.7814	  -976.989	  -16.7814	  16.7814	  0.32	  0.00267472	  0.00251467	  0.212685	  0.200099	  -1	  -1	  -1	  -1	  70	  10672	  23	  4.83877e+06	  1.03328e+06	  1.46230e+06	  5712.11	  7.74	  1.30204	  1.18821	  41380	  305391	  -1	  9491	  17	  2752	  5856	  1134816	  361601	  17.2419	  17.2419	  -1064.29	  -17.2419	  0	  0	  1.81221e+06	  7078.95	  0.05	  0.32	  0.24	  -1	  -1	  0.05	  0.113399	  0.105285	  138	  202	  -1	  -1	  -1	  -1	 
