 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  num_io	  num_LAB	  num_MLAB	  num_DSP	  num_M20K	  num_PLL	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  routed_wirelength	  avg_routed_wirelength	  routed_wiresegment	  avg_routed_wiresegment	  total_nets_routed	  total_connections_routed	  total_heap_pushes	  total_heap_pops	  logic_block_area_total	  logic_block_area_used	  routing_area_total	  routing_area_per_tile	  crit_path_route_success_iteration	  num_rr_graph_nodes	  num_rr_graph_edges	  collapsed_nodes	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  create_rr_graph_time	  create_intra_cluster_rr_graph_time	  adding_internal_edges	  route_mem	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  router_lookahead_mem	  tile_lookahead_computation_time	  router_lookahead_computation_time	 
 stratix10_arch.timing.xml	  murax_stratix10_arch_timing.blif	  common	  16.21	  vpr	  382.44 MiB	  	  35	  93	  0	  0	  8	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  391620	  18	  17	  2338	  2195	  1	  2035	  136	  17	  13	  221	  io_cell	  auto	  340.2 MiB	  7.18	  12025	  15143	  2373	  11284	  1486	  382.4 MiB	  0.82	  0.02	  3.667	  -3355.12	  -2.667	  3.667	  0.00	  0.00751636	  0.00623723	  0.354082	  0.308909	  13333	  6.56152	  4082	  2.00886	  6905	  16479	  4317407	  919786	  0	  0	  3.37726e+06	  15281.7	  11	  52540	  541133	  -1	  3.321	  3.321	  -2922.28	  -2.321	  0	  0	  1.23	  -1	  -1	  382.4 MiB	  1.29	  0.623395	  0.553667	  382.4 MiB	  -1	  0.16	 
