 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_global_nets	  num_routed_nets	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_dedicated_network	  16.75	  vpr	  87.78 MiB	  	  -1	  -1	  1.62	  25940	  2	  0.13	  -1	  -1	  34228	  -1	  -1	  32	  311	  15	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  89888	  311	  156	  1015	  1158	  1	  965	  514	  28	  28	  784	  memory	  auto	  32.1 MiB	  0.86	  8845	  198082	  66456	  118274	  13352	  82.2 MiB	  1.17	  0.02	  3.956	  -3577.83	  -3.956	  3.956	  0.91	  0.00595862	  0.00507335	  0.579582	  0.507447	  -1	  -1	  -1	  -1	  38	  15121	  19	  4.25198e+07	  9.94461e+06	  2.06185e+06	  2629.91	  7.81	  2.09337	  1.84486	  78047	  421269	  -1	  13915	  13	  2941	  3356	  1063385	  481002	  4.40758	  4.40758	  -4403.13	  -4.40758	  -487.231	  -1.50494	  2.60823e+06	  3326.82	  0.10	  0.99	  0.35	  -1	  -1	  0.10	  0.1939	  0.175475	  15	  950	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_dedicated_network	  12.26	  vpr	  82.69 MiB	  	  -1	  -1	  1.60	  26028	  2	  0.12	  -1	  -1	  34260	  -1	  -1	  32	  311	  15	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  84676	  311	  156	  1015	  1158	  1	  965	  514	  28	  28	  784	  memory	  auto	  31.9 MiB	  0.56	  8845	  198082	  66456	  118274	  13352	  82.7 MiB	  1.18	  0.02	  3.956	  -3577.83	  -3.956	  3.956	  0.93	  0.0063214	  0.00542235	  0.581161	  0.508246	  -1	  -1	  -1	  -1	  36	  15620	  28	  4.25198e+07	  9.94461e+06	  2.00618e+06	  2558.90	  4.17	  1.9785	  1.74537	  76483	  403003	  -1	  14013	  15	  2977	  3438	  716727	  218700	  4.40926	  4.40926	  -4353.58	  -4.40926	  -187.028	  -1.38104	  2.47848e+06	  3161.33	  0.10	  0.84	  0.34	  -1	  -1	  0.10	  0.214406	  0.193914	  15	  950	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_dedicated_network	  13.85	  vpr	  84.25 MiB	  	  -1	  -1	  1.59	  25768	  2	  0.13	  -1	  -1	  34248	  -1	  -1	  32	  311	  15	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  86276	  311	  156	  1015	  1158	  1	  965	  514	  28	  28	  784	  memory	  auto	  32.0 MiB	  0.86	  8670	  198082	  67338	  117530	  13214	  84.3 MiB	  1.18	  0.02	  4.3081	  -3773.97	  -4.3081	  4.3081	  0.90	  0.00578914	  0.00514189	  0.580527	  0.513158	  -1	  -1	  -1	  -1	  38	  16089	  24	  4.25198e+07	  9.94461e+06	  2.05729e+06	  2624.09	  4.91	  1.60281	  1.41862	  78047	  421435	  -1	  14828	  11	  2717	  3081	  1120212	  641147	  5.50533	  5.50533	  -4581.38	  -5.50533	  -1561.99	  -3.22679	  2.60365e+06	  3320.98	  0.10	  1.07	  0.35	  -1	  -1	  0.10	  0.172057	  0.156482	  15	  950	 
