arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	
k4_N10_memSize16384_memData64.xml	ch_intrinsics_modified.v	common	2.71	vpr	61.64 MiB		-1	-1	0.45	18444	3	0.09	-1	-1	32856	-1	-1	71	99	1	0	success	v8.0.0-11920-g63becbef4-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2024-12-04T15:29:41	betzgrp-wintermute.eecg.utoronto.ca	/home/elgamma8/research/release/vtr-verilog-to-routing	63120	99	130	353	483	1	222	301	13	13	169	clb	auto	21.8 MiB	0.06	723	26509	3069	10019	13421	61.6 MiB	0.04	0.00	28	1598	8	3.33e+06	2.25e+06	384474.	2275.00	0.18	
