#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: D:\DMYWdownloadsoftware\PDS\pango\PDS_2022.2-SP6.4\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.26100
#Hostname: LAPTOP-E50OTCNR
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Tue Nov  4 23:05:49 2025
Compiling verification operator library.
Compiling common defs.
Compiling prim grid devices.
Compiling gate devices.
Compiling gate operators.
Building architecture model.
Loading device packaging model.
pnr strategy configuration : 
strategy name : 0
Building architecture floorplan logic view.
Constraint check start.
Executing : def_port {cmos1_scl} LOC=R14 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 3)] | Port cmos1_scl has been placed at location R14, whose type is share pin.
Executing : def_port {cmos1_scl} LOC=R14 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE successfully
Executing : def_port {cmos1_sda} LOC=P14 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 4)] | Port cmos1_sda has been placed at location P14, whose type is share pin.
Executing : def_port {cmos1_sda} LOC=P14 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE successfully
Executing : def_port {cmos2_scl} LOC=U20 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE
Executing : def_port {cmos2_scl} LOC=U20 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE successfully
Executing : def_port {cmos2_sda} LOC=N17 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE
Executing : def_port {cmos2_sda} LOC=N17 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE successfully
Executing : def_port {ddr_mem_dq[0]} LOC=P6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[0]} LOC=P6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[1]} LOC=M5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[1]} LOC=M5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[2]} LOC=M6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[2]} LOC=M6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[3]} LOC=N2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[3]} LOC=N2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[4]} LOC=P2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[4]} LOC=P2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[5]} LOC=P1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[5]} LOC=P1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[6]} LOC=R1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[6]} LOC=R1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[7]} LOC=N4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[7]} LOC=N4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[8]} LOC=J6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[8]} LOC=J6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[9]} LOC=K6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[9]} LOC=K6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[10]} LOC=M2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[10]} LOC=M2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[11]} LOC=M3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[11]} LOC=M3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[12]} LOC=K3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[12]} LOC=K3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[13]} LOC=L3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[13]} LOC=L3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[14]} LOC=J4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[14]} LOC=J4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dq[15]} LOC=K4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dq[15]} LOC=K4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dqs[0]} LOC=P5 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dqs[0]} LOC=P5 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dqs[1]} LOC=M1 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_HYS=ON CP_DYN_TERM=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dqs[1]} LOC=M1 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_HYS=ON CP_DYN_TERM=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dqs_n[0]} LOC=P4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dqs_n[0]} LOC=P4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dqs_n[1]} LOC=L1 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE
Executing : def_port {ddr_mem_dqs_n[1]} LOC=L1 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE successfully
Executing : def_port {i2c_sda} LOC=R19 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=4 SLEW=FAST PULLUP=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 27)] | Port i2c_sda has been placed at location R19, whose type is share pin.
Executing : def_port {i2c_sda} LOC=R19 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=4 SLEW=FAST PULLUP=TRUE successfully
Executing : def_port {cmos1_reset} LOC=V18 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE
Executing : def_port {cmos1_reset} LOC=V18 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE successfully
Executing : def_port {cmos2_reset} LOC=AA21 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 29)] | Port cmos2_reset has been placed at location AA21, whose type is share pin.
Executing : def_port {cmos2_reset} LOC=AA21 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE successfully
Executing : def_port {ddr_mem_a[0]} LOC=T1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[0]} LOC=T1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[1]} LOC=U1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[1]} LOC=U1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[2]} LOC=U2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[2]} LOC=U2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[3]} LOC=V2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[3]} LOC=V2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[4]} LOC=R3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[4]} LOC=R3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[5]} LOC=R2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[5]} LOC=R2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[6]} LOC=W2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[6]} LOC=W2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[7]} LOC=Y2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[7]} LOC=Y2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[8]} LOC=W1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[8]} LOC=W1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[9]} LOC=Y1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[9]} LOC=Y1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[10]} LOC=U3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[10]} LOC=U3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[11]} LOC=AA1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[11]} LOC=AA1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[12]} LOC=AB1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[12]} LOC=AB1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[13]} LOC=AB3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[13]} LOC=AB3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_a[14]} LOC=AB2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_a[14]} LOC=AB2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_ba[0]} LOC=AA3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_ba[0]} LOC=AA3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_ba[1]} LOC=AA5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_ba[1]} LOC=AA5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_ba[2]} LOC=AB5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_ba[2]} LOC=AB5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_cas_n} LOC=U6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_cas_n} LOC=U6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_ck} LOC=Y4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_ck} LOC=Y4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_ck_n} LOC=AA4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_ck_n} LOC=AA4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_cke} LOC=W4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_cke} LOC=W4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_cs_n} LOC=V5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_cs_n} LOC=V5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dm[0]} LOC=N5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_dm[0]} LOC=N5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_dm[1]} LOC=L5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_dm[1]} LOC=L5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_odt} LOC=R6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_odt} LOC=R6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_ras_n} LOC=W5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_ras_n} LOC=W5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_rst_n} LOC=T3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_rst_n} LOC=T3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {ddr_mem_we_n} LOC=W6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {ddr_mem_we_n} LOC=W6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {pclk_led} LOC=J16 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=4 SLEW=SLOW PULLUP=TRUE
Executing : def_port {pclk_led} LOC=J16 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=4 SLEW=SLOW PULLUP=TRUE successfully
Executing : def_port {ref_led} LOC=M17 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=4 SLEW=SLOW PULLUP=TRUE
Executing : def_port {ref_led} LOC=M17 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=4 SLEW=SLOW PULLUP=TRUE successfully
Executing : def_port {button_rst_n} LOC=M15 VCCIO=3.3 IOSTANDARD=LVCMOS18 NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 61)] | Port button_rst_n has been placed at location M15, whose type is share pin.
Executing : def_port {button_rst_n} LOC=M15 VCCIO=3.3 IOSTANDARD=LVCMOS18 NONE=TRUE successfully
Executing : def_port {cmos1_data[0]} LOC=Y18 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
Executing : def_port {cmos1_data[0]} LOC=Y18 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE successfully
Executing : def_port {cmos1_data[1]} LOC=AA19 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 63)] | Port cmos1_data[1] has been placed at location AA19, whose type is share pin.
Executing : def_port {cmos1_data[1]} LOC=AA19 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE successfully
Executing : def_port {cmos1_data[2]} LOC=AB20 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 64)] | Port cmos1_data[2] has been placed at location AB20, whose type is share pin.
Executing : def_port {cmos1_data[2]} LOC=AB20 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE successfully
Executing : def_port {cmos1_data[3]} LOC=V19 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
Executing : def_port {cmos1_data[3]} LOC=V19 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE successfully
Executing : def_port {cmos1_data[4]} LOC=L13 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 66)] | Port cmos1_data[4] has been placed at location L13, whose type is share pin.
Executing : def_port {cmos1_data[4]} LOC=L13 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE successfully
Executing : def_port {cmos1_data[5]} LOC=AB22 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 67)] | Port cmos1_data[5] has been placed at location AB22, whose type is share pin.
Executing : def_port {cmos1_data[5]} LOC=AB22 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE successfully
Executing : def_port {cmos1_data[6]} LOC=Y19 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
Executing : def_port {cmos1_data[6]} LOC=Y19 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE successfully
Executing : def_port {cmos1_data[7]} LOC=AB21 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 69)] | Port cmos1_data[7] has been placed at location AB21, whose type is share pin.
Executing : def_port {cmos1_data[7]} LOC=AB21 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE successfully
Executing : def_port {cmos1_href} LOC=N15 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
Executing : def_port {cmos1_href} LOC=N15 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE successfully
Executing : def_port {cmos1_pclk} LOC=T18 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 71)] | Port cmos1_pclk has been placed at location T18, whose type is share pin.
Executing : def_port {cmos1_pclk} LOC=T18 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE successfully
Executing : def_port {cmos1_vsync} LOC=W17 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 72)] | Port cmos1_vsync has been placed at location W17, whose type is share pin.
Executing : def_port {cmos1_vsync} LOC=W17 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE successfully
Executing : def_port {cmos2_data[0]} LOC=U17 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2001: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 73)] Object 'cmos2_data[0]' is dangling, which has no connection. it will be ignored.
Executing : def_port {cmos2_data[0]} LOC=U17 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE failed
Executing : def_port {cmos2_data[1]} LOC=V20 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2001: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 74)] Object 'cmos2_data[1]' is dangling, which has no connection. it will be ignored.
Executing : def_port {cmos2_data[1]} LOC=V20 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE failed
Executing : def_port {cmos2_data[2]} LOC=R16 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2001: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 75)] Object 'cmos2_data[2]' is dangling, which has no connection. it will be ignored.
Executing : def_port {cmos2_data[2]} LOC=R16 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE failed
Executing : def_port {cmos2_data[3]} LOC=P15 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2001: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 76)] Object 'cmos2_data[3]' is dangling, which has no connection. it will be ignored.
Executing : def_port {cmos2_data[3]} LOC=P15 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE failed
Executing : def_port {cmos2_data[4]} LOC=W19 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2001: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 77)] Object 'cmos2_data[4]' is dangling, which has no connection. it will be ignored.
Executing : def_port {cmos2_data[4]} LOC=W19 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE failed
Executing : def_port {cmos2_data[5]} LOC=W20 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2001: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 78)] Object 'cmos2_data[5]' is dangling, which has no connection. it will be ignored.
Executing : def_port {cmos2_data[5]} LOC=W20 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE failed
Executing : def_port {cmos2_data[6]} LOC=P17 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2001: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 79)] Object 'cmos2_data[6]' is dangling, which has no connection. it will be ignored.
Executing : def_port {cmos2_data[6]} LOC=P17 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE failed
Executing : def_port {cmos2_data[7]} LOC=AB18 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2001: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 80)] Object 'cmos2_data[7]' is dangling, which has no connection. it will be ignored.
Executing : def_port {cmos2_data[7]} LOC=AB18 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE failed
Executing : def_port {cmos2_href} LOC=U18 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2001: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 81)] Object 'cmos2_href' is dangling, which has no connection. it will be ignored.
Executing : def_port {cmos2_href} LOC=U18 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE failed
Executing : def_port {cmos2_pclk} LOC=P16 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2001: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 82)] Object 'cmos2_pclk' is dangling, which has no connection. it will be ignored.
Executing : def_port {cmos2_pclk} LOC=P16 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE failed
Executing : def_port {cmos2_vsync} LOC=R17 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE
C: ConstraintEditor-2001: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 83)] Object 'cmos2_vsync' is dangling, which has no connection. it will be ignored.
Executing : def_port {cmos2_vsync} LOC=R17 VCCIO=3.3 IOSTANDARD=LVCMOS33 NONE=TRUE failed
Executing : def_port {i2c_scl} LOC=P19 VCCIO=3.3 IOSTANDARD=LVCMOS33 PULLUP=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 84)] | Port i2c_scl has been placed at location P19, whose type is share pin.
Executing : def_port {i2c_scl} LOC=P19 VCCIO=3.3 IOSTANDARD=LVCMOS33 PULLUP=TRUE successfully
Executing : def_port {perst_n} LOC=M16 VCCIO=3.3 IOSTANDARD=LVCMOS18 NONE=TRUE
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/dram_pcie.pcf(line number: 85)] | Port perst_n has been placed at location M16, whose type is share pin.
Executing : def_port {perst_n} LOC=M16 VCCIO=3.3 IOSTANDARD=LVCMOS18 NONE=TRUE successfully
Executing : def_port {ref_clk_n} LOC=E6
Executing : def_port {ref_clk_n} LOC=E6 successfully
Executing : def_port {ref_clk_p} LOC=F6
Executing : def_port {ref_clk_p} LOC=F6 successfully
Executing : def_port {sys_clk} LOC=V4 VCCIO=1.5 IOSTANDARD=LVCMOS15 UNUSED=TRUE
Executing : def_port {sys_clk} LOC=V4 VCCIO=1.5 IOSTANDARD=LVCMOS15 UNUSED=TRUE successfully
Executing : def_inst_site {u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv} CLMA_285_54 FF3
Executing : def_inst_site {u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv} CLMA_285_54 FF3 successfully
Executing : def_inst_site {u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv} CLMA_285_360 FF3
Executing : def_inst_site {u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv} CLMA_285_360 FF3 successfully
Executing : def_inst_site {u_ddr3/u_ddrphy_top/u_ddrphy_cpd/cpd_inst} DDRPHY_CPD_297_4
Executing : def_inst_site {u_ddr3/u_ddrphy_top/u_ddrphy_cpd/cpd_inst} DDRPHY_CPD_297_4 successfully
Executing : def_inst_site {u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/gophsst} HSSTLP_292_612 U0_HSSTLP_LANE
Executing : def_inst_site {u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/gophsst} HSSTLP_292_612 U0_HSSTLP_LANE successfully
Executing : def_inst_site {u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/gophsst} HSSTLP_292_612 U1_HSSTLP_LANE
Executing : def_inst_site {u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/gophsst} HSSTLP_292_612 U1_HSSTLP_LANE successfully
Executing : def_inst_site {u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/PLL0_ENABLE.U_GTP_HSSTLP_PLL0/gophsst} HSSTLP_292_612 U0_HSSTLP_PLL
Executing : def_inst_site {u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/PLL0_ENABLE.U_GTP_HSSTLP_PLL0/gophsst} HSSTLP_292_612 U0_HSSTLP_PLL successfully
W: ConstraintEditor-4019: Port Bus 'rxn' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'rxp' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'txn' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'txp' unspecified I/O constraint.
Constraint check end.
I: Column Clock Check open.
Read Column Clock Map.

Placement started.
Phase 1 Pre global placement started.
Mapping instance GTP_GRS_INST/grs_ccs to CCS_75_10.
Mapping instance u_CORES/u_GTP_SCANCHAIN_PG/scanchain to SCANCHAIN_76_6.
Mapping instance u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/gateop to PCIE_243_612.
Mapping instance u_PLL/u_gpll/gpll_inst to GPLL_295_157.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst to DDRPHY_IOCLK_DIV_296_4.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst to PPLL_295_1.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst to DDR_PHY_297_159.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/ddc_inst to DDR_PHY_297_157.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/ddc_inst to DDR_PHY_297_3.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst to DDRPHY_IOCLK_DIV_296_310.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst to PPLL_295_307.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY to DDR_PHY_297_307.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY to DDR_PHY_297_309.
Phase 1.1 1st GP placement started.
Design Utilization : 25%.
First map gop timing takes 2.22 sec
Worst slack after clock region global placement is -1180
Wirelength after clock region global placement is 294709 and checksum is 25AB92DBC6FE1FCF.
1st GP placement takes 11.42 sec.

Phase 1.2 Clock placement started.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk to RCKB_291_150.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk to RCKB_291_456.
Mapping instance u_ddr3/u_ddrphy_top/u_clkbufm/clkbufm_inst to MRCKB_289_150.
Mapping instance clkbufg_3/gopclkbufg to USCM_167_318.
Mapping instance u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/gopclkbufg to USCM_167_321.
Mapping instance clkbufg_5/gopclkbufg to USCM_167_270.
Mapping instance clkbufg_6/gopclkbufg to USCM_167_324.
Mapping instance clkbufg_8/gopclkbufg to USCM_167_273.
Mapping instance u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst to GPLL_7_157.
Mapping instance u_ddr3/u_ddrphy_top/u_sysclk_bufg/gopclkbufg to USCM_167_276.
Mapping instance u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst to GPLL_295_463.
Mapping instance u_ddr3/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg to USCM_167_327.
C: Place-2028: GLOBAL_CLOCK: the driver u_CORES/u_GTP_SCANCHAIN_PG/scanchain fixed at SCANCHAIN_76_6 is unreasonable. Sub-optimal placement for a clock source and a clock buffer.
Mapping instance clkbufg_4/gopclkbufg to USCM_167_279.
C: Place-2028: GLOBAL_CLOCK: the driver cmos1_pclk_ibuf/opit_1 fixed at IOLHR_16_54 is unreasonable. Sub-optimal placement for a clock source and a clock buffer.
Mapping instance clkbufg_7/gopclkbufg to USCM_167_282.
Clock placement takes 0.25 sec.

Wirelength after Pre Global Placement is 294709 and checksum is 25AB92DBC6FE1FCF.
Pre global placement takes 12.30 sec.

Phase 2 Global placement started.
Phase 2.1 Fixed placement started.
Placed fixed group with base inst button_rst_n_ibuf/opit_1 on IOLHR_16_318.
Placed fixed group with base inst cmos1_data_ibuf[0]/opit_1 on IOLHR_16_144.
Placed fixed group with base inst cmos1_data_ibuf[1]/opit_1 on IOLHR_16_120.
Placed fixed group with base inst cmos1_data_ibuf[2]/opit_1 on IOLHR_16_114.
Placed fixed group with base inst cmos1_data_ibuf[3]/opit_1 on IOLHR_16_126.
Placed fixed group with base inst cmos1_data_ibuf[4]/opit_1 on IOLHR_16_360.
Placed fixed group with base inst cmos1_data_ibuf[5]/opit_1 on IOLHR_16_180.
Placed fixed group with base inst cmos1_data_ibuf[6]/opit_1 on IOLHR_16_138.
Placed fixed group with base inst cmos1_data_ibuf[7]/opit_1 on IOLHR_16_186.
Placed fixed group with base inst cmos1_href_ibuf/opit_1 on IOLHR_16_0.
Placed fixed group with base inst cmos1_pclk_ibuf/opit_1 on IOLHR_16_54.
Placed fixed group with base inst cmos1_reset_obuf/opit_1 on IOLHR_16_132.
Placed fixed group with base inst cmos1_scl_iobuf/opit_1 on IOLHR_16_66.
Placed fixed group with base inst cmos1_vsync_ibuf/opit_1 on IOLHR_16_102.
Placed fixed group with base inst cmos2_reset_obuf/opit_1 on IOLHR_16_204.
Placed fixed group with base inst cmos2_scl_iobuf/opit_1 on IOLHR_16_174.
Placed fixed group with base inst coms1_reg_config.u1.i2c_sdat_tri/opit_1 on IOLHR_16_72.
Placed fixed group with base inst coms2_reg_config.u1.i2c_sdat_tri/opit_1 on IOLHR_16_48.
Placed fixed group with base inst ddr_mem_rst_n_obuf/opit_1 on IOLHR_292_300.
Placed fixed group with base inst i2cSlave_u.sda_tri/opit_1 on IOLHR_16_240.
Placed fixed group with base inst i2c_scl_ibuf/opit_1 on IOLHR_16_246.
Placed fixed group with base inst pclk_led_obuf/opit_1 on IOLHR_16_606.
Placed fixed group with base inst perst_n_ibuf/opit_1 on IOLHR_16_312.
Placed fixed group with base inst ref_led_obuf/opit_1 on IOLHR_16_306.
Placed fixed group with base inst sys_clk_ibuf/opit_1 on IOLHR_292_162.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1 on IOLHR_292_318.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1 on IOLHR_292_324.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1 on IOLHR_292_330.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[3].u_iobuf_dq/opit_1 on IOLHR_292_336.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1 on IOLHR_292_342.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1 on IOLHR_292_360.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[6].u_iobuf_dq/opit_1 on IOLHR_292_366.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1 on IOLHR_292_378.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/genblk1.u_iobufco_dqs/opit_2 on IOLHR_292_354.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_outbuft_dm/opit_1 on IOLHR_292_312.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1 on IOLHR_292_396.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1 on IOLHR_292_402.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1 on IOLHR_292_408.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[3].u_iobuf_dq/opit_1 on IOLHR_292_414.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1 on IOLHR_292_432.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1 on IOLHR_292_438.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[6].u_iobuf_dq/opit_1 on IOLHR_292_444.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1 on IOLHR_292_450.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/genblk1.u_iobufco_dqs/opit_2 on IOLHR_292_426.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_outbuft_dm/opit_1 on IOLHR_292_390.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[0].u_outbuft_addr0/opit_1 on IOLHR_292_294.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[1].u_outbuft_addr0/opit_1 on IOLHR_292_288.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[2].u_outbuft_addr0/opit_1 on IOLHR_292_282.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[3].u_outbuft_addr0/opit_1 on IOLHR_292_276.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1 on IOLHR_292_270.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[5].u_outbuft_addr0/opit_1 on IOLHR_292_264.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[6].u_outbuft_addr0/opit_1 on IOLHR_292_258.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[7].u_outbuft_addr0/opit_1 on IOLHR_292_252.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[8].u_outbuft_addr0/opit_1 on IOLHR_292_246.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[9].u_outbuft_addr0/opit_1 on IOLHR_292_240.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[10].u_outbuft_addr0/opit_1 on IOLHR_292_234.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[11].u_outbuft_addr0/opit_1 on IOLHR_292_222.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[12].u_outbuft_addr0/opit_1 on IOLHR_292_216.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[13].u_outbuft_addr0/opit_1 on IOLHR_292_210.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[14].u_outbuft_addr0/opit_1 on IOLHR_292_204.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[0].u_outbuft_ba/opit_1 on IOLHR_292_192.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[1].u_outbuft_ba/opit_1 on IOLHR_292_186.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[2].u_outbuft_ba/opit_1 on IOLHR_292_180.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/u_outbuft_casn/opit_1 on IOLHR_292_108.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/u_outbuft_cke/opit_1 on IOLHR_292_156.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/u_outbuft_csn/opit_1 on IOLHR_292_102.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/u_outbuft_odt/opit_1 on IOLHR_292_96.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/u_outbuft_rasn/opit_1 on IOLHR_292_114.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/u_outbuft_wen/opit_1 on IOLHR_292_120.
Placed fixed group with base inst u_ddr3/u_ddrphy_top/ddrphy_slice_top/u_outbuftco_ck/opit_3 on IOLHR_292_174.
Placed fixed group with base inst u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/gophsst on HSSTLP_292_612.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv on CLMA_285_54.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv on CLMA_285_360.
Placed fixed instance u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/PLL0_ENABLE.U_GTP_HSSTLP_PLL0/gophsst on HSSTLP_292_612.
Placed fixed instance GTP_GRS_INST/grs_ccs on CCS_75_10.
Placed fixed instance clkbufg_3/gopclkbufg on USCM_167_318.
Placed fixed instance clkbufg_4/gopclkbufg on USCM_167_279.
Placed fixed instance clkbufg_5/gopclkbufg on USCM_167_270.
Placed fixed instance clkbufg_6/gopclkbufg on USCM_167_324.
Placed fixed instance clkbufg_7/gopclkbufg on USCM_167_282.
Placed fixed instance clkbufg_8/gopclkbufg on USCM_167_273.
Placed fixed instance ref_clk_n_ibuf_hsst on SPAD_291_614.
Placed fixed instance ref_clk_p_ibuf_hsst on SPAD_291_613.
Placed fixed instance u_CORES/u_GTP_SCANCHAIN_PG/scanchain on SCANCHAIN_76_6.
Placed fixed instance u_PLL/u_gpll/gpll_inst on GPLL_295_157.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst on GPLL_7_157.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst on DDR_PHY_297_159.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/ddc_inst on DDR_PHY_297_157.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/ddc_inst on DDR_PHY_297_3.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst on PPLL_295_1.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk on RCKB_291_150.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst on DDRPHY_IOCLK_DIV_296_4.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst on PPLL_295_307.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk on RCKB_291_456.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst on DDRPHY_IOCLK_DIV_296_310.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY on DDR_PHY_297_307.
Placed fixed instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY on DDR_PHY_297_309.
Placed fixed instance u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst on GPLL_295_463.
Placed fixed instance u_ddr3/u_ddrphy_top/u_clkbufm/clkbufm_inst on MRCKB_289_150.
Placed fixed instance u_ddr3/u_ddrphy_top/u_ddrphy_cpd/cpd_inst on DDRPHY_CPD_297_4.
Placed fixed instance u_ddr3/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg on USCM_167_327.
Placed fixed instance u_ddr3/u_ddrphy_top/u_sysclk_bufg/gopclkbufg on USCM_167_276.
Placed fixed instance u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/gopclkbufg on USCM_167_321.
Placed fixed instance u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/gateop on PCIE_243_612.
Placed fixed instance BKCL_auto_0 on BKCL_1_340.
Placed fixed instance BKCL_auto_1 on BKCL_1_34.
Placed fixed instance BKCL_auto_2 on BKCL_301_340.
Placed fixed instance BKCL_auto_3 on BKCL_301_34.
Fixed placement takes 0.41 sec.

Phase 2.2 Process placement started.
I: The IO driver of u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst(CLKIN1) is not constraint at pllpad, its clock path will pass through SRB.
I: The IO driver of u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst(CLKIN1) is not constraint at pllpad, its clock path will pass through SRB.
Process placement takes 0.00 sec.

Phase 2.3 IO placement started.
IO placement takes 0.08 sec.

Phase 2.4 2nd GP placement started.
Run super clustering :
	Initial slack -3654.
	5 iterations finished.
	Final slack -2616.
Super clustering done.
Design Utilization : 25%.
Worst slack after global placement is 330
2nd GP placement takes 7.50 sec.

Wirelength after global placement is 163817 and checksum is 5612B6C33C2EE298.
Global placement takes 8.00 sec.

Phase 3 Post global placement started.
Packing LUT6D started.
I: LUT6D pack result: There are 4058 LUT6 in collection, pack success:168
Packing LUT6D takes 1.72 sec.
Phase 3.1 Macro cell placement started.
I: Process macros using "Greedy".
Wirelength after macro cell placement is 179677 and checksum is E5B09EBAD2A7A108.
Macro cell placement takes 0.09 sec.

Phase 3.2 3rd GP placement started.
Run super clustering :
	Initial slack -3654.
	4 iterations finished.
	Final slack -2836.
Super clustering done.
Design Utilization : 25%.
Worst slack after post global placement is 244
3rd GP placement takes 4.34 sec.

Wirelength after post global placement is 160137 and checksum is 481438E0E9E0EF06.
Packing LUT6D started.
I: LUT6D pack result: There are 3722 LUT6 in collection, pack success:8
Packing LUT6D takes 1.73 sec.
Post global placement takes 7.94 sec.

Phase 4 Legalization started.
The average distance in LP is 0.696817.
Wirelength after legalization is 181769 and checksum is 3DE90E65BA7CC34D.
Legalization takes 0.98 sec.

Phase 5 Timing-driven detailed placement started.
Phase 5.1 Replication placement started.
Worst slack before Replication Place is 998.
Replication placement takes 0.56 sec.

Wirelength after replication placement is 181769 and checksum is 3DE90E65BA7CC34D.
Phase 5.2 Swapping placement started.
Worst slack before detailed placement is 998, TNS before detailed placement is 0. 
Cost at Swap iteration 0 : 998, wslk 1154, tns 0, takes 0.08 sec.
Cost at DP iteration 0 : 1154, wslk 1154, tns 0, takes 0.02 sec.
Worst slack after detailed placement is 1154, TNS after detailed placement is 0. 
Swapping placement takes 0.52 sec.

Wirelength after detailed placement is 181762 and checksum is CB71BCC4D0440DE5.
Timing-driven detailed placement takes 1.11 sec.

Worst slack is 1154, TNS after placement is 0.
Placement done.
Total placement takes 35.42 sec.
Finished placement.

Routing started.
Enter timing driven router mode.
Route thread size: 3
Building routing graph takes 1.42 sec.
Setup STE netlist take 551 msec.
Dispose control chain take 470 msec.
Collect const net info take 169 msec.
Total nets for routing: 17693.
Total loads for routing: 79109.
Direct connect net size: 1959
Build all design net take 693 msec.
Worst slack is 1154, TNS before route is 0.
Processing design graph takes 1.95 sec.
Delay table total memory: 0.47260857 MB
Route graph total memory: 85.38207436 MB
Route design total memory: 24.84857178 MB
Global routing takes 0.00 sec.
Total 17691 subnets.
Unrouted clock nets at iteration 0 (0.129 sec): 4
Unrouted clock nets at iteration 1 (0.001 sec): 4
Unrouted clock nets at iteration 2 (0.001 sec): 4
Unrouted clock nets at iteration 3 (0.001 sec): 4
Unrouted clock nets at iteration 4 (0.007 sec): 0
Total route nets size: 17618
Pre route takes 6.771 sec
Unrouted general nets at iteration 6 (MT total route time: 2.858 sec): 15270(overused: 91452)
Unrouted general nets at iteration 7 (MT total route time: 2.820 sec): 13145(overused: 68573)
Unrouted general nets at iteration 8 (MT total route time: 2.334 sec): 10974(overused: 46618)
Unrouted general nets at iteration 9 (MT total route time: 1.952 sec): 9230(overused: 33581)
Unrouted general nets at iteration 10 (MT total route time: 1.521 sec): 7961(overused: 25373)
Unrouted general nets at iteration 11 (MT total route time: 1.386 sec): 6258(overused: 20139)
Unrouted general nets at iteration 12 (MT total route time: 1.242 sec): 5225(overused: 16067)
Unrouted general nets at iteration 13 (MT total route time: 0.988 sec): 4170(overused: 12120)
Unrouted general nets at iteration 14 (MT total route time: 1.000 sec): 3518(overused: 9703)
Unrouted general nets at iteration 15 (MT total route time: 0.819 sec): 2857(overused: 7377)
Unrouted general nets at iteration 16 (MT total route time: 0.751 sec): 2509(overused: 6495)
Unrouted general nets at iteration 17 (MT total route time: 0.634 sec): 2202(overused: 5452)
Unrouted general nets at iteration 18 (MT total route time: 0.552 sec): 1942(overused: 4591)
Unrouted general nets at iteration 19 (MT total route time: 0.545 sec): 1798(overused: 4084)
Unrouted general nets at iteration 20 (MT total route time: 0.459 sec): 1513(overused: 3325)
Unrouted general nets at iteration 21 (MT total route time: 0.390 sec): 1289(overused: 2747)
Unrouted general nets at iteration 22 (MT total route time: 0.399 sec): 1166(overused: 2499)
Unrouted general nets at iteration 23 (MT total route time: 0.323 sec): 1062(overused: 2140)
Unrouted general nets at iteration 24 (MT total route time: 0.303 sec): 987(overused: 1987)
Unrouted general nets at iteration 25 (MT total route time: 0.301 sec): 802(overused: 1589)
Unrouted general nets at iteration 26 (MT total route time: 0.264 sec): 763(overused: 1536)
Unrouted general nets at iteration 27 (MT total route time: 0.267 sec): 666(overused: 1323)
Unrouted general nets at iteration 28 (MT total route time: 0.212 sec): 538(overused: 1031)
Unrouted general nets at iteration 29 (MT total route time: 0.184 sec): 473(overused: 905)
Unrouted general nets at iteration 30 (MT total route time: 0.160 sec): 391(overused: 704)
Unrouted general nets at iteration 31 (MT total route time: 0.155 sec): 339(overused: 610)
Unrouted general nets at iteration 32 (MT total route time: 0.127 sec): 283(overused: 484)
Unrouted general nets at iteration 33 (MT total route time: 0.113 sec): 239(overused: 387)
Unrouted general nets at iteration 34 (MT total route time: 0.105 sec): 210(overused: 392)
Unrouted general nets at iteration 35 (MT total route time: 0.116 sec): 229(overused: 408)
Unrouted general nets at iteration 36 (MT total route time: 0.122 sec): 197(overused: 316)
Unrouted general nets at iteration 37 (MT total route time: 0.102 sec): 192(overused: 322)
Unrouted general nets at iteration 38 (MT total route time: 0.101 sec): 202(overused: 368)
Unrouted general nets at iteration 39 (MT total route time: 0.110 sec): 180(overused: 288)
Unrouted general nets at iteration 40 (MT total route time: 0.094 sec): 140(overused: 226)
Unrouted general nets at iteration 41 (MT total route time: 0.086 sec): 136(overused: 202)
Unrouted general nets at iteration 42 (MT total route time: 0.081 sec): 122(overused: 188)
Unrouted general nets at iteration 43 (MT total route time: 0.106 sec): 161(overused: 312)
Unrouted general nets at iteration 44 (MT total route time: 0.109 sec): 156(overused: 280)
Unrouted general nets at iteration 45 (MT total route time: 0.090 sec): 168(overused: 264)
Unrouted general nets at iteration 46 (MT total route time: 0.108 sec): 154(overused: 243)
Unrouted general nets at iteration 47 (MT total route time: 0.102 sec): 135(overused: 222)
Unrouted general nets at iteration 48 (MT total route time: 0.079 sec): 111(overused: 172)
Unrouted general nets at iteration 49 (MT total route time: 0.080 sec): 84(overused: 110)
Unrouted general nets at iteration 50 (MT total route time: 0.084 sec): 104(overused: 154)
Unrouted general nets at iteration 51 (MT total route time: 0.078 sec): 100(overused: 154)
Unrouted general nets at iteration 52 (MT total route time: 0.071 sec): 80(overused: 119)
Unrouted general nets at iteration 53 (MT total route time: 0.068 sec): 67(overused: 96)
Unrouted general nets at iteration 54 (MT total route time: 0.064 sec): 58(overused: 116)
Unrouted general nets at iteration 55 (MT total route time: 0.068 sec): 72(overused: 137)
Unrouted general nets at iteration 56 (MT total route time: 0.071 sec): 75(overused: 114)
Unrouted general nets at iteration 57 (MT total route time: 0.090 sec): 52(overused: 72)
Unrouted general nets at iteration 58 (MT total route time: 0.072 sec): 45(overused: 74)
Unrouted general nets at iteration 59 (MT total route time: 0.064 sec): 39(overused: 68)
Unrouted general nets at iteration 60 (MT total route time: 0.059 sec): 26(overused: 46)
Unrouted general nets at iteration 61 (MT total route time: 0.061 sec): 22(overused: 44)
Unrouted general nets at iteration 62 (MT total route time: 0.062 sec): 19(overused: 30)
Unrouted general nets at iteration 63 (MT total route time: 0.070 sec): 22(overused: 42)
Unrouted general nets at iteration 64 (MT total route time: 0.064 sec): 18(overused: 22)
Unrouted general nets at iteration 65 (MT total route time: 0.055 sec): 14(overused: 18)
Unrouted general nets at iteration 66 (MT total route time: 0.049 sec): 4(overused: 8)
Unrouted general nets at iteration 67 (MT total route time: 0.045 sec): 2(overused: 4)
Unrouted general nets at iteration 68 (MT total route time: 0.049 sec): 0(overused: 0)
----General net take 0.055 sec(route net take 0.020 sec, inc cost take 0.035 sec, iter times: 1)
----const net route take 0.126 sec
Unrouted nets at iteration 69 (0.183 sec): 0
Detailed routing takes 47.26 sec.
I: Design net cmos1_pclk_16bit is routed by general path.
C: Route-2036: The clock path from cmos1_8_16bit/pclk_div2/opit_0_inv:Q to u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM36K_E1/gopdrm_36k:CLKA[0] is routed by SRB.
I: Design net coms1_reg_config/clock_20k is routed by general path.
C: Route-2036: The clock path from coms1_reg_config/clock_20k_cnt[0]/opit_0_L6QL5Q1:L5Q to coms1_reg_config/reg_data/gopdrm_18k:CLKA is routed by SRB.
I: Design net nt_cmos1_pclk is routed by general path.
C: Route-2036: The clock path from cmos1_pclk_ibuf/opit_1:DI_TO_CLK to clkbufg_7/gopclkbufg:CLK is routed by SRB.
I: Design net u_CORES/capt_o is routed by general path.
C: Route-2036: The clock path from u_CORES/u_GTP_SCANCHAIN_PG/scanchain:CAPTUREDR to u_CORES/u_debug_core_0/u_hub_data_decode/newconfini.conf_sel_ini/opit_0_inv:CLK is routed by SRB.
I: Design net u_CORES/drck_o is routed by general path.
C: Route-2036: The clock path from u_CORES/u_GTP_SCANCHAIN_PG/scanchain:TCK1 to clkbufg_4/gopclkbufg:CLK is routed by SRB.
Fix violation Finished.
No hold violation.
Hold Violation Fix in router takes 6.74 sec.
Sort Original Nets take 0.020 sec
Build solution node for device pins which were mapped to more than one design pin take 0.034 sec
Total net: 17693, route succeed net: 17693
Generate routing result take 0.054 sec
Handle PERMUX permutation take 0.846 sec
Handle const net take 0.040 sec
Handle route through take 0.013 sec
Handle loads' routing node take 0.149 sec
Used SRB routing arc is 183570.
Finish routing takes 1.43 sec.
Total routing takes 64.19 sec.


Device Utilization Summary :
+------------------------------------------------------------------------------+
| Logic Utilization           | Used     | Available     | Utilization(%)     
+------------------------------------------------------------------------------+
| Use of ADC                  | 0        | 1             | 0                  
| Use of ANALOG               | 0        | 1             | 0                  
| Use of APM                  | 0        | 120           | 0                  
| Use of BKCL                 | 4        | 5             | 80                 
| Use of CCS                  | 1        | 1             | 100                
| Use of CLMA                 | 2544     | 6575          | 39                 
|   FF                        | 8759     | 52600         | 17                 
|   LUT                       | 7109     | 26300         | 28                 
|   LUT-FF pairs              | 3993     | 26300         | 16                 
| Use of CLMS                 | 858      | 2375          | 37                 
|   FF                        | 2563     | 19000         | 14                 
|   LUT                       | 2449     | 9500          | 26                 
|   LUT-FF pairs              | 1231     | 9500          | 13                 
|   Distributed RAM           | 618      | 9500          | 7                  
| Use of DDRPHY_CPD           | 1        | 10            | 10                 
| Use of DDRPHY_IOCLK_DIV     | 2        | 5             | 40                 
| Use of DDR_PHY              | 5        | 20            | 25                 
| Use of DRM                  | 72.5     | 85            | 86                 
| Use of GCLK_INBUF_SYN       | 0        | 20            | 0                  
| Use of GPLL                 | 3        | 5             | 60                 
| Use of GSEB                 | 0        | 123           | 0                  
| Use of HARD0                | 1236     | 5850          | 22                 
| Use of HCKB                 | 29       | 72            | 41                 
|  HCKB dataused              | 0        | 72            | 0                  
| Use of HCKMUX_TEST          | 0        | 6             | 0                  
| Use of HSSTLP               | 0.5      | 1             | 50                 
| Use of IO                   | 73       | 250           | 30                 
|   IOBD                      | 35       | 120           | 30                 
|   IOBS                      | 38       | 130           | 30                 
| Use of IOCKB                | 0        | 20            | 0                  
| Use of IOCKMUX_TEST         | 0        | 5             | 0                  
| Use of IOLHR                | 73       | 250           | 30                 
| Use of KEYRAM               | 0        | 1             | 0                  
| Use of MFG_TEST             | 0        | 1             | 0                  
| Use of MRCKB                | 1        | 10            | 10                 
| Use of MRCKMUX_TEST         | 0        | 5             | 0                  
| Use of MRPOSTMUX_TEST       | 0        | 5             | 0                  
| Use of PCIE                 | 1        | 1             | 100                
| Use of PCKMUX_TEST          | 0        | 10            | 0                  
| Use of PLLMRMUX_TEST        | 0        | 5             | 0                  
| Use of PLLREFMUX_TEST       | 0        | 5             | 0                  
| Use of PPLL                 | 2        | 5             | 40                 
| Use of PREGMUXC_TEST        | 0        | 3             | 0                  
| Use of PREGMUXLR_TEST       | 0        | 5             | 0                  
| Use of RCKB                 | 3        | 20            | 15                 
|  RCKB dataused              | 0        | 20            | 0                  
| Use of RCKMUX_TEST          | 0        | 5             | 0                  
| Use of SCANCHAIN            | 1        | 1             | 100                
| Use of SCKMUX_TEST          | 0        | 10            | 0                  
| Use of SFB                  | 0        | 1375          | 0                  
| Use of SPAD                 | 2        | 4             | 50                 
| Use of TSERDES              | 10       | 40            | 25                 
| Use of USCM                 | 9        | 32            | 29                 
|  USCM dataused              | 0        | 32            | 0                  
| Use of USCMMUX_TEST         | 0        | 32            | 0                  
+------------------------------------------------------------------------------+

Finished routing.
Design 'pcie_dma_test' has been placed and routed successfully.
Saving design to DB.
Finished placement and routing.
Action pnr: Real time elapsed is 0h:2m:17s
Action pnr: CPU time elapsed is 0h:2m:7s
Action pnr: Process CPU time elapsed is 0h:3m:14s
Current time: Tue Nov  4 23:08:04 2025
Action pnr: Peak memory pool usage is 2,102 MB
