(_flow fab_demo "2022.2-SP6.4"
    (_comment "Generated by Fabric Compiler (version on 2022.2-SP6.4<build 146967>) at Fri Nov  7 01:35:08 2025")
    (_version "1.1.0")
    (_status "initial")
    (_project 
        (_option prj_work_dir (_string "."))
        (_option prj_impl_dir (_string "."))
    )
    (_task tsk_setup
        (_widget wgt_select_arch
            (_input
                (_part
                    (_family Logos2)
                    (_device PG2L50H)
                    (_speedgrade -6)
                    (_package FBG484)
                )
            )
        )
        (_widget wgt_my_design_src
            (_input
                (_file "hdl/uart2apb_32bit/pgr_apb_ctr_32bit.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:44")
                )
                (_file "hdl/uart2apb_32bit/pgr_apb_mif_32bit.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:44")
                )
                (_file "hdl/uart2apb_32bit/pgr_clk_gen_32bit.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:46")
                )
                (_file "hdl/uart2apb_32bit/pgr_cmd_parser_32bit.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:46")
                )
                (_file "hdl/uart2apb_32bit/pgr_fifo_top_32bit.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:46")
                )
                (_file "hdl/uart2apb_32bit/pgr_uart_rx_32bit.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:46")
                )
                (_file "hdl/uart2apb_32bit/pgr_uart_top_32bit.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:46")
                )
                (_file "hdl/uart2apb_32bit/pgr_uart_tx_32bit.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:48")
                )
                (_file "hdl/uart2apb_32bit/pgr_uart2apb_top_32bit.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:48")
                )
                (_file "hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_ctr_v1_0.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:11:18")
                )
                (_file "hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_v1_1.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:11:18")
                )
                (_file "hdl/uart2apb_32bit/fifo/pgm_distributed_sdpram_v1_1.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:11:20")
                )
                (_file "hdl/uart2apb_32bit/fifo/pgr_prefetch_fifo.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:11:20")
                )
                (_file "hdl/pcie_dma_ctrl/ipm_distributed_sdpram_v1_2.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:40")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_expd_apb_mux.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:40")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma.v"
                    (_format verilog)
                    (_timespec "2025-10-18T19:05:04")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_controller.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:40")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_cpld_tx_ctrl.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:40")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_mrd_tx_ctrl.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:42")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_mwr_tx_ctrl.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:42")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_rd_ctrl.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:42")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_cpld_wr_ctrl.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:42")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_mwr_wr_ctrl.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:42")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_top.v"
                    (_format verilog)
                    (_timespec "2025-10-18T19:05:08")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_tlp_rcv.v"
                    (_format verilog)
                    (_timespec "2025-10-13T22:40:18")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_tlp_tx_mux.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:44")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_cpld_rd_ctrl.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:44")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_mwr_rd_ctrl.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:44")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v"
                    (_format verilog)
                    (_timespec "2025-10-14T23:26:06")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_wr_ctrl.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:44")
                )
                (_file "hdl/pcie_dma_ctrl/pgs_pciex4_prefetch_fifo_v1_2.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:09:44")
                )
                (_file "hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_ctrl.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:11:18")
                )
                (_file "hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_v1_2.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:11:18")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/ips2l_pcie_dma_ram.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:11:18")
                )
                (_file "hdl/pcie_dma_ctrl/fifo/ipm_distributed_sdpram_v1_2_distributed_fifo.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:11:16")
                )
                (_file "hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:12:18")
                )
                (_file "hdl/pcie_dma_test.v" + "pcie_dma_test"
                    (_format verilog)
                    (_timespec "2025-11-07T01:32:35")
                )
                (_file "my_code_file/IIc_text/i2cSlave.v"
                    (_format verilog)
                    (_timespec "2025-10-16T18:20:36")
                )
                (_file "my_code_file/IIc_text/i2cSlave_define.v"
                    (_format verilog)
                    (_timespec "2025-01-13T22:09:48")
                )
                (_file "my_code_file/IIc_text/registerInterface.v"
                    (_format verilog)
                    (_timespec "2025-10-16T18:59:04")
                )
                (_file "my_code_file/IIc_text/serialInterface.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:10:32")
                )
                (_file "my_code_file/IIc_text/timescale.v"
                    (_format verilog)
                    (_timespec "2024-12-26T17:10:32")
                )
                (_file "my_code_file/OV5640/cmos_8_16bit.v"
                    (_format verilog)
                    (_timespec "2025-10-21T00:00:06")
                )
                (_file "my_code_file/OV5640/i2c_com.v"
                    (_format verilog)
                    (_timespec "2023-03-20T09:41:14")
                )
                (_file "my_code_file/OV5640/power_on_delay.v"
                    (_format verilog)
                    (_timespec "2023-03-29T15:21:02")
                )
                (_file "my_code_file/OV5640/reg_config.v"
                    (_format verilog)
                    (_timespec "2025-10-22T21:18:30")
                )
                (_file "my_code_file/SXT/rgb565_to_rgb888.v"
                    (_format verilog)
                    (_timespec "2025-10-22T00:50:40")
                )
                (_file "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m.v"
                    (_format verilog)
                    (_timespec "2024-01-07T06:29:54")
                )
                (_file "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/eth_img_rec.v"
                    (_format verilog)
                    (_timespec "2025-11-07T00:39:38")
                )
                (_file "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/pcie_dma_ctrl.v"
                    (_format verilog)
                    (_timespec "2024-01-07T06:29:54")
                )
            )
        )
        (_widget wgt_my_ips_src
            (_input
                (_ip "ipcore/pcie_test/pcie_test.idf"
                    (_timespec "2025-10-12T12:26:40")
                    (_ip_source_item "ipcore/pcie_test/rtl/ips2l_pcie_apb_cross_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/ips2l_pcie_apb_mux_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/ips2l_pcie_apb2dbi_v1_1.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/ips2l_pcie_cfg_init_v1_7.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/ips2l_pcie_pll_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/ips2l_pcie_top_v1_8.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/ips2l_pcie_seio_intf_v1_2.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rcv_data_ram.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rcv_header_ram.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/external_ram/retry_data_ram/retry_data_ram.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_cross_sync_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_debounce_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_wtchdg_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsstl_phy_mac_rdata_proc.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_fsm_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_rst_fsm_v1_1.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsst_pipe/ips_hsst_rst_sync_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x1_top.v"
                        (_timespec "2025-10-12T12:26:40")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v"
                        (_timespec "2025-10-12T12:26:40")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x4_top.v"
                        (_timespec "2025-10-12T12:26:40")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_apb_bridge_v1_2.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_fifo_clr_v1_3.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_pll_rst_fsm_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_debounce_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_pll_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_rx_v1_6.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_sync_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_tx_v1_6.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_v1_6.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_wtchdg_v1_0.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rxlane_rst_fsm_v1_6.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_txlane_rst_fsm_v1_6.v"
                        (_timespec "2025-09-18T10:47:38")
                    )
                    (_ip_source_item "ipcore/pcie_test/pcie_test.v"
                        (_timespec "2025-10-12T12:26:40")
                    )
                )
                (_ip "ipcore/PLL/PLL.idf"
                    (_timespec "2025-10-22T21:19:52")
                    (_ip_source_item "ipcore/PLL/PLL.v"
                        (_timespec "2025-10-22T21:19:52")
                    )
                )
                (_ip "my_code_file/DDR3/ip_core/ddr3/ddr3.idf"
                    (_timespec "2025-11-04T23:30:04")
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp"
                        (_timespec "2024-01-31T01:20:58")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/ddr3.v"
                        (_timespec "2025-11-04T23:30:04")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v"
                        (_timespec "2025-11-04T23:30:04")
                    )
                    (_ip_source_item "my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v"
                        (_timespec "2025-11-04T23:30:04")
                    )
                )
                (_ip "ipcore/SXT1_FIFO/SXT1_FIFO.idf"
                    (_timespec "2025-11-03T23:51:12")
                    (_ip_source_item "ipcore/SXT1_FIFO/rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v"
                        (_timespec "2025-11-03T23:51:12")
                    )
                    (_ip_source_item "ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v"
                        (_timespec "2025-11-03T23:51:12")
                    )
                    (_ip_source_item "ipcore/SXT1_FIFO/rtl/ipm2l_fifo_v1_10_SXT1_FIFO.v"
                        (_timespec "2025-11-03T23:51:12")
                    )
                    (_ip_source_item "ipcore/SXT1_FIFO/SXT1_FIFO.v"
                        (_timespec "2025-11-03T23:51:12")
                    )
                )
                (_ip "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/eth_pkt_fifo.idf"
                    (_timespec "2025-09-16T20:23:11")
                    (_ip_source_item "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_fifo_ctrl_v1_3.v"
                        (_timespec "2024-01-07T06:29:54")
                    )
                    (_ip_source_item "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v"
                        (_timespec "2024-01-07T06:29:54")
                    )
                    (_ip_source_item "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_fifo_v1_6_eth_pkt_fifo.v"
                        (_timespec "2024-01-07T06:29:54")
                    )
                    (_ip_source_item "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/eth_pkt_fifo.v"
                        (_timespec "2024-01-07T06:29:54")
                    )
                )
                (_ip "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/hdmi_pcie_fifo.idf"
                    (_timespec "2025-09-16T20:02:44")
                    (_ip_source_item "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_fifo_ctrl_v1_3.v"
                        (_timespec "2024-01-07T06:29:54")
                    )
                    (_ip_source_item "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v"
                        (_timespec "2024-01-07T06:29:54")
                    )
                    (_ip_source_item "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_fifo_v1_6_hdmi_pcie_fifo.v"
                        (_timespec "2024-01-07T06:29:54")
                    )
                    (_ip_source_item "E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/hdmi_pcie_fifo.v"
                        (_timespec "2024-01-07T06:29:54")
                    )
                )
            )
        )
        (_widget wgt_import_logic_con_file
            (_input
                (_file "fdc/pcie_dma_test.fdc"
                    (_format fdc)
                    (_timespec "2025-11-07T01:05:35")
                )
            )
        )
        (_widget wgt_edit_user_cons
            (_attribute _click_to_run (_switch ON))
        )
        (_widget wgt_simulation
            (_option compiled_lib_location (_string ""))
            (_option verilog_options (_string ""))
            (_option gen_param (_string ""))
            (_option sim_exe_dir (_string ""))
        )
    )
    (_task tsk_compile
        (_command cmd_compile
            (_gci_state (_integer 2))
            (_db_output
                (_file "compile/pcie_dma_test_comp.adf"
                    (_format adif)
                    (_timespec "2025-11-07T01:34:01")
                )
            )
            (_output
                (_file "compile/pcie_dma_test.cmr"
                    (_format verilog)
                    (_timespec "2025-11-07T01:34:01")
                )
                (_file "compile/cmr.db"
                    (_format text)
                    (_timespec "2025-11-07T01:34:02")
                )
            )
        )
        (_widget wgt_rtl_view
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_synthesis
        (_command cmd_synthesize
            (_gci_state (_integer 2))
            (_option selected_syn_tool_opt (_integer 2))
            (_db_output
                (_file "synthesize/pcie_dma_test_syn.adf"
                    (_format adif)
                    (_timespec "2025-11-07T01:35:02")
                )
            )
            (_output
                (_file "synthesize/pcie_dma_test_syn.vm"
                    (_format structural_verilog)
                    (_timespec "2025-11-07T01:35:05")
                )
                (_file "synthesize/pcie_dma_test_controlsets.txt"
                    (_format text)
                    (_timespec "2025-11-07T01:34:50")
                )
                (_file "synthesize/snr.db"
                    (_format text)
                    (_timespec "2025-11-07T01:35:08")
                )
                (_file "synthesize/pcie_dma_test.snr"
                    (_format text)
                    (_timespec "2025-11-07T01:35:08")
                )
            )
        )
        (_widget wgt_tech_view
            (_attribute _click_to_run (_switch ON))
        )
        (_widget wgt_map_constraint
        )
        (_widget wgt_my_fic_src
            (_input
                (_file "synthesize/pcie_dma_test_syn.fic"
                    (_format text)
                    (_timespec "2025-11-04T20:13:10")
                )
            )
        )
        (_widget wgt_inserter_gui_view
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_devmap
        (_command cmd_devmap
            (_gci_state (_integer 0))
        )
        (_widget wgt_edit_placement_cons
            (_attribute _click_to_run (_switch ON))
            (_input
                (_file "device_map/dram_pcie.pcf"
                    (_format pcf)
                    (_timespec "2025-11-06T19:59:13")
                )
            )
        )
        (_widget wgt_edit_route_cons
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_pnr
        (_command cmd_pnr
            (_gci_state (_integer 0))
        )
        (_widget wgt_power_calculator
            (_attribute _click_to_run (_switch ON))
        )
        (_widget wgt_timing_analysis
            (_attribute _click_to_run (_switch ON))
        )
        (_command cmd_report_post_pnr_timing
            (_gci_state (_integer 0))
            (_attribute _auto_exe_lock (_switch OFF))
        )
        (_widget wgt_arch_browser
            (_attribute _click_to_run (_switch ON))
        )
        (_command cmd_report_power
            (_gci_state (_integer 0))
            (_attribute _auto_exe_lock (_switch OFF))
            (_attribute _auto_exe (_switch OFF))
        )
        (_command cmd_gen_netlist
            (_gci_state (_integer 0))
            (_attribute _auto_exe_lock (_switch OFF))
            (_attribute _auto_exe (_switch OFF))
        )
    )
    (_task tsk_gen_bitstream
        (_command cmd_gen_bitstream
            (_gci_state (_integer 0))
            (_option compress_bitstream (_boolean TRUE))
            (_option master_configuration_clock_frequency (_string "40M"))
        )
    )
)
