
----------------------------------------------------------------------------------------------------
| Tool Version : Fabric Compiler (version 2022.2-SP6.4 <build 146967>)
| Date         : Wed Jan  8 10:20:19 2025
| Design       : test_ddr
| Device       : PG2L50H
| Speed Grade  : -6
| Package      : FBG484
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
| Timing Models: Production
| Tcl Command  : report_timing 
----------------------------------------------------------------------------------------------------

Timing analysis mode : multi corner

 Clock Summary:                                                                                                                                                                                                     
********************************************************************************************************************************************************************************************************************
                                                                                      Clock   Non-clock                                                                                                             
 Clock                    Period       Waveform            Type                       Loads       Loads  Sources                                                                                                    
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 ref_clk                  40.0000      {0.0000 20.0000}    Declared                     576          15  {free_clk}                                                                                                 
   rst_clk                40.0000      {0.0000 20.0000}    Generated (ref_clk)          126          37  {I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0}                                         
   ddrphy_sysclk          7.6190       {0.0000 3.8090}     Generated (ref_clk)         3372         247  {I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0}                                          
   phy_dq_clk_0           0.9524       {0.0000 0.4760}     Generated (ref_clk)           35           1  {I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY}         
     phy_dq_sysclk_0      7.6190       {1.9040 5.7140}     Generated (phy_dq_clk_0)      35           0  {I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT} 
   phy_dq_clk_1           0.9524       {0.0000 0.4760}     Generated (ref_clk)           42           1  {I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY}         
     phy_dq_sysclk_1      7.6190       {1.9040 5.7140}     Generated (phy_dq_clk_1)      42           0  {I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT} 
====================================================================================================================================================================================================================

 Clock Groups:                                                                                      
****************************************************************************************************
 Clock Group                   Group Type                 Clocks                                    
----------------------------------------------------------------------------------------------------
 ref_clk                       asynchronous               ref_clk                                   
 rst_clk                       asynchronous               rst_clk                                   
 phy_dq_clk_0                  asynchronous               phy_dq_clk_0                              
 phy_dq_clk_1                  asynchronous               phy_dq_clk_1                              
====================================================================================================

 Performance Summary:                                                                               
****************************************************************************************************
                              Requested       Estimated      Requested      Estimated               
 Clock                        Frequency       Frequency      Period         Period             Slack
----------------------------------------------------------------------------------------------------
 ref_clk                    25.0000 MHz    206.3558 MHz        40.0000         4.8460         35.154
 rst_clk                    25.0000 MHz    245.2784 MHz        40.0000         4.0770         35.923
 ddrphy_sysclk             131.2500 MHz    166.5546 MHz         7.6190         6.0040          1.615
====================================================================================================

Design Summary : All Constraints Met.

Setup Summary(Slow Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                     35.154       0.000              0           1397
 rst_clk                rst_clk                     35.923       0.000              0            560
 ddrphy_sysclk          ddrphy_sysclk                1.615       0.000              0          13362
 phy_dq_sysclk_1        ddrphy_sysclk                1.936       0.000              0            130
 phy_dq_sysclk_0        ddrphy_sysclk                3.633       0.000              0              1
 ddrphy_sysclk          phy_dq_sysclk_0              1.522       0.000              0            196
 ddrphy_sysclk          phy_dq_sysclk_1              0.547       0.000              0            210
====================================================================================================

Hold Summary(Slow Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                      0.196       0.000              0           1397
 rst_clk                rst_clk                      0.193       0.000              0            560
 ddrphy_sysclk          ddrphy_sysclk                0.143       0.000              0          13362
 phy_dq_sysclk_1        ddrphy_sysclk                0.590       0.000              0            130
 phy_dq_sysclk_0        ddrphy_sysclk                0.929       0.000              0              1
 ddrphy_sysclk          phy_dq_sysclk_0              0.452       0.000              0            196
 ddrphy_sysclk          phy_dq_sysclk_1              0.457       0.000              0            210
====================================================================================================

Recovery Summary(Slow Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                     37.655       0.000              0            574
 rst_clk                rst_clk                     37.621       0.000              0            124
 ddrphy_sysclk          ddrphy_sysclk                4.770       0.000              0           3345
====================================================================================================

Removal Summary(Slow Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                      0.359       0.000              0            574
 rst_clk                rst_clk                      0.369       0.000              0            124
 ddrphy_sysclk          ddrphy_sysclk                0.275       0.000              0           3345
====================================================================================================

Minimum Pulse Width Summary(Slow Corner):
****************************************************************************************************
                                                                         WPWS Failing     WPWS Total
 Clock                                            WPWS(ns)    TPWS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                                            19.800       0.000              0            575
 rst_clk                                            19.800       0.000              0            125
 ddrphy_sysclk                                       3.609       0.000              0           3371
 phy_dq_clk_0                                        0.011       0.000              0             35
 phy_dq_sysclk_0                                     1.659       0.000              0             35
 phy_dq_clk_1                                        0.011       0.000              0             42
 phy_dq_sysclk_1                                     2.209       0.000              0             42
====================================================================================================

Setup Summary(Fast Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                     37.146       0.000              0           1397
 rst_clk                rst_clk                     37.669       0.000              0            560
 ddrphy_sysclk          ddrphy_sysclk                4.159       0.000              0          13362
 phy_dq_sysclk_1        ddrphy_sysclk                3.978       0.000              0            130
 phy_dq_sysclk_0        ddrphy_sysclk                4.813       0.000              0              1
 ddrphy_sysclk          phy_dq_sysclk_0              3.776       0.000              0            196
 ddrphy_sysclk          phy_dq_sysclk_1              3.365       0.000              0            210
====================================================================================================

Hold Summary(Fast Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                      0.132       0.000              0           1397
 rst_clk                rst_clk                      0.112       0.000              0            560
 ddrphy_sysclk          ddrphy_sysclk                0.100       0.000              0          13362
 phy_dq_sysclk_1        ddrphy_sysclk                0.101       0.000              0            130
 phy_dq_sysclk_0        ddrphy_sysclk                0.246       0.000              0              1
 ddrphy_sysclk          phy_dq_sysclk_0              0.099       0.000              0            196
 ddrphy_sysclk          phy_dq_sysclk_1              0.097       0.000              0            210
====================================================================================================

Recovery Summary(Fast Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                     38.530       0.000              0            574
 rst_clk                rst_clk                     38.496       0.000              0            124
 ddrphy_sysclk          ddrphy_sysclk                5.831       0.000              0           3345
====================================================================================================

Removal Summary(Fast Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                      0.237       0.000              0            574
 rst_clk                rst_clk                      0.239       0.000              0            124
 ddrphy_sysclk          ddrphy_sysclk                0.176       0.000              0           3345
====================================================================================================

Minimum Pulse Width Summary(Fast Corner):
****************************************************************************************************
                                                                         WPWS Failing     WPWS Total
 Clock                                            WPWS(ns)    TPWS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                                            19.800       0.000              0            575
 rst_clk                                            19.800       0.000              0            125
 ddrphy_sysclk                                       3.609       0.000              0           3371
 phy_dq_clk_0                                        0.011       0.000              0             35
 phy_dq_sysclk_0                                     1.659       0.000              0             35
 phy_dq_clk_1                                        0.011       0.000              0             42
 phy_dq_sysclk_1                                     2.209       0.000              0             42
====================================================================================================

Slow Corner
****************************************************************************************************
====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.216  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.334
  Launch Clock Delay      :  3.900
  Clock Pessimism Removal :  0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.469       3.900         _N111            
 CLMA_171_342/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMA_171_342/Q2                   tco                   0.213       4.113 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      1.352       5.465         uart_read_addr[4]
 CLMS_255_313/Y1                   td                    0.113       5.578 r       u_uart_rd_lock/N214_37[9]_2/LUT6D_inst_perm/L6
                                   net (fanout=32)       1.269       6.847         _N41416          
 CLMA_177_336/Y2                   td                    0.240       7.087 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N500/LUT6_inst_perm/L6
                                   net (fanout=32)       1.155       8.242         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N500
 CLMA_147_385/CE                                                           r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/CE

 Data arrival time                                                   8.242         Logic Levels: 2  
                                                                                   Logic: 0.566ns(13.035%), Route: 3.776ns(86.965%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.391      43.334         _N109            
 CLMA_147_385/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/CLK
 clock pessimism                                         0.350      43.684                          
 clock uncertainty                                      -0.050      43.634                          

 Setup time                                             -0.238      43.396                          

 Data required time                                                 43.396                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.396                          
 Data arrival time                                                   8.242                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        35.154                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[23]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.216  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.334
  Launch Clock Delay      :  3.900
  Clock Pessimism Removal :  0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.469       3.900         _N111            
 CLMA_171_342/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMA_171_342/Q2                   tco                   0.213       4.113 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      1.352       5.465         uart_read_addr[4]
 CLMS_255_313/Y1                   td                    0.113       5.578 r       u_uart_rd_lock/N214_37[9]_2/LUT6D_inst_perm/L6
                                   net (fanout=32)       1.269       6.847         _N41416          
 CLMA_177_336/Y2                   td                    0.240       7.087 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N500/LUT6_inst_perm/L6
                                   net (fanout=32)       1.155       8.242         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N500
 CLMA_147_385/CE                                                           r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[23]/opit_0_inv/CE

 Data arrival time                                                   8.242         Logic Levels: 2  
                                                                                   Logic: 0.566ns(13.035%), Route: 3.776ns(86.965%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.391      43.334         _N109            
 CLMA_147_385/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[23]/opit_0_inv/CLK
 clock pessimism                                         0.350      43.684                          
 clock uncertainty                                      -0.050      43.634                          

 Setup time                                             -0.238      43.396                          

 Data required time                                                 43.396                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.396                          
 Data arrival time                                                   8.242                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        35.154                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_2[27]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.074  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.338
  Launch Clock Delay      :  3.900
  Clock Pessimism Removal :  0.488

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.469       3.900         _N111            
 CLMA_171_342/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMA_171_342/Q2                   tco                   0.213       4.113 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      1.352       5.465         uart_read_addr[4]
 CLMS_255_313/Y1                   td                    0.113       5.578 r       u_uart_rd_lock/N214_37[9]_2/LUT6D_inst_perm/L6
                                   net (fanout=32)       1.347       6.925         _N41416          
 CLMA_171_343/CR1                  td                    0.222       7.147 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N227/LUT6D_inst_perm/L5
                                   net (fanout=32)       1.083       8.230         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N296
 CLMS_207_379/CE                                                           r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_2[27]/opit_0_inv/CE

 Data arrival time                                                   8.230         Logic Levels: 2  
                                                                                   Logic: 0.548ns(12.656%), Route: 3.782ns(87.344%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.395      43.338         _N111            
 CLMS_207_379/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_2[27]/opit_0_inv/CLK
 clock pessimism                                         0.488      43.826                          
 clock uncertainty                                      -0.050      43.776                          

 Setup time                                             -0.238      43.538                          

 Data required time                                                 43.538                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.538                          
 Data arrival time                                                   8.230                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        35.308                          
====================================================================================================

====================================================================================================

Startpoint  : u_adc_ctrl/paddr[0]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : u_adc_ctrl/dbg_temp_rd_pos_d[1]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.887
  Launch Clock Delay      :  3.326
  Clock Pessimism Removal :  -0.561

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.383       3.326         _N109            
 CLMA_147_432/CLK                                                          r       u_adc_ctrl/paddr[0]/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_147_432/Q1                   tco                   0.166       3.492 f       u_adc_ctrl/paddr[0]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=2)        0.075       3.567         u_adc_ctrl/dbg_temp_rd_pos_d [0]
 CLMA_147_432/M3                                                           f       u_adc_ctrl/dbg_temp_rd_pos_d[1]/opit_0_inv/D

 Data arrival time                                                   3.567         Logic Levels: 0  
                                                                                   Logic: 0.166ns(68.880%), Route: 0.075ns(31.120%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.456       3.887         _N109            
 CLMA_147_432/CLK                                                          r       u_adc_ctrl/dbg_temp_rd_pos_d[1]/opit_0_inv/CLK
 clock pessimism                                        -0.561       3.326                          
 clock uncertainty                                       0.000       3.326                          

 Hold time                                               0.045       3.371                          

 Data required time                                                  3.371                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.371                          
 Data arrival time                                                   3.567                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.196                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[0]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[8]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.211  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.896
  Launch Clock Delay      :  3.335
  Clock Pessimism Removal :  -0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.392       3.335         _N111            
 CLMA_171_361/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[0]/opit_0_inv/CLK

 CLMA_171_361/Q0                   tco                   0.166       3.501 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[0]/opit_0_inv/Q
                                   net (fanout=14)       0.298       3.799         u_ips2l_uart_ctrl/u_uart_ctrl/data [8]
 CLMA_159_372/BD                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[8]/opit_0_inv/D

 Data arrival time                                                   3.799         Logic Levels: 0  
                                                                                   Logic: 0.166ns(35.776%), Route: 0.298ns(64.224%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.465       3.896         _N109            
 CLMA_159_372/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[8]/opit_0_inv/CLK
 clock pessimism                                        -0.350       3.546                          
 clock uncertainty                                       0.000       3.546                          

 Hold time                                               0.046       3.592                          

 Data required time                                                  3.592                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.592                          
 Data arrival time                                                   3.799                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.207                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b2[7]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[23]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.213  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.898
  Launch Clock Delay      :  3.335
  Clock Pessimism Removal :  -0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.392       3.335         _N109            
 CLMA_159_366/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b2[7]/opit_0_inv/CLK

 CLMA_159_366/Q0                   tco                   0.166       3.501 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b2[7]/opit_0_inv/Q
                                   net (fanout=14)       0.300       3.801         u_ips2l_uart_ctrl/u_uart_ctrl/data [23]
 CLMA_171_354/BD                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[23]/opit_0_inv/D

 Data arrival time                                                   3.801         Logic Levels: 0  
                                                                                   Logic: 0.166ns(35.622%), Route: 0.300ns(64.378%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.467       3.898         _N111            
 CLMA_171_354/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[23]/opit_0_inv/CLK
 clock pessimism                                        -0.350       3.548                          
 clock uncertainty                                       0.000       3.548                          

 Hold time                                               0.046       3.594                          

 Data required time                                                  3.594                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.594                          
 Data arrival time                                                   3.801                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.207                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/tran_err_rst_cnt[5]/opit_0_inv_L6QL5Q1_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/I1
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.211  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.665
  Launch Clock Delay      :  5.508
  Clock Pessimism Removal :  0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=74)       0.475       5.508         _N115            
 CLMA_201_337/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/tran_err_rst_cnt[5]/opit_0_inv_L6QL5Q1_perm/CLK

 CLMA_201_337/CR1                  tco                   0.264       5.772 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/tran_err_rst_cnt[5]/opit_0_inv_L6QL5Q1_perm/L5Q
                                   net (fanout=3)        0.581       6.353         dbg_tran_err_rst_cnt[4]
 CLMA_195_330/Y2                   td                    0.235       6.588 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N161_1_3/LUT6_inst_perm/L6
                                   net (fanout=2)        0.652       7.240         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N46865
 CLMS_177_325/Y3                   td                    0.101       7.341 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_9/gateop_perm/L6
                                   net (fanout=3)        0.297       7.638         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N40242
 CLMA_171_318/Y1                   td                    0.078       7.716 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_107/gateop_perm/L6
                                   net (fanout=2)        0.391       8.107         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N42219
 CLMA_171_307/Y1                   td                    0.235       8.342 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_49/gateop_LUT6DL5_perm/L6
                                   net (fanout=1)        0.606       8.948         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N48
 CLMS_159_313/B1                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/I1

 Data arrival time                                                   8.948         Logic Levels: 4  
                                                                                   Logic: 0.913ns(26.541%), Route: 2.527ns(73.459%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.402      44.665         _N116            
 CLMS_159_313/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/CLK
 clock pessimism                                         0.632      45.297                          
 clock uncertainty                                      -0.150      45.147                          

 Setup time                                             -0.276      44.871                          

 Data required time                                                 44.871                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.871                          
 Data arrival time                                                   8.948                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        35.923                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CE
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.665
  Launch Clock Delay      :  5.508
  Clock Pessimism Removal :  0.843

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.475       5.508         _N116            
 CLMA_147_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CLK

 CLMA_147_325/Q0                   tco                   0.213       5.721 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=2)        0.734       6.455         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [18]
 CLMA_147_307/Y3                   td                    0.113       6.568 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=2)        0.283       6.851         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N46855
 CLMA_147_313/Y1                   td                    0.235       7.086 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_1/gateop_perm/L6
                                   net (fanout=11)       0.586       7.672         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N49
 CLMA_147_288/Y0                   td                    0.101       7.773 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_deb_pre/opit_0_inv_L5Q_perm/L6
                                   net (fanout=10)       0.600       8.373         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43
 CLMA_147_319/CECO                 td                    0.143       8.516 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L6Q_perm/CECO
                                   net (fanout=1)        0.000       8.516         ntR23            
 CLMA_147_325/CECI                                                         r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CE

 Data arrival time                                                   8.516         Logic Levels: 4  
                                                                                   Logic: 0.805ns(26.762%), Route: 2.203ns(73.238%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.402      44.665         _N116            
 CLMA_147_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.843      45.508                          
 clock uncertainty                                      -0.150      45.358                          

 Setup time                                             -0.238      45.120                          

 Data required time                                                 45.120                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 45.120                          
 Data arrival time                                                   8.516                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        36.604                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L6QL5Q_perm/CE
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.028  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.666
  Launch Clock Delay      :  5.508
  Clock Pessimism Removal :  0.814

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.475       5.508         _N116            
 CLMA_147_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CLK

 CLMA_147_325/Q0                   tco                   0.213       5.721 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=2)        0.734       6.455         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [18]
 CLMA_147_307/Y3                   td                    0.113       6.568 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=2)        0.283       6.851         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N46855
 CLMA_147_313/Y1                   td                    0.235       7.086 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_1/gateop_perm/L6
                                   net (fanout=11)       0.586       7.672         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N49
 CLMA_147_288/Y0                   td                    0.101       7.773 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_deb_pre/opit_0_inv_L5Q_perm/L6
                                   net (fanout=10)       0.600       8.373         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43
 CLMA_147_319/CE                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L6QL5Q_perm/CE

 Data arrival time                                                   8.373         Logic Levels: 3  
                                                                                   Logic: 0.662ns(23.106%), Route: 2.203ns(76.894%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.403      44.666         _N116            
 CLMA_147_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                         0.814      45.480                          
 clock uncertainty                                      -0.150      45.330                          

 Setup time                                             -0.238      45.092                          

 Data required time                                                 45.092                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 45.092                          
 Data arrival time                                                   8.373                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        36.719                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[9]/opit_0_inv_AQ_perm/CIN
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.209  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.519
  Launch Clock Delay      :  4.678
  Clock Pessimism Removal :  -0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.415       4.678         _N114            
 CLMA_231_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/CLK

 CLMA_231_301/Q1                   tco                   0.166       4.844 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[6]/opit_0_inv_AQ_perm/Q
                                   net (fanout=7)        0.093       4.937         debug_dps_cnt_dir0[6]
 CLMA_231_301/COUT                 td                    0.137       5.074 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/COUT
                                   net (fanout=1)        0.000       5.074         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/_N7780
 CLMA_231_307/CIN                                                          f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[9]/opit_0_inv_AQ_perm/CIN

 Data arrival time                                                   5.074         Logic Levels: 1  
                                                                                   Logic: 0.303ns(76.515%), Route: 0.093ns(23.485%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=74)       0.486       5.519         _N115            
 CLMA_231_307/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[9]/opit_0_inv_AQ_perm/CLK
 clock pessimism                                        -0.632       4.887                          
 clock uncertainty                                       0.000       4.887                          

 Hold time                                              -0.006       4.881                          

 Data required time                                                  4.881                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.881                          
 Data arrival time                                                   5.074                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.193                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[0]/opit_0_inv_L6Q_perm/I2
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.209  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.519
  Launch Clock Delay      :  4.678
  Clock Pessimism Removal :  -0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.415       4.678         _N114            
 CLMA_231_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/CLK

 CLMA_231_301/Q1                   tco                   0.166       4.844 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[6]/opit_0_inv_AQ_perm/Q
                                   net (fanout=7)        0.166       5.010         debug_dps_cnt_dir0[6]
 CLMA_231_307/B2                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[0]/opit_0_inv_L6Q_perm/I2

 Data arrival time                                                   5.010         Logic Levels: 0  
                                                                                   Logic: 0.166ns(50.000%), Route: 0.166ns(50.000%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=74)       0.486       5.519         _N115            
 CLMA_231_307/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[0]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                        -0.632       4.887                          
 clock uncertainty                                       0.000       4.887                          

 Hold time                                              -0.084       4.803                          

 Data required time                                                  4.803                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.803                          
 Data arrival time                                                   5.010                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.207                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_up_d[0]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_up_d[2]/opit_0_inv/D
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.208  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.504
  Launch Clock Delay      :  4.664
  Clock Pessimism Removal :  -0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.401       4.664         _N116            
 CLMA_153_324/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_up_d[0]/opit_0_inv_srl/CLK

 CLMA_153_324/CR0                  tco                   0.182       4.846 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_up_d[0]/opit_0_inv_srl/CR0
                                   net (fanout=3)        0.298       5.144         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_up_d [1]
 CLMA_171_330/BD                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_up_d[2]/opit_0_inv/D

 Data arrival time                                                   5.144         Logic Levels: 0  
                                                                                   Logic: 0.182ns(37.917%), Route: 0.298ns(62.083%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=74)       0.471       5.504         _N115            
 CLMA_171_330/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_up_d[2]/opit_0_inv/CLK
 clock pessimism                                        -0.632       4.872                          
 clock uncertainty                                       0.000       4.872                          

 Hold time                                               0.046       4.918                          

 Data required time                                                  4.918                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.918                          
 Data arrival time                                                   5.144                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.226                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_value[6]/opit_0_inv_L6Q_perm/I2
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.075  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.346
  Launch Clock Delay      :  5.813
  Clock Pessimism Removal :  1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.480       5.813         _N105            
 CLMA_219_265/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L6Q_perm/CLK

 CLMA_219_265/Q1                   tco                   0.213       6.026 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=13)       0.767       6.793         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dqs_gate_vld
 CLMA_201_276/Y2                   td                    0.235       7.028 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N40_13[2]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.417       7.445         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/_N14305
 CLMA_195_282/Y3                   td                    0.223       7.668 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N40_16[2]_3/gateop_perm/L6
                                   net (fanout=2)        0.283       7.951         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_next [2]
 CLMA_201_282/Y2                   td                    0.101       8.052 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N190_1/LUT6_inst_perm/L6
                                   net (fanout=2)        0.442       8.494         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/_N41732
 CLMS_195_283/Y1                   td                    0.113       8.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N222_1/LUT6_inst_perm/L6
                                   net (fanout=9)        0.427       9.034         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N276
 CLMS_195_265/Y1                   td                    0.101       9.135 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N230_3/gateop_perm/L6
                                   net (fanout=3)        0.126       9.261         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N230
 CLMS_195_265/Y0                   td                    0.113       9.374 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N223_7_maj1/LUT6_inst_perm/L6
                                   net (fanout=2)        0.125       9.499         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/_N4386
 CLMS_195_265/Y2                   td                    0.235       9.734 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N223_7_ac3/LUT6_inst_perm/L6
                                   net (fanout=3)        0.442      10.176         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/_N4393
 CLMA_201_276/Y1                   td                    0.240      10.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N223_7_ac4/LUT6_inst_perm/L6
                                   net (fanout=1)        0.453      10.869         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/_N4397
 CLMS_195_277/Y3                   td                    0.078      10.947 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N223_7_sum6/LUT6_inst_perm/L6
                                   net (fanout=1)        0.411      11.358         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/nb5 [6]
 CLMA_195_282/C2                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_value[6]/opit_0_inv_L6Q_perm/I2

 Data arrival time                                                  11.358         Logic Levels: 9  
                                                                                   Logic: 1.652ns(29.793%), Route: 3.893ns(70.207%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.405      11.965         _N105            
 CLMA_195_282/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_value[6]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         1.392      13.357                          
 clock uncertainty                                      -0.150      13.207                          

 Setup time                                             -0.234      12.973                          

 Data required time                                                 12.973                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.973                          
 Data arrival time                                                  11.358                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.615                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/dll_90_bin[0]/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/wl_p_dll_bin[7]/opit_0_inv_L6Q_perm/I2
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.067  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.356
  Launch Clock Delay      :  5.815
  Clock Pessimism Removal :  1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.482       5.815         _N106            
 CLMA_219_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/dll_90_bin[0]/opit_0_inv/CLK

 CLMA_219_319/CR2                  tco                   0.261       6.076 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/dll_90_bin[0]/opit_0_inv/Q
                                   net (fanout=12)       0.719       6.795         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dll_90_bin [0]
 CLMA_219_306/COUT                 td                    0.401       7.196 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N255.fsub_4/gateop_perm/COUT
                                   net (fanout=1)        0.000       7.196         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N255.co [4]
 CLMA_219_312/Y2                   td                    0.157       7.353 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N255.fsub_7/gateop_perm/Y
                                   net (fanout=1)        0.597       7.950         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/wrcal_step_minus [6]
 CLMA_213_337/CR0                  td                    0.346       8.296 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[1]/opit_0_inv_L6Q_LUT6DQL5_perm/L5
                                   net (fanout=1)        0.727       9.023         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/_N15233
 CLMA_213_319/COUT                 td                    0.235       9.258 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N263_1_7/gateop_perm/COUT
                                   net (fanout=1)        0.000       9.258         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/_N7394
 CLMA_213_325/Y1                   td                    0.142       9.400 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N263_1_9/gateop_perm/Y
                                   net (fanout=1)        0.780      10.180         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N263 [8]
 CLMA_237_318/Y1                   td                    0.188      10.368 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N265_mux8/LUT6_inst_perm/L6
                                   net (fanout=1)        0.125      10.493         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N265
 CLMA_237_318/Y0                   td                    0.188      10.681 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N513_83/gateop_perm/L6
                                   net (fanout=8)        0.620      11.301         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/_N15268
 CLMS_267_331/D2                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/wl_p_dll_bin[7]/opit_0_inv_L6Q_perm/I2

 Data arrival time                                                  11.301         Logic Levels: 7  
                                                                                   Logic: 1.918ns(34.962%), Route: 3.568ns(65.038%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.415      11.975         _N106            
 CLMS_267_331/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/wl_p_dll_bin[7]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         1.392      13.367                          
 clock uncertainty                                      -0.150      13.217                          

 Setup time                                             -0.228      12.989                          

 Data required time                                                 12.989                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.989                          
 Data arrival time                                                  11.301                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.688                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dfi/mux_dfi_we_n[0]/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_L6Q_perm/I0
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.073  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.345
  Launch Clock Delay      :  5.810
  Clock Pessimism Removal :  1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.477       5.810         _N105            
 CLMS_237_235/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dfi/mux_dfi_we_n[0]/opit_0_inv/CLK

 CLMS_237_235/Q2                   tco                   0.213       6.023 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dfi/mux_dfi_we_n[0]/opit_0_inv/Q
                                   net (fanout=1)        0.739       6.762         I_ips_ddr_top/dfi_we_n [0]
 CLMA_243_216/Y2                   td                    0.235       6.997 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=3)        0.448       7.445         I_ips_ddr_top/u_ddrphy_top/read_cmd [0]
 CLMS_237_235/Y1                   td                    0.188       7.633 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/N230_1/LUT6_inst_perm/L6
                                   net (fanout=2)        0.609       8.242         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/N230
 CLMA_243_240/Y2                   td                    0.240       8.482 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_12[2]_1/gateop_perm/L6
                                   net (fanout=1)        0.616       9.098         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/_N13968
 CLMA_219_241/Y3                   td                    0.188       9.286 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_14[2]/LUT6_inst_perm/L6
                                   net (fanout=5)        0.414       9.700         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped [2]
 CLMA_219_235/Y1                   td                    0.240       9.940 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=1)        0.300      10.240         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src [3]
 CLMA_231_234/Y3                   td                    0.188      10.428 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[7]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.800      11.228         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/_N13905
 CLMA_219_253/C0                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_L6Q_perm/I0

 Data arrival time                                                  11.228         Logic Levels: 6  
                                                                                   Logic: 1.492ns(27.538%), Route: 3.926ns(72.462%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.404      11.964         _N105            
 CLMA_219_253/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         1.392      13.356                          
 clock uncertainty                                      -0.150      13.206                          

 Setup time                                             -0.286      12.920                          

 Data required time                                                 12.920                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.920                          
 Data arrival time                                                  11.228                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.692                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/opit_0_inv_32X2DL6QL5Q/DIH
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.073  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.800
  Launch Clock Delay      :  4.335
  Clock Pessimism Removal :  -1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.394       4.335         _N105            
 CLMA_201_216/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/CLK

 CLMA_201_216/CR1                  tco                   0.183       4.518 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/Q
                                   net (fanout=2)        0.273       4.791         I_ips_ddr_top/u_ips_ddrc_top/dcd_wr_addr [16]
 CLMS_195_217/BD                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/opit_0_inv_32X2DL6QL5Q/DIH

 Data arrival time                                                   4.791         Logic Levels: 0  
                                                                                   Logic: 0.183ns(40.132%), Route: 0.273ns(59.868%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.467       5.800         _N105            
 CLMS_195_217/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/opit_0_inv_32X2DL6QL5Q/CLK
 clock pessimism                                        -1.392       4.408                          
 clock uncertainty                                       0.000       4.408                          

 Hold time                                               0.240       4.648                          

 Data required time                                                  4.648                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.648                          
 Data arrival time                                                   4.791                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.143                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[17]/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[23]/opit_0_inv_32X2DL6QL5Q/DIL
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.069  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.801
  Launch Clock Delay      :  4.340
  Clock Pessimism Removal :  -1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.399       4.340         _N105            
 CLMA_201_240/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[17]/opit_0_inv/CLK

 CLMA_201_240/CR1                  tco                   0.183       4.523 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[17]/opit_0_inv/Q
                                   net (fanout=2)        0.273       4.796         I_ips_ddr_top/u_ips_ddrc_top/dcd_wr_addr [17]
 CLMS_195_223/M1                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[23]/opit_0_inv_32X2DL6QL5Q/DIL

 Data arrival time                                                   4.796         Logic Levels: 0  
                                                                                   Logic: 0.183ns(40.132%), Route: 0.273ns(59.868%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.468       5.801         _N105            
 CLMS_195_223/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[23]/opit_0_inv_32X2DL6QL5Q/CLK
 clock pessimism                                        -1.392       4.409                          
 clock uncertainty                                       0.000       4.409                          

 Hold time                                               0.240       4.649                          

 Data required time                                                  4.649                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.649                          
 Data arrival time                                                   4.796                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.147                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/DIH
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.027  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.794
  Launch Clock Delay      :  4.331
  Clock Pessimism Removal :  -1.436

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.390       4.331         _N105            
 CLMA_183_210/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK

 CLMA_183_210/Q1                   tco                   0.166       4.497 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/Q
                                   net (fanout=2)        0.250       4.747         I_ips_ddr_top/u_ips_ddrc_top/dcd_wr_addr [12]
 CLMS_177_205/BD                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/DIH

 Data arrival time                                                   4.747         Logic Levels: 0  
                                                                                   Logic: 0.166ns(39.904%), Route: 0.250ns(60.096%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.461       5.794         _N105            
 CLMS_177_205/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/CLK
 clock pessimism                                        -1.436       4.358                          
 clock uncertainty                                       0.000       4.358                          

 Hold time                                               0.240       4.598                          

 Data required time                                                  4.598                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.598                          
 Data arrival time                                                   4.747                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.149                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[6]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    1.257  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.345
  Launch Clock Delay      :  3.345
  Clock Pessimism Removal :  0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.227       5.249         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_396/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_396/RX_DATA[6]          tco                   0.449       5.698 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/RX_DATA[6]
                                   net (fanout=1)        0.527       6.225         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [6]
 CLMA_285_415/CR1                  td                    0.122       6.347 r       CLKROUTE_69/CR   
                                   net (fanout=1)        0.297       6.644         _N76             
 CLMA_285_408/CR2                  td                    0.120       6.764 r       CLKROUTE_70/CR   
                                   net (fanout=1)        2.828       9.592         _N77             
 CLMS_273_397/M0                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[6]/opit_0_inv_srl/D

 Data arrival time                                                   9.592         Logic Levels: 2  
                                                                                   Logic: 0.691ns(15.911%), Route: 3.652ns(84.089%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.404      11.964         _N106            
 CLMS_273_397/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[6]/opit_0_inv_srl/CLK
 clock pessimism                                         0.257      12.221                          
 clock uncertainty                                      -0.550      11.671                          

 Setup time                                             -0.143      11.528                          

 Data required time                                                 11.528                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.528                          
 Data arrival time                                                   9.592                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.936                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[44]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    1.264  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.352
  Launch Clock Delay      :  3.345
  Clock Pessimism Removal :  0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.227       5.249         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_360/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_360/RX_DATA[4]          tco                   0.449       5.698 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/RX_DATA[4]
                                   net (fanout=1)        3.689       9.387         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_rdata [44]
 CLMA_279_366/M2                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[44]/opit_0_inv_srl/D

 Data arrival time                                                   9.387         Logic Levels: 0  
                                                                                   Logic: 0.449ns(10.851%), Route: 3.689ns(89.149%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.411      11.971         _N106            
 CLMA_279_366/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[44]/opit_0_inv_srl/CLK
 clock pessimism                                         0.257      12.228                          
 clock uncertainty                                      -0.550      11.678                          

 Setup time                                             -0.143      11.535                          

 Data required time                                                 11.535                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.535                          
 Data arrival time                                                   9.387                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         2.148                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[57]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    1.264  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.352
  Launch Clock Delay      :  3.345
  Clock Pessimism Removal :  0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.227       5.249         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_450/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_450/RX_DATA[1]          tco                   0.449       5.698 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/RX_DATA[1]
                                   net (fanout=1)        0.534       6.232         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [57]
 CLMS_279_445/CR3                  td                    0.119       6.351 r       CLKROUTE_87/CR   
                                   net (fanout=1)        0.733       7.084         _N94             
 CLMA_273_432/CR1                  td                    0.122       7.206 r       CLKROUTE_88/CR   
                                   net (fanout=1)        2.006       9.212         _N95             
 CLMA_279_366/M3                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[57]/opit_0_inv_srl/D

 Data arrival time                                                   9.212         Logic Levels: 2  
                                                                                   Logic: 0.690ns(17.411%), Route: 3.273ns(82.589%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.411      11.971         _N106            
 CLMA_279_366/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[57]/opit_0_inv_srl/CLK
 clock pessimism                                         0.257      12.228                          
 clock uncertainty                                      -0.550      11.678                          

 Setup time                                             -0.034      11.644                          

 Data required time                                                 11.644                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.644                          
 Data arrival time                                                   9.212                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         2.432                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[19]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    2.719  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.828
  Launch Clock Delay      :  2.852
  Clock Pessimism Removal :  -0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    1.002      10.623 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.623         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      10.718 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      10.978         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      11.111 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      11.489         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      11.645 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      12.047         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      12.074 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      12.074         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      12.180 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.195      12.375         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_330/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_330/RX_DATA[3]          tco                   0.272      12.647 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/RX_DATA[3]
                                   net (fanout=1)        1.728      14.375         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_rdata [19]
 CLMS_279_289/M3                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[19]/opit_0_inv_srl/D

 Data arrival time                                                  14.375         Logic Levels: 0  
                                                                                   Logic: 0.272ns(13.600%), Route: 1.728ns(86.400%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.495      13.447         _N105            
 CLMS_279_289/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[19]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.257      13.190                          
 clock uncertainty                                       0.550      13.740                          

 Hold time                                               0.045      13.785                          

 Data required time                                                 13.785                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 13.785                          
 Data arrival time                                                  14.375                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.590                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[3].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[27]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    2.722  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.831
  Launch Clock Delay      :  2.852
  Clock Pessimism Removal :  -0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    1.002      10.623 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.623         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      10.718 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      10.978         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      11.111 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      11.489         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      11.645 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      12.047         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      12.074 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      12.074         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      12.180 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.195      12.375         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_336/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[3].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_336/RX_DATA[3]          tco                   0.272      12.647 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[3].u_iobuf_dq/opit_1/RX_DATA[3]
                                   net (fanout=1)        1.752      14.399         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_rdata [27]
 CLMA_285_300/M3                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[27]/opit_0_inv_srl/D

 Data arrival time                                                  14.399         Logic Levels: 0  
                                                                                   Logic: 0.272ns(13.439%), Route: 1.752ns(86.561%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.498      13.450         _N105            
 CLMA_285_300/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[27]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.257      13.193                          
 clock uncertainty                                       0.550      13.743                          

 Hold time                                               0.045      13.788                          

 Data required time                                                 13.788                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 13.788                          
 Data arrival time                                                  14.399                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.611                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[19]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    2.712  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.821
  Launch Clock Delay      :  2.852
  Clock Pessimism Removal :  -0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    1.002      10.623 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.623         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      10.718 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      10.978         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      11.111 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      11.489         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      11.645 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      12.047         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      12.074 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      12.074         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      12.180 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.195      12.375         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_408/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_408/RX_DATA[3]          tco                   0.272      12.647 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/RX_DATA[3]
                                   net (fanout=1)        1.745      14.392         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [19]
 CLMA_279_342/M3                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[19]/opit_0_inv_srl/D

 Data arrival time                                                  14.392         Logic Levels: 0  
                                                                                   Logic: 0.272ns(13.485%), Route: 1.745ns(86.515%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.488      13.440         _N106            
 CLMA_279_342/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[19]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.257      13.183                          
 clock uncertainty                                       0.550      13.733                          

 Hold time                                               0.045      13.778                          

 Data required time                                                 13.778                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 13.778                          
 Data arrival time                                                  14.392                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.614                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
Endpoint    : I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    1.687  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.344
  Launch Clock Delay      :  3.118
  Clock Pessimism Removal :  0.461

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       5.022         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 DDRPHY_CPD_297_4/PPLL_SYSCLK                                              r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY

 DDRPHY_CPD_297_4/CPD_UP_DNB       tco                   0.095       5.117 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/FLAG_PD
                                   net (fanout=2)        2.992       8.109         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_up_dnb
 CLMA_213_253/M2                                                           f       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D

 Data arrival time                                                   8.109         Logic Levels: 0  
                                                                                   Logic: 0.095ns(3.077%), Route: 2.992ns(96.923%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.403      11.963         _N105            
 CLMA_213_253/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                         0.461      12.424                          
 clock uncertainty                                      -0.550      11.874                          

 Setup time                                             -0.132      11.742                          

 Data required time                                                 11.742                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.742                          
 Data arrival time                                                   8.109                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.633                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
Endpoint    : I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    2.691  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.809
  Launch Clock Delay      :  2.657
  Clock Pessimism Removal :  -0.461

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    1.002      10.623 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.623         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      10.718 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      10.978         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      11.111 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      11.489         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156      11.645 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      12.047         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      12.074 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      12.074         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      12.180 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      12.180         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 DDRPHY_CPD_297_4/PPLL_SYSCLK                                              r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY

 DDRPHY_CPD_297_4/CPD_UP_DNB       tco                   0.078      12.258 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/FLAG_PD
                                   net (fanout=2)        2.141      14.399         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_up_dnb
 CLMA_213_253/M2                                                           f       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D

 Data arrival time                                                  14.399         Logic Levels: 0  
                                                                                   Logic: 0.078ns(3.515%), Route: 2.141ns(96.485%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.476      13.428         _N105            
 CLMA_213_253/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.461      12.967                          
 clock uncertainty                                       0.550      13.517                          

 Hold time                                              -0.047      13.470                          

 Data required time                                                 13.470                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 13.470                          
 Data arrival time                                                  14.399                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.929                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[7].u_outbuft_addr0/opit_1/TX_DATA[1]
Path Group  : phy_dq_sysclk_0
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.506  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.821
  Clock Pessimism Removal :  0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.488      13.440         _N105            
 CLMA_279_252/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_279_252/Q0                   tco                   0.213      13.653 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        1.169      14.822         debug_data[135]  
 CLMA_285_186/Y0                   td                    0.101      14.923 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       0.795      15.718         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_253/Y0                   td                    0.235      15.953 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_63:56_2[1]/LUT6D_inst_perm/L6
                                   net (fanout=2)        2.058      18.011         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [57]
 IOLHR_292_252/TX_DATA[1]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[7].u_outbuft_addr0/opit_1/TX_DATA[1]

 Data arrival time                                                  18.011         Logic Levels: 2  
                                                                                   Logic: 0.549ns(12.011%), Route: 4.022ns(87.989%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_252/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[7].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.461      20.457                          
 clock uncertainty                                      -0.550      19.907                          

 Setup time                                             -0.374      19.533                          

 Data required time                                                 19.533                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.533                          
 Data arrival time                                                  18.011                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.522                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/TX_DATA[5]
Path Group  : phy_dq_sysclk_0
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.506  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.821
  Clock Pessimism Removal :  0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.488      13.440         _N105            
 CLMA_279_252/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_279_252/Q0                   tco                   0.213      13.653 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        1.169      14.822         debug_data[135]  
 CLMA_285_186/Y0                   td                    0.101      14.923 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       1.116      16.039         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_258/CR2                  td                    0.349      16.388 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_39:32_2[2]/LUT6D_inst_perm/L5
                                   net (fanout=2)        1.483      17.871         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [37]
 IOLHR_292_270/TX_DATA[5]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/TX_DATA[5]

 Data arrival time                                                  17.871         Logic Levels: 2  
                                                                                   Logic: 0.663ns(14.963%), Route: 3.768ns(85.037%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_270/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.461      20.457                          
 clock uncertainty                                      -0.550      19.907                          

 Setup time                                             -0.374      19.533                          

 Data required time                                                 19.533                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.533                          
 Data arrival time                                                  17.871                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.662                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[3].u_outbuft_addr0/opit_1/TX_DATA[6]
Path Group  : phy_dq_sysclk_0
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.506  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.821
  Clock Pessimism Removal :  0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.488      13.440         _N105            
 CLMA_279_252/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_279_252/Q0                   tco                   0.213      13.653 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        1.169      14.822         debug_data[135]  
 CLMA_285_186/Y0                   td                    0.101      14.923 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       0.940      15.863         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_276/Y1                   td                    0.101      15.964 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_31:24_2[3]/LUT6D_inst_perm/L6
                                   net (fanout=2)        1.848      17.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [29]
 IOLHR_292_276/TX_DATA[6]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[3].u_outbuft_addr0/opit_1/TX_DATA[6]

 Data arrival time                                                  17.812         Logic Levels: 2  
                                                                                   Logic: 0.415ns(9.492%), Route: 3.957ns(90.508%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_276/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[3].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.461      20.457                          
 clock uncertainty                                      -0.550      19.907                          

 Setup time                                             -0.374      19.533                          

 Data required time                                                 19.533                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.533                          
 Data arrival time                                                  17.812                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.721                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[8].u_outbuft_addr0/opit_1/TX_DATA[5]
Path Group  : phy_dq_sysclk_0
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.465  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.353
  Clock Pessimism Removal :  -0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.412       4.353         _N105            
 CLMA_285_229/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_srl/CLK

 CLMA_285_229/Q1                   tco                   0.166       4.519 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_srl/Q0
                                   net (fanout=6)        0.247       4.766         I_ips_ddr_top/u_ddrphy_top/phy_addr [38]
 CLMA_285_241/CR2                  td                    0.170       4.936 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_71:64_2[2]/LUT6D_inst_perm/L5
                                   net (fanout=2)        0.839       5.775         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [69]
 IOLHR_292_246/TX_DATA[5]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[8].u_outbuft_addr0/opit_1/TX_DATA[5]

 Data arrival time                                                   5.775         Logic Levels: 1  
                                                                                   Logic: 0.336ns(23.629%), Route: 1.086ns(76.371%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_246/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[8].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                        -0.461       4.792                          
 clock uncertainty                                       0.550       5.342                          

 Hold time                                              -0.019       5.323                          

 Data required time                                                  5.323                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.323                          
 Data arrival time                                                   5.775                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.452                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[0].u_outbuft_ba/opit_1/TX_DATA[4]
Path Group  : phy_dq_sysclk_0
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.461  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.349
  Clock Pessimism Removal :  -0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.408       4.349         _N105            
 CLMA_261_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_261_235/Q2                   tco                   0.166       4.515 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=11)       0.826       5.341         I_ips_ddr_top/u_ddrphy_top/phy_ba [0]
 CLMA_285_198/Y1                   td                    0.082       5.423 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_ba_7:0_2[2]/LUT6D_inst_perm/L6
                                   net (fanout=2)        0.360       5.783         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_ba [3]
 IOLHR_292_192/TX_DATA[4]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[0].u_outbuft_ba/opit_1/TX_DATA[4]

 Data arrival time                                                   5.783         Logic Levels: 1  
                                                                                   Logic: 0.248ns(17.294%), Route: 1.186ns(82.706%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_192/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[0].u_outbuft_ba/opit_1/OCLKDIV
 clock pessimism                                        -0.461       4.792                          
 clock uncertainty                                       0.550       5.342                          

 Hold time                                              -0.019       5.323                          

 Data required time                                                  5.323                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.323                          
 Data arrival time                                                   5.783                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.460                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[10].u_outbuft_addr0/opit_1/TX_DATA[0]
Path Group  : phy_dq_sysclk_0
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.465  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.353
  Clock Pessimism Removal :  -0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.412       4.353         _N105            
 CLMA_285_229/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/opit_0_inv_srl/CLK

 CLMA_285_229/CR3                  tco                   0.181       4.534 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/opit_0_inv_srl/CR0
                                   net (fanout=1)        0.553       5.087         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r [42]
 CLMA_285_229/Y2                   td                    0.153       5.240 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_87:80_2[0]/LUT6D_inst_perm/L6
                                   net (fanout=1)        0.545       5.785         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [80]
 IOLHR_292_234/TX_DATA[0]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[10].u_outbuft_addr0/opit_1/TX_DATA[0]

 Data arrival time                                                   5.785         Logic Levels: 1  
                                                                                   Logic: 0.334ns(23.324%), Route: 1.098ns(76.676%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_234/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[10].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                        -0.461       4.792                          
 clock uncertainty                                       0.550       5.342                          

 Hold time                                              -0.019       5.323                          

 Data required time                                                  5.323                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.323                          
 Data arrival time                                                   5.785                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.462                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[5]
Path Group  : phy_dq_sysclk_1
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.703  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.814
  Clock Pessimism Removal :  0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.481      13.433         _N106            
 CLMA_285_390/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/CLK

 CLMA_285_390/CR0                  tco                   0.261      13.694 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/L6QQ
                                   net (fanout=12)       2.078      15.772         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r [3]
 CLMA_285_391/Y2                   td                    0.101      15.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/N28[5]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.667      16.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdq_en [5]
 CLMA_285_361/CR2                  td                    0.120      16.660 r       CLKROUTE_18/CR   
                                   net (fanout=2)        2.171      18.831         _N25             
 TSERDES_299_307/TS_CTRL[5]                                                r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[5]

 Data arrival time                                                  18.831         Logic Levels: 2  
                                                                                   Logic: 0.482ns(8.929%), Route: 4.916ns(91.071%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 TSERDES_299_307/OCLKDIV                                                   r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/OCLKDIV
 clock pessimism                                         0.257      20.253                          
 clock uncertainty                                      -0.550      19.703                          

 Setup time                                             -0.325      19.378                          

 Data required time                                                 19.378                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.378                          
 Data arrival time                                                  18.831                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.547                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[0]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[5]
Path Group  : phy_dq_sysclk_1
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.702  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.813
  Clock Pessimism Removal :  0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.480      13.432         _N106            
 CLMA_285_396/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[0]/opit_0_inv_L6QQ_perm/CLK

 CLMA_285_396/Q0                   tco                   0.213      13.645 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[0]/opit_0_inv_L6QQ_perm/L6Q
                                   net (fanout=12)       1.613      15.258         I_ips_ddr_top/u_ddrphy_top/phy_wrdata_en [0]
 CLMA_285_403/Y3                   td                    0.113      15.371 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/N28[5]/LUT6_inst_perm/L6
                                   net (fanout=2)        3.061      18.432         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdq_en [5]
 TSERDES_299_309/TS_CTRL[5]                                                r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[5]

 Data arrival time                                                  18.432         Logic Levels: 1  
                                                                                   Logic: 0.326ns(6.520%), Route: 4.674ns(93.480%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 TSERDES_299_309/OCLKDIV                                                   r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/OCLKDIV
 clock pessimism                                         0.257      20.253                          
 clock uncertainty                                      -0.550      19.703                          

 Setup time                                             -0.325      19.378                          

 Data required time                                                 19.378                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.378                          
 Data arrival time                                                  18.432                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.946                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[6]
Path Group  : phy_dq_sysclk_1
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.703  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.814
  Clock Pessimism Removal :  0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.481      13.433         _N106            
 CLMA_285_390/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/CLK

 CLMA_285_390/CR0                  tco                   0.261      13.694 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/L6QQ
                                   net (fanout=12)       2.078      15.772         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r [3]
 CLMA_285_391/Y2                   td                    0.101      15.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/N28[5]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.667      16.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdq_en [5]
 CLMA_285_361/CR2                  td                    0.120      16.660 r       CLKROUTE_18/CR   
                                   net (fanout=2)        1.581      18.241         _N25             
 TSERDES_299_307/TS_CTRL[6]                                                r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[6]

 Data arrival time                                                  18.241         Logic Levels: 2  
                                                                                   Logic: 0.482ns(10.025%), Route: 4.326ns(89.975%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 TSERDES_299_307/OCLKDIV                                                   r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/OCLKDIV
 clock pessimism                                         0.257      20.253                          
 clock uncertainty                                      -0.550      19.703                          

 Setup time                                             -0.325      19.378                          

 Data required time                                                 19.378                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.378                          
 Data arrival time                                                  18.241                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.137                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/genblk1.u_iobufco_dqs/opit_2/TX_DATA[0]
Path Group  : phy_dq_sysclk_1
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.247  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.339
  Clock Pessimism Removal :  -0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.398       4.339         _N106            
 CLMA_231_390/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK

 CLMA_231_390/CR0                  tco                   0.182       4.521 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/L5Q
                                   net (fanout=15)       0.415       4.936         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/wrlvl_dqs_en
 CLMA_231_409/Y3                   td                    0.075       5.011 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/N662[0]/gateop_LUT6DL5_perm/L6
                                   net (fanout=1)        0.973       5.984         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdqs [0]
 IOLHR_292_426/TX_DATA[0]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/genblk1.u_iobufco_dqs/opit_2/TX_DATA[0]

 Data arrival time                                                   5.984         Logic Levels: 1  
                                                                                   Logic: 0.257ns(15.623%), Route: 1.388ns(84.377%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_426/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/genblk1.u_iobufco_dqs/opit_2/OCLKDIV
 clock pessimism                                        -0.257       4.996                          
 clock uncertainty                                       0.550       5.546                          

 Hold time                                              -0.019       5.527                          

 Data required time                                                  5.527                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.527                          
 Data arrival time                                                   5.984                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.457                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[0]
Path Group  : phy_dq_sysclk_1
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.255  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.347
  Clock Pessimism Removal :  -0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.406       4.347         _N106            
 CLMA_285_396/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv_L6QQ_perm/CLK

 CLMA_285_396/CR1                  tco                   0.183       4.530 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv_L6QQ_perm/L6QQ
                                   net (fanout=6)        0.153       4.683         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r [1]
 CLMA_285_397/Y2                   td                    0.075       4.758 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/N28[0]/LUT6_inst_perm/L6
                                   net (fanout=1)        1.261       6.019         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdq_en [0]
 TSERDES_299_307/TS_CTRL[0]                                                f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[0]

 Data arrival time                                                   6.019         Logic Levels: 1  
                                                                                   Logic: 0.258ns(15.431%), Route: 1.414ns(84.569%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 TSERDES_299_307/OCLKDIV                                                   r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/OCLKDIV
 clock pessimism                                        -0.257       4.996                          
 clock uncertainty                                       0.550       5.546                          

 Hold time                                              -0.009       5.537                          

 Data required time                                                  5.537                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.537                          
 Data arrival time                                                   6.019                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.482                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[51]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[6].u_iobuf_dq/opit_1/TX_DATA[6]
Path Group  : phy_dq_sysclk_1
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.247  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.339
  Clock Pessimism Removal :  -0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.398       4.339         _N106            
 CLMA_273_432/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[51]/opit_0_inv_L6QQ_perm/CLK

 CLMA_273_432/Q2                   tco                   0.166       4.505 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[51]/opit_0_inv_L6QQ_perm/L6Q
                                   net (fanout=4)        0.152       4.657         I_ips_ddr_top/u_ddrphy_top/phy_wrdata [54]
 CLMS_273_433/Y1                   td                    0.150       4.807 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[66]/LUT6_inst_perm/L6
                                   net (fanout=1)        1.209       6.016         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdq [54]
 IOLHR_292_366/TX_DATA[6]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[6].u_iobuf_dq/opit_1/TX_DATA[6]

 Data arrival time                                                   6.016         Logic Levels: 1  
                                                                                   Logic: 0.316ns(18.843%), Route: 1.361ns(81.157%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_366/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[6].u_iobuf_dq/opit_1/OCLKDIV
 clock pessimism                                        -0.257       4.996                          
 clock uncertainty                                       0.550       5.546                          

 Hold time                                              -0.019       5.527                          

 Data required time                                                  5.527                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.527                          
 Data arrival time                                                   6.016                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.489                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[10]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.229  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.329
  Launch Clock Delay      :  3.908
  Clock Pessimism Removal :  0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.477       3.908         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.212       4.120 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.728       4.848         free_clk_rst_n   
 CLMA_177_336/RSCO                 td                    0.098       4.946 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       4.946         ntR298           
 CLMA_177_342/RSCO                 td                    0.079       5.025 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.025         ntR297           
 CLMA_177_348/RSCO                 td                    0.079       5.104 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[31]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=5)        0.000       5.104         ntR296           
 CLMA_177_354/RSCO                 td                    0.079       5.183 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[31]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       5.183         ntR295           
 CLMA_177_360/RSCO                 td                    0.079       5.262 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_7[23]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.262         ntR294           
 CLMA_177_366/RSCO                 td                    0.079       5.341 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[15]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       5.341         ntR293           
 CLMA_177_372/RSCO                 td                    0.079       5.420 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[15]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.420         ntR292           
 CLMA_177_378/RSCO                 td                    0.079       5.499 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[27]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=3)        0.000       5.499         ntR291           
 CLMA_177_384/RSCO                 td                    0.079       5.578 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[28]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.578         ntR290           
 CLMA_177_390/RSCO                 td                    0.079       5.657 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_2[28]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       5.657         ntR289           
 CLMA_177_396/RSCO                 td                    0.079       5.736 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[28]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.736         ntR288           
 CLMA_177_402/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[10]/opit_0_inv/RS

 Data arrival time                                                   5.736         Logic Levels: 11 
                                                                                   Logic: 1.100ns(60.175%), Route: 0.728ns(39.825%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.386      43.329         _N111            
 CLMA_177_402/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[10]/opit_0_inv/CLK
 clock pessimism                                         0.350      43.679                          
 clock uncertainty                                      -0.050      43.629                          

 Recovery time                                          -0.238      43.391                          

 Data required time                                                 43.391                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.391                          
 Data arrival time                                                   5.736                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.655                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[26]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.229  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.329
  Launch Clock Delay      :  3.908
  Clock Pessimism Removal :  0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.477       3.908         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.212       4.120 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.728       4.848         free_clk_rst_n   
 CLMA_177_336/RSCO                 td                    0.098       4.946 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       4.946         ntR298           
 CLMA_177_342/RSCO                 td                    0.079       5.025 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.025         ntR297           
 CLMA_177_348/RSCO                 td                    0.079       5.104 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[31]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=5)        0.000       5.104         ntR296           
 CLMA_177_354/RSCO                 td                    0.079       5.183 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[31]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       5.183         ntR295           
 CLMA_177_360/RSCO                 td                    0.079       5.262 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_7[23]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.262         ntR294           
 CLMA_177_366/RSCO                 td                    0.079       5.341 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[15]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       5.341         ntR293           
 CLMA_177_372/RSCO                 td                    0.079       5.420 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[15]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.420         ntR292           
 CLMA_177_378/RSCO                 td                    0.079       5.499 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[27]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=3)        0.000       5.499         ntR291           
 CLMA_177_384/RSCO                 td                    0.079       5.578 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[28]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.578         ntR290           
 CLMA_177_390/RSCO                 td                    0.079       5.657 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_2[28]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       5.657         ntR289           
 CLMA_177_396/RSCO                 td                    0.079       5.736 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[28]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.736         ntR288           
 CLMA_177_402/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[26]/opit_0_inv/RS

 Data arrival time                                                   5.736         Logic Levels: 11 
                                                                                   Logic: 1.100ns(60.175%), Route: 0.728ns(39.825%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.386      43.329         _N111            
 CLMA_177_402/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[26]/opit_0_inv/CLK
 clock pessimism                                         0.350      43.679                          
 clock uncertainty                                      -0.050      43.629                          

 Recovery time                                          -0.238      43.391                          

 Data required time                                                 43.391                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.391                          
 Data arrival time                                                   5.736                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.655                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[28]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.229  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.329
  Launch Clock Delay      :  3.908
  Clock Pessimism Removal :  0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.477       3.908         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.212       4.120 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.728       4.848         free_clk_rst_n   
 CLMA_177_336/RSCO                 td                    0.098       4.946 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       4.946         ntR298           
 CLMA_177_342/RSCO                 td                    0.079       5.025 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.025         ntR297           
 CLMA_177_348/RSCO                 td                    0.079       5.104 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[31]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=5)        0.000       5.104         ntR296           
 CLMA_177_354/RSCO                 td                    0.079       5.183 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[31]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       5.183         ntR295           
 CLMA_177_360/RSCO                 td                    0.079       5.262 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_7[23]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.262         ntR294           
 CLMA_177_366/RSCO                 td                    0.079       5.341 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[15]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       5.341         ntR293           
 CLMA_177_372/RSCO                 td                    0.079       5.420 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[15]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.420         ntR292           
 CLMA_177_378/RSCO                 td                    0.079       5.499 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[27]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=3)        0.000       5.499         ntR291           
 CLMA_177_384/RSCO                 td                    0.079       5.578 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[28]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.578         ntR290           
 CLMA_177_390/RSCO                 td                    0.079       5.657 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_2[28]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       5.657         ntR289           
 CLMA_177_396/RSCO                 td                    0.079       5.736 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[28]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.736         ntR288           
 CLMA_177_402/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[28]/opit_0_inv/RS

 Data arrival time                                                   5.736         Logic Levels: 11 
                                                                                   Logic: 1.100ns(60.175%), Route: 0.728ns(39.825%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.386      43.329         _N111            
 CLMA_177_402/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[28]/opit_0_inv/CLK
 clock pessimism                                         0.350      43.679                          
 clock uncertainty                                      -0.050      43.629                          

 Recovery time                                          -0.238      43.391                          

 Data required time                                                 43.391                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.391                          
 Data arrival time                                                   5.736                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.655                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[4]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.208  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.905
  Launch Clock Delay      :  3.347
  Clock Pessimism Removal :  -0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.404       3.347         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.182       3.529 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.324       3.853         free_clk_rst_n   
 CLMS_177_319/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[4]/opit_0_inv/RS

 Data arrival time                                                   3.853         Logic Levels: 0  
                                                                                   Logic: 0.182ns(35.968%), Route: 0.324ns(64.032%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.474       3.905         _N111            
 CLMS_177_319/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[4]/opit_0_inv/CLK
 clock pessimism                                        -0.350       3.555                          
 clock uncertainty                                       0.000       3.555                          

 Removal time                                           -0.061       3.494                          

 Data required time                                                  3.494                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.494                          
 Data arrival time                                                   3.853                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.359                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[7]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.208  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.905
  Launch Clock Delay      :  3.347
  Clock Pessimism Removal :  -0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.404       3.347         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.182       3.529 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.324       3.853         free_clk_rst_n   
 CLMS_177_319/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[7]/opit_0_inv/RS

 Data arrival time                                                   3.853         Logic Levels: 0  
                                                                                   Logic: 0.182ns(35.968%), Route: 0.324ns(64.032%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.474       3.905         _N111            
 CLMS_177_319/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[7]/opit_0_inv/CLK
 clock pessimism                                        -0.350       3.555                          
 clock uncertainty                                       0.000       3.555                          

 Removal time                                           -0.061       3.494                          

 Data required time                                                  3.494                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.494                          
 Data arrival time                                                   3.853                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.359                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[16]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.028  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.907
  Launch Clock Delay      :  3.347
  Clock Pessimism Removal :  -0.532

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.404       3.347         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.182       3.529 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.152       3.681         free_clk_rst_n   
 CLMA_147_318/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[16]/opit_0_inv/RS

 Data arrival time                                                   3.681         Logic Levels: 0  
                                                                                   Logic: 0.182ns(54.491%), Route: 0.152ns(45.509%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.476       3.907         _N109            
 CLMA_147_318/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[16]/opit_0_inv/CLK
 clock pessimism                                        -0.532       3.375                          
 clock uncertainty                                       0.000       3.375                          

 Removal time                                           -0.061       3.314                          

 Data required time                                                  3.314                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.314                          
 Data arrival time                                                   3.681                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.367                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/RS
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.209  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.665
  Launch Clock Delay      :  5.506
  Clock Pessimism Removal :  0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.473       5.506         _N114            
 CLMA_213_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_213_235/CR0                  tco                   0.212       5.718 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=40)       1.472       7.190         I_ips_ddr_top/u_ddrphy_top/rst_seq_rstn
 CLMA_147_319/RSCO                 td                    0.098       7.288 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=1)        0.000       7.288         ntR543           
 CLMA_147_325/RSCI                                                         r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/RS

 Data arrival time                                                   7.288         Logic Levels: 1  
                                                                                   Logic: 0.310ns(17.396%), Route: 1.472ns(82.604%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.402      44.665         _N116            
 CLMA_147_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.632      45.297                          
 clock uncertainty                                      -0.150      45.147                          

 Recovery time                                          -0.238      44.909                          

 Data required time                                                 44.909                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.909                          
 Data arrival time                                                   7.288                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.621                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.208  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.666
  Launch Clock Delay      :  5.506
  Clock Pessimism Removal :  0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.473       5.506         _N114            
 CLMA_213_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_213_235/CR0                  tco                   0.261       5.767 r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=40)       1.517       7.284         I_ips_ddr_top/u_ddrphy_top/rst_seq_rstn
 CLMA_147_319/RS                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   7.284         Logic Levels: 0  
                                                                                   Logic: 0.261ns(14.679%), Route: 1.517ns(85.321%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.403      44.666         _N116            
 CLMA_147_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                         0.632      45.298                          
 clock uncertainty                                      -0.150      45.148                          

 Recovery time                                          -0.238      44.910                          

 Data required time                                                 44.910                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.910                          
 Data arrival time                                                   7.284                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.626                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.208  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.666
  Launch Clock Delay      :  5.506
  Clock Pessimism Removal :  0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.473       5.506         _N114            
 CLMA_213_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_213_235/CR0                  tco                   0.261       5.767 r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=40)       1.517       7.284         I_ips_ddr_top/u_ddrphy_top/rst_seq_rstn
 CLMA_147_319/RS                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   7.284         Logic Levels: 0  
                                                                                   Logic: 0.261ns(14.679%), Route: 1.517ns(85.321%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.403      44.666         _N116            
 CLMA_147_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                         0.632      45.298                          
 clock uncertainty                                      -0.150      45.148                          

 Recovery time                                          -0.238      44.910                          

 Data required time                                                 44.910                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.910                          
 Data arrival time                                                   7.284                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.626                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[3]/opit_0_inv_L6Q_perm/RS
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.028  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.506
  Launch Clock Delay      :  4.664
  Clock Pessimism Removal :  -0.814

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.401       4.664         _N116            
 CLMS_159_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_319/CR0                  tco                   0.182       4.846 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=61)       0.154       5.000         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMS_159_325/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[3]/opit_0_inv_L6Q_perm/RS

 Data arrival time                                                   5.000         Logic Levels: 0  
                                                                                   Logic: 0.182ns(54.167%), Route: 0.154ns(45.833%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.473       5.506         _N116            
 CLMS_159_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[3]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                        -0.814       4.692                          
 clock uncertainty                                       0.000       4.692                          

 Removal time                                           -0.061       4.631                          

 Data required time                                                  4.631                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.631                          
 Data arrival time                                                   5.000                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.369                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[6]/opit_0_inv_L6Q_perm/RS
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.028  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.506
  Launch Clock Delay      :  4.664
  Clock Pessimism Removal :  -0.814

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.401       4.664         _N116            
 CLMS_159_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_319/CR0                  tco                   0.182       4.846 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=61)       0.154       5.000         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMS_159_325/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[6]/opit_0_inv_L6Q_perm/RS

 Data arrival time                                                   5.000         Logic Levels: 0  
                                                                                   Logic: 0.182ns(54.167%), Route: 0.154ns(45.833%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.473       5.506         _N116            
 CLMS_159_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[6]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                        -0.814       4.692                          
 clock uncertainty                                       0.000       4.692                          

 Removal time                                           -0.061       4.631                          

 Data required time                                                  4.631                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.631                          
 Data arrival time                                                   5.000                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.369                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/delay_cnt[0]/opit_0_inv_L5Q_perm/RS
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.028  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.506
  Launch Clock Delay      :  4.664
  Clock Pessimism Removal :  -0.814

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N117            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.401       4.664         _N116            
 CLMS_159_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_319/CR0                  tco                   0.182       4.846 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=61)       0.154       5.000         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_159_324/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/delay_cnt[0]/opit_0_inv_L5Q_perm/RS

 Data arrival time                                                   5.000         Logic Levels: 0  
                                                                                   Logic: 0.182ns(54.167%), Route: 0.154ns(45.833%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N117            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.473       5.506         _N116            
 CLMA_159_324/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/delay_cnt[0]/opit_0_inv_L5Q_perm/CLK
 clock pessimism                                        -0.814       4.692                          
 clock uncertainty                                       0.000       4.692                          

 Removal time                                           -0.061       4.631                          

 Data required time                                                  4.631                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.631                          
 Data arrival time                                                   5.000                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.369                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.071  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.343
  Launch Clock Delay      :  5.806
  Clock Pessimism Removal :  1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.473       5.806         _N105            
 CLMA_243_205/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_243_205/CR0                  tco                   0.212       6.018 f       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=437)      0.974       6.992         I_ips_ddr_top/ddrc_rstn
 CLMS_177_193/RSCO                 td                    0.098       7.090 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[1]/opit_0_inv_32X2DL6Q/RSCO
                                   net (fanout=1)        0.000       7.090         ntR359           
 CLMS_177_199/RSCO                 td                    0.079       7.169 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[1]/opit_0_inv_32X2DL6Q/RSCO
                                   net (fanout=2)        0.000       7.169         ntR358           
 CLMS_177_205/RSCO                 td                    0.079       7.248 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       7.248         ntR357           
 CLMS_177_211/RSCO                 td                    0.079       7.327 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[17]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       7.327         ntR356           
 CLMS_177_217/RSCO                 td                    0.079       7.406 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[15]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       7.406         ntR355           
 CLMS_177_223/RSCO                 td                    0.079       7.485 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[25]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=1)        0.000       7.485         ntR354           
 CLMS_177_229/RSCO                 td                    0.079       7.564 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[25]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=1)        0.000       7.564         ntR353           
 CLMS_177_235/RSCO                 td                    0.079       7.643 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=2)        0.000       7.643         ntR352           
 CLMS_177_241/RSCO                 td                    0.079       7.722 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][2]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       7.722         ntR351           
 CLMS_177_247/RSCO                 td                    0.079       7.801 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L6QL5Q_perm/RSCO
                                   net (fanout=3)        0.000       7.801         ntR350           
 CLMS_177_253/RSCO                 td                    0.079       7.880 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][14]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       7.880         ntR349           
 CLMS_177_259/RSCO                 td                    0.079       7.959 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][14]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       7.959         ntR348           
 CLMS_177_265/RSCO                 td                    0.079       8.038 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][13]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       8.038         ntR347           
 CLMS_177_271/RSCO                 td                    0.079       8.117 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][14]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       8.117         ntR346           
 CLMS_177_277/RSCO                 td                    0.079       8.196 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=2)        0.000       8.196         ntR345           
 CLMS_177_283/RSCI                                                         r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   8.196         Logic Levels: 15 
                                                                                   Logic: 1.416ns(59.247%), Route: 0.974ns(40.753%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.402      11.962         _N105            
 CLMS_177_283/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                         1.392      13.354                          
 clock uncertainty                                      -0.150      13.204                          

 Recovery time                                          -0.238      12.966                          

 Data required time                                                 12.966                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.966                          
 Data arrival time                                                   8.196                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.770                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.071  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.343
  Launch Clock Delay      :  5.806
  Clock Pessimism Removal :  1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.473       5.806         _N105            
 CLMA_243_205/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_243_205/CR0                  tco                   0.212       6.018 f       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=437)      0.974       6.992         I_ips_ddr_top/ddrc_rstn
 CLMS_177_193/RSCO                 td                    0.098       7.090 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[1]/opit_0_inv_32X2DL6Q/RSCO
                                   net (fanout=1)        0.000       7.090         ntR359           
 CLMS_177_199/RSCO                 td                    0.079       7.169 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[1]/opit_0_inv_32X2DL6Q/RSCO
                                   net (fanout=2)        0.000       7.169         ntR358           
 CLMS_177_205/RSCO                 td                    0.079       7.248 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       7.248         ntR357           
 CLMS_177_211/RSCO                 td                    0.079       7.327 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[17]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       7.327         ntR356           
 CLMS_177_217/RSCO                 td                    0.079       7.406 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[15]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       7.406         ntR355           
 CLMS_177_223/RSCO                 td                    0.079       7.485 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[25]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=1)        0.000       7.485         ntR354           
 CLMS_177_229/RSCO                 td                    0.079       7.564 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[25]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=1)        0.000       7.564         ntR353           
 CLMS_177_235/RSCO                 td                    0.079       7.643 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=2)        0.000       7.643         ntR352           
 CLMS_177_241/RSCO                 td                    0.079       7.722 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][2]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       7.722         ntR351           
 CLMS_177_247/RSCO                 td                    0.079       7.801 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L6QL5Q_perm/RSCO
                                   net (fanout=3)        0.000       7.801         ntR350           
 CLMS_177_253/RSCO                 td                    0.079       7.880 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][14]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       7.880         ntR349           
 CLMS_177_259/RSCO                 td                    0.079       7.959 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][14]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       7.959         ntR348           
 CLMS_177_265/RSCO                 td                    0.079       8.038 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][13]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       8.038         ntR347           
 CLMS_177_271/RSCO                 td                    0.079       8.117 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][14]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       8.117         ntR346           
 CLMS_177_277/RSCO                 td                    0.079       8.196 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=2)        0.000       8.196         ntR345           
 CLMS_177_283/RSCI                                                         r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm/RS

 Data arrival time                                                   8.196         Logic Levels: 15 
                                                                                   Logic: 1.416ns(59.247%), Route: 0.974ns(40.753%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.402      11.962         _N105            
 CLMS_177_283/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm/CLK
 clock pessimism                                         1.392      13.354                          
 clock uncertainty                                      -0.150      13.204                          

 Recovery time                                          -0.238      12.966                          

 Data required time                                                 12.966                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.966                          
 Data arrival time                                                   8.196                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.770                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.071  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.343
  Launch Clock Delay      :  5.806
  Clock Pessimism Removal :  1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.473       5.806         _N105            
 CLMA_243_205/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_243_205/CR0                  tco                   0.212       6.018 f       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=437)      0.949       6.967         I_ips_ddr_top/ddrc_rstn
 CLMA_171_199/RSCO                 td                    0.098       7.065 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=1)        0.000       7.065         ntR217           
 CLMA_171_205/RSCO                 td                    0.079       7.144 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=7)        0.000       7.144         ntR216           
 CLMA_171_211/RSCO                 td                    0.079       7.223 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/poll/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=2)        0.000       7.223         ntR215           
 CLMA_171_217/RSCO                 td                    0.079       7.302 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[37]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       7.302         ntR214           
 CLMA_171_223/RSCO                 td                    0.079       7.381 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[3]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=1)        0.000       7.381         ntR213           
 CLMA_171_229/RSCO                 td                    0.079       7.460 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[6]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=7)        0.000       7.460         ntR212           
 CLMA_171_235/RSCO                 td                    0.079       7.539 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[45]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       7.539         ntR211           
 CLMA_171_241/RSCO                 td                    0.079       7.618 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][5]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       7.618         ntR210           
 CLMA_171_247/RSCO                 td                    0.079       7.697 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][5]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       7.697         ntR209           
 CLMA_171_253/RSCO                 td                    0.079       7.776 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][5]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       7.776         ntR208           
 CLMA_171_259/RSCO                 td                    0.079       7.855 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][6]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       7.855         ntR207           
 CLMA_171_265/RSCO                 td                    0.079       7.934 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][14]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       7.934         ntR206           
 CLMA_171_271/RSCO                 td                    0.079       8.013 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][13]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       8.013         ntR205           
 CLMA_171_277/RSCO                 td                    0.079       8.092 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[19]/opit_0_inv_L6QL5Q_perm/RSCO
                                   net (fanout=4)        0.000       8.092         ntR204           
 CLMA_171_283/RSCO                 td                    0.079       8.171 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[35]/opit_0_inv_L6Q_LUT6DL5Q_perm/RSCO
                                   net (fanout=4)        0.000       8.171         ntR203           
 CLMA_171_289/RSCI                                                         r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   8.171         Logic Levels: 15 
                                                                                   Logic: 1.416ns(59.873%), Route: 0.949ns(40.127%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.402      11.962         _N105            
 CLMA_171_289/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                         1.392      13.354                          
 clock uncertainty                                      -0.150      13.204                          

 Recovery time                                          -0.238      12.966                          

 Data required time                                                 12.966                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.966                          
 Data arrival time                                                   8.171                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.795                          
====================================================================================================

====================================================================================================

Startpoint  : u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK
Endpoint    : u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[25]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.213  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.810
  Launch Clock Delay      :  4.343
  Clock Pessimism Removal :  -1.254

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.402       4.343         _N106            
 CLMA_171_307/CLK                                                          r       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK

 CLMA_171_307/CR0                  tco                   0.182       4.525 f       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/L6QQ
                                   net (fanout=512)      0.245       4.770         core_clk_rst_n   
 CLMA_171_300/RS                                                           f       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[25]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   4.770         Logic Levels: 0  
                                                                                   Logic: 0.182ns(42.623%), Route: 0.245ns(57.377%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.477       5.810         _N105            
 CLMA_171_300/CLK                                                          r       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[25]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                        -1.254       4.556                          
 clock uncertainty                                       0.000       4.556                          

 Removal time                                           -0.061       4.495                          

 Data required time                                                  4.495                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.495                          
 Data arrival time                                                   4.770                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.275                          
====================================================================================================

====================================================================================================

Startpoint  : u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK
Endpoint    : u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[104]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.213  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.810
  Launch Clock Delay      :  4.343
  Clock Pessimism Removal :  -1.254

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.402       4.343         _N106            
 CLMA_171_307/CLK                                                          r       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK

 CLMA_171_307/CR0                  tco                   0.182       4.525 f       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/L6QQ
                                   net (fanout=512)      0.245       4.770         core_clk_rst_n   
 CLMA_171_300/RS                                                           f       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[104]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   4.770         Logic Levels: 0  
                                                                                   Logic: 0.182ns(42.623%), Route: 0.245ns(57.377%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.477       5.810         _N105            
 CLMA_171_300/CLK                                                          r       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[104]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                        -1.254       4.556                          
 clock uncertainty                                       0.000       4.556                          

 Removal time                                           -0.061       4.495                          

 Data required time                                                  4.495                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.495                          
 Data arrival time                                                   4.770                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.275                          
====================================================================================================

====================================================================================================

Startpoint  : u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK
Endpoint    : u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[105]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.213  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.810
  Launch Clock Delay      :  4.343
  Clock Pessimism Removal :  -1.254

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.402       4.343         _N106            
 CLMA_171_307/CLK                                                          r       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK

 CLMA_171_307/CR0                  tco                   0.182       4.525 f       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/L6QQ
                                   net (fanout=512)      0.245       4.770         core_clk_rst_n   
 CLMA_171_300/RS                                                           f       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[105]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   4.770         Logic Levels: 0  
                                                                                   Logic: 0.182ns(42.623%), Route: 0.245ns(57.377%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.477       5.810         _N105            
 CLMA_171_300/CLK                                                          r       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[105]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                        -1.254       4.556                          
 clock uncertainty                                       0.000       4.556                          

 Removal time                                           -0.061       4.495                          

 Data required time                                                  4.495                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.495                          
 Data arrival time                                                   4.770                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.275                          
====================================================================================================

====================================================================================================

Startpoint  : u_axi_bist_top/u_test_rd_ctrl/err_flag_led/opit_0_inv_L5Q_perm/CLK
Endpoint    : err_flag_led (port)
Path Group  : **default**
Path Type   : max (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.494       5.827         _N105            
 CLMA_261_301/CLK                                                          r       u_axi_bist_top/u_test_rd_ctrl/err_flag_led/opit_0_inv_L5Q_perm/CLK

 CLMA_261_301/CR3                  tco                   0.260       6.087 r       u_axi_bist_top/u_test_rd_ctrl/err_flag_led/opit_0_inv_L5Q_perm/L5Q
                                   net (fanout=36)       1.230       7.317         err_flag         
 CLMS_159_289/CR3                  td                    0.297       7.614 r       u_axi_bist_top/u_test_rd_ctrl/execute_rd_cnt[0]/opit_0_inv_L6Q_LUT6DQL5_perm/L5
                                   net (fanout=1)        2.535      10.149         nt_err_flag_led  
 IOLHR_16_606/DO_P                 td                    0.641      10.790 r       err_flag_led_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000      10.790         err_flag_led_obuf/ntO
 IOBS_0_606/PAD                    td                    1.288      12.078 r       err_flag_led_obuf/opit_0/O
                                   net (fanout=1)        0.039      12.117         err_flag_led     
 J16                                                                       r       err_flag_led (port)

 Data arrival time                                                  12.117         Logic Levels: 3  
                                                                                   Logic: 2.486ns(39.523%), Route: 3.804ns(60.477%)
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/CLK
Endpoint    : mem_rst_n (port)
Path Group  : **default**
Path Type   : max (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_160/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_2/CLKOUT
                                   net (fanout=246)      0.472       5.805         _N107            
 CLMA_147_252/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/CLK

 CLMA_147_252/CR3                  tco                   0.260       6.065 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/L6QQ
                                   net (fanout=1)        1.502       7.567         I_ips_ddr_top/u_ddrphy_top/calib_rst
 CLMA_285_289/Y0                   td                    0.235       7.802 r       u_axi_bist_top/u_test_rd_ctrl/axi_rdata_d1[0]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=1)        0.463       8.265         nt_mem_rst_n     
 IOLHR_292_300/DO_P                td                    0.641       8.906 r       mem_rst_n_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000       8.906         mem_rst_n_obuf/ntO
 IOBS_300_300/PAD                  td                    0.850       9.756 r       mem_rst_n_obuf/opit_0/O
                                   net (fanout=1)        0.092       9.848         mem_rst_n        
 T3                                                                        r       mem_rst_n (port) 

 Data arrival time                                                   9.848         Logic Levels: 3  
                                                                                   Logic: 1.986ns(49.122%), Route: 2.057ns(50.878%)
====================================================================================================

====================================================================================================

Startpoint  : heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/CLK
Endpoint    : heart_beat_led (port)
Path Group  : **default**
Path Type   : max (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.473       5.806         _N105            
 CLMA_201_246/CLK                                                          r       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/CLK

 CLMA_201_246/Q0                   tco                   0.213       6.019 r       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/L6Q
                                   net (fanout=3)        1.725       7.744         nt_heart_beat_led
 IOLHR_16_306/DO_P                 td                    0.641       8.385 r       heart_beat_led_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000       8.385         heart_beat_led_obuf/ntO
 IOBS_0_306/PAD                    td                    1.288       9.673 r       heart_beat_led_obuf/opit_0/O
                                   net (fanout=1)        0.053       9.726         heart_beat_led   
 M17                                                                       r       heart_beat_led (port)

 Data arrival time                                                   9.726         Logic Levels: 2  
                                                                                   Logic: 2.142ns(54.643%), Route: 1.778ns(45.357%)
====================================================================================================

====================================================================================================

Startpoint  : uart_rxd (port)
Endpoint    : u_ips2l_uart_ctrl/u_uart_top/u_ips2l_seu_uart_rx/rxd_d[0]/opit_0_inv_srl/D
Path Group  : **default**
Path Type   : min (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 M16                                                     0.000       0.000 f       uart_rxd (port)  
                                   net (fanout=1)        0.052       0.052         uart_rxd         
 IOBS_0_312/DIN                    td                    0.678       0.730 f       uart_rxd_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.730         uart_rxd_ibuf/ntD
 IOLHR_16_312/DI_TO_CLK            td                    0.095       0.825 f       uart_rxd_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=1)        0.937       1.762         nt_uart_rxd      
 CLMA_147_337/M3                                                           f       u_ips2l_uart_ctrl/u_uart_top/u_ips2l_seu_uart_rx/rxd_d[0]/opit_0_inv_srl/D

 Data arrival time                                                   1.762         Logic Levels: 2  
                                                                                   Logic: 0.773ns(43.871%), Route: 0.989ns(56.129%)
====================================================================================================

====================================================================================================

Startpoint  : rst_board (port)
Endpoint    : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/RS
Path Group  : **default**
Path Type   : min (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 M15                                                     0.000       0.000 f       rst_board (port) 
                                   net (fanout=1)        0.052       0.052         rst_board        
 IOBD_0_318/DIN                    td                    0.815       0.867 f       rst_board_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.867         rst_board_ibuf/ntD
 IOLHR_16_318/DI_TO_CLK            td                    0.095       0.962 f       rst_board_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=2)        0.819       1.781         nt_rst_board     
 CLMA_147_312/RS                                                           f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/RS

 Data arrival time                                                   1.781         Logic Levels: 2  
                                                                                   Logic: 0.910ns(51.095%), Route: 0.871ns(48.905%)
====================================================================================================

====================================================================================================

Startpoint  : mem_dq[5] (port)
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L6Q_perm/I2
Path Group  : **default**
Path Type   : min (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 P1                                                      0.000       0.000 f       mem_dq[5] (port) 
                                   net (fanout=1)        0.103       0.103         nt_mem_dq[5]     
 IOBS_300_360/DIN                  td                    0.853       0.956 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_0/O
                                   net (fanout=1)        0.000       0.956         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/ntI
 IOLHR_292_360/DI_TO_CLK           td                    0.739       1.695 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/DI_TO_CLK
                                   net (fanout=2)        0.237       1.932         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_in_dly [5]
 CLMA_285_355/A2                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L6Q_perm/I2

 Data arrival time                                                   1.932         Logic Levels: 2  
                                                                                   Logic: 1.592ns(82.402%), Route: 0.340ns(17.598%)
====================================================================================================

{ref_clk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 19.800      20.000          0.200           High Pulse Width  CLMA_147_432/CLK        u_adc_ctrl/dbg_temp_rd_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_147_432/CLK        u_adc_ctrl/dbg_temp_rd_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           High Pulse Width  CLMA_147_432/CLK        u_adc_ctrl/dbg_temp_rd_pos_d[1]/opit_0_inv/CLK
====================================================================================================

{rst_clk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 19.800      20.000          0.200           High Pulse Width  CLMA_201_288/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_201_288/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_171_360/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[0]/opit_0_inv_L5Q_perm/CLK
====================================================================================================

{ddrphy_sysclk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 3.609       3.809           0.200           High Pulse Width  CLMA_243_205/CLK        I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
 3.609       3.809           0.200           High Pulse Width  CLMA_261_241/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_calib_mux/calib_address[0]/opit_0_inv_L6Q_perm/CLK
 3.609       3.809           0.200           High Pulse Width  CLMA_273_246/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_calib_mux/calib_address[1]/opit_0_inv_L6Q_perm/CLK
====================================================================================================

{phy_dq_clk_0} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 0.011       0.476           0.465           High Pulse Width  DDR_PHY_297_159/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst/CLKA
 0.011       0.476           0.465           Low Pulse Width   DDR_PHY_297_159/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst/CLKA
 0.011       0.476           0.465           High Pulse Width  TSERDES_299_159/SERCLK  I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_tserdes_ca0/oserdes_inst/SERCLK
====================================================================================================

{phy_dq_sysclk_0} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 1.659       3.809           2.150           Low Pulse Width   DDRPHY_CPD_297_4/PPLL_SYSCLK
                                                                                       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
 1.660       3.810           2.150           High Pulse Width  DDRPHY_CPD_297_4/PPLL_SYSCLK
                                                                                       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
 2.209       3.809           1.600           Low Pulse Width   TSERDES_299_159/OCLKDIV I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_tserdes_ca0/oserdes_inst/OCLKDIV
====================================================================================================

{phy_dq_clk_1} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 0.011       0.476           0.465           High Pulse Width  DDR_PHY_297_307/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY/CLKA
 0.011       0.476           0.465           Low Pulse Width   DDR_PHY_297_307/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY/CLKA
 0.011       0.476           0.465           Low Pulse Width   TSERDES_299_308/SERCLK  I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/SERCLK
====================================================================================================

{phy_dq_sysclk_1} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_318/ICLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_318/OCLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/OCLKDIV
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_324/ICLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV
====================================================================================================

====================================================================================================
Fast Corner
****************************************************************************************************
====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.154  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.105
  Launch Clock Delay      :  2.482
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.304       2.482         _N111            
 CLMA_171_342/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMA_171_342/Q2                   tco                   0.125       2.607 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      0.810       3.417         uart_read_addr[4]
 CLMS_255_313/Y1                   td                    0.070       3.487 f       u_uart_rd_lock/N214_37[9]_2/LUT6D_inst_perm/L6
                                   net (fanout=32)       0.769       4.256         _N41416          
 CLMA_177_336/Y2                   td                    0.125       4.381 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N500/LUT6_inst_perm/L6
                                   net (fanout=32)       0.635       5.016         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N500
 CLMA_147_385/CE                                                           r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/CE

 Data arrival time                                                   5.016         Logic Levels: 2  
                                                                                   Logic: 0.320ns(12.628%), Route: 2.214ns(87.372%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.251      42.105         _N109            
 CLMA_147_385/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.328                          
 clock uncertainty                                      -0.050      42.278                          

 Setup time                                             -0.116      42.162                          

 Data required time                                                 42.162                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.162                          
 Data arrival time                                                   5.016                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.146                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[23]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.154  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.105
  Launch Clock Delay      :  2.482
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.304       2.482         _N111            
 CLMA_171_342/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMA_171_342/Q2                   tco                   0.125       2.607 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      0.810       3.417         uart_read_addr[4]
 CLMS_255_313/Y1                   td                    0.070       3.487 f       u_uart_rd_lock/N214_37[9]_2/LUT6D_inst_perm/L6
                                   net (fanout=32)       0.769       4.256         _N41416          
 CLMA_177_336/Y2                   td                    0.125       4.381 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N500/LUT6_inst_perm/L6
                                   net (fanout=32)       0.635       5.016         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N500
 CLMA_147_385/CE                                                           r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[23]/opit_0_inv/CE

 Data arrival time                                                   5.016         Logic Levels: 2  
                                                                                   Logic: 0.320ns(12.628%), Route: 2.214ns(87.372%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.251      42.105         _N109            
 CLMA_147_385/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[23]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.328                          
 clock uncertainty                                      -0.050      42.278                          

 Setup time                                             -0.116      42.162                          

 Data required time                                                 42.162                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.162                          
 Data arrival time                                                   5.016                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.146                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[17]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.156  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.103
  Launch Clock Delay      :  2.482
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.304       2.482         _N111            
 CLMA_171_342/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMA_171_342/Q2                   tco                   0.125       2.607 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      0.810       3.417         uart_read_addr[4]
 CLMS_255_313/Y1                   td                    0.070       3.487 f       u_uart_rd_lock/N214_37[9]_2/LUT6D_inst_perm/L6
                                   net (fanout=32)       0.769       4.256         _N41416          
 CLMA_177_336/Y2                   td                    0.125       4.381 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N500/LUT6_inst_perm/L6
                                   net (fanout=32)       0.544       4.925         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N500
 CLMS_159_385/CE                                                           r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[17]/opit_0_inv/CE

 Data arrival time                                                   4.925         Logic Levels: 2  
                                                                                   Logic: 0.320ns(13.099%), Route: 2.123ns(86.901%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.249      42.103         _N109            
 CLMS_159_385/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[17]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.326                          
 clock uncertainty                                      -0.050      42.276                          

 Setup time                                             -0.116      42.160                          

 Data required time                                                 42.160                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.160                          
 Data arrival time                                                   4.925                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.235                          
====================================================================================================

====================================================================================================

Startpoint  : u_adc_ctrl/paddr[0]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : u_adc_ctrl/dbg_temp_rd_pos_d[1]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.469
  Launch Clock Delay      :  2.097
  Clock Pessimism Removal :  -0.372

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.243       2.097         _N109            
 CLMA_147_432/CLK                                                          r       u_adc_ctrl/paddr[0]/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_147_432/Q1                   tco                   0.103       2.200 r       u_adc_ctrl/paddr[0]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=2)        0.055       2.255         u_adc_ctrl/dbg_temp_rd_pos_d [0]
 CLMA_147_432/M3                                                           r       u_adc_ctrl/dbg_temp_rd_pos_d[1]/opit_0_inv/D

 Data arrival time                                                   2.255         Logic Levels: 0  
                                                                                   Logic: 0.103ns(65.190%), Route: 0.055ns(34.810%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.291       2.469         _N109            
 CLMA_147_432/CLK                                                          r       u_adc_ctrl/dbg_temp_rd_pos_d[1]/opit_0_inv/CLK
 clock pessimism                                        -0.372       2.097                          
 clock uncertainty                                       0.000       2.097                          

 Hold time                                               0.026       2.123                          

 Data required time                                                  2.123                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.123                          
 Data arrival time                                                   2.255                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.132                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b2[7]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[23]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.151  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.480
  Launch Clock Delay      :  2.106
  Clock Pessimism Removal :  -0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.252       2.106         _N109            
 CLMA_159_366/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b2[7]/opit_0_inv/CLK

 CLMA_159_366/Q0                   tco                   0.109       2.215 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b2[7]/opit_0_inv/Q
                                   net (fanout=14)       0.206       2.421         u_ips2l_uart_ctrl/u_uart_ctrl/data [23]
 CLMA_171_354/BD                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[23]/opit_0_inv/D

 Data arrival time                                                   2.421         Logic Levels: 0  
                                                                                   Logic: 0.109ns(34.603%), Route: 0.206ns(65.397%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.302       2.480         _N111            
 CLMA_171_354/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[23]/opit_0_inv/CLK
 clock pessimism                                        -0.223       2.257                          
 clock uncertainty                                       0.000       2.257                          

 Hold time                                               0.029       2.286                          

 Data required time                                                  2.286                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.286                          
 Data arrival time                                                   2.421                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.135                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[0]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[8]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.148  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.477
  Launch Clock Delay      :  2.106
  Clock Pessimism Removal :  -0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.252       2.106         _N111            
 CLMA_171_361/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[0]/opit_0_inv/CLK

 CLMA_171_361/Q0                   tco                   0.103       2.209 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[0]/opit_0_inv/Q
                                   net (fanout=14)       0.211       2.420         u_ips2l_uart_ctrl/u_uart_ctrl/data [8]
 CLMA_159_372/BD                                                           r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[8]/opit_0_inv/D

 Data arrival time                                                   2.420         Logic Levels: 0  
                                                                                   Logic: 0.103ns(32.803%), Route: 0.211ns(67.197%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.299       2.477         _N109            
 CLMA_159_372/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[8]/opit_0_inv/CLK
 clock pessimism                                        -0.223       2.254                          
 clock uncertainty                                       0.000       2.254                          

 Hold time                                               0.029       2.283                          

 Data required time                                                  2.283                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.283                          
 Data arrival time                                                   2.420                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.137                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/tran_err_rst_cnt[5]/opit_0_inv_L6QL5Q1_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/I1
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.149  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.962
  Launch Clock Delay      :  3.554
  Clock Pessimism Removal :  0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=74)       0.310       3.554         _N115            
 CLMA_201_337/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/tran_err_rst_cnt[5]/opit_0_inv_L6QL5Q1_perm/CLK

 CLMA_201_337/CR1                  tco                   0.142       3.696 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/tran_err_rst_cnt[5]/opit_0_inv_L6QL5Q1_perm/L5Q
                                   net (fanout=3)        0.320       4.016         dbg_tran_err_rst_cnt[4]
 CLMA_195_330/Y2                   td                    0.122       4.138 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N161_1_3/LUT6_inst_perm/L6
                                   net (fanout=2)        0.353       4.491         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N46865
 CLMS_177_325/Y3                   td                    0.066       4.557 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_9/gateop_perm/L6
                                   net (fanout=3)        0.164       4.721         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N40242
 CLMA_171_318/Y1                   td                    0.039       4.760 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_107/gateop_perm/L6
                                   net (fanout=2)        0.234       4.994         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N42219
 CLMA_171_307/Y1                   td                    0.123       5.117 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_49/gateop_LUT6DL5_perm/L6
                                   net (fanout=1)        0.332       5.449         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N48
 CLMS_159_313/B1                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/I1

 Data arrival time                                                   5.449         Logic Levels: 4  
                                                                                   Logic: 0.492ns(25.963%), Route: 1.403ns(74.037%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.262      42.962         _N116            
 CLMS_159_313/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/CLK
 clock pessimism                                         0.443      43.405                          
 clock uncertainty                                      -0.150      43.255                          

 Setup time                                             -0.137      43.118                          

 Data required time                                                 43.118                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.118                          
 Data arrival time                                                   5.449                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.669                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CE
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.962
  Launch Clock Delay      :  3.554
  Clock Pessimism Removal :  0.592

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.310       3.554         _N116            
 CLMA_147_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CLK

 CLMA_147_325/Q0                   tco                   0.125       3.679 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=2)        0.386       4.065         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [18]
 CLMA_147_307/Y3                   td                    0.070       4.135 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=2)        0.160       4.295         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N46855
 CLMA_147_313/Y1                   td                    0.122       4.417 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_1/gateop_perm/L6
                                   net (fanout=11)       0.324       4.741         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N49
 CLMA_147_288/Y0                   td                    0.055       4.796 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_deb_pre/opit_0_inv_L5Q_perm/L6
                                   net (fanout=10)       0.325       5.121         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43
 CLMA_147_319/CECO                 td                    0.088       5.209 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L6Q_perm/CECO
                                   net (fanout=1)        0.000       5.209         ntR23            
 CLMA_147_325/CECI                                                         r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CE

 Data arrival time                                                   5.209         Logic Levels: 4  
                                                                                   Logic: 0.460ns(27.795%), Route: 1.195ns(72.205%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.262      42.962         _N116            
 CLMA_147_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.592      43.554                          
 clock uncertainty                                      -0.150      43.404                          

 Setup time                                             -0.116      43.288                          

 Data required time                                                 43.288                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.288                          
 Data arrival time                                                   5.209                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.079                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[10]/opit_0_inv_L6Q_perm/CE
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.149  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.961
  Launch Clock Delay      :  3.553
  Clock Pessimism Removal :  0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.309       3.553         _N116            
 CLMA_159_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]/opit_0_inv_L6Q_perm/CLK

 CLMA_159_318/Q1                   tco                   0.125       3.678 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=5)        0.406       4.084         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [5]
 CLMS_159_319/Y3                   td                    0.070       4.154 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N250_10/gateop_perm/L6
                                   net (fanout=5)        0.418       4.572         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N46789
 CLMA_177_318/Y1                   td                    0.070       4.642 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N338/LUT6_inst_perm/L6
                                   net (fanout=6)        0.431       5.073         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N338
 CLMA_177_318/CE                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[10]/opit_0_inv_L6Q_perm/CE

 Data arrival time                                                   5.073         Logic Levels: 2  
                                                                                   Logic: 0.265ns(17.434%), Route: 1.255ns(82.566%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=74)       0.261      42.961         _N115            
 CLMA_177_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[10]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.443      43.404                          
 clock uncertainty                                      -0.150      43.254                          

 Setup time                                             -0.072      43.182                          

 Data required time                                                 43.182                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.182                          
 Data arrival time                                                   5.073                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.109                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[9]/opit_0_inv_AQ_perm/CIN
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.147  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.565
  Launch Clock Delay      :  2.975
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.275       2.975         _N114            
 CLMA_231_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/CLK

 CLMA_231_301/Q1                   tco                   0.103       3.078 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[6]/opit_0_inv_AQ_perm/Q
                                   net (fanout=7)        0.059       3.137         debug_dps_cnt_dir0[6]
 CLMA_231_301/COUT                 td                    0.083       3.220 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/COUT
                                   net (fanout=1)        0.000       3.220         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/_N7780
 CLMA_231_307/CIN                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[9]/opit_0_inv_AQ_perm/CIN

 Data arrival time                                                   3.220         Logic Levels: 1  
                                                                                   Logic: 0.186ns(75.918%), Route: 0.059ns(24.082%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=74)       0.321       3.565         _N115            
 CLMA_231_307/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[9]/opit_0_inv_AQ_perm/CLK
 clock pessimism                                        -0.443       3.122                          
 clock uncertainty                                       0.000       3.122                          

 Hold time                                              -0.014       3.108                          

 Data required time                                                  3.108                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.108                          
 Data arrival time                                                   3.220                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.112                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[0]/opit_0_inv_L6Q_perm/I2
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.147  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.565
  Launch Clock Delay      :  2.975
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.275       2.975         _N114            
 CLMA_231_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/CLK

 CLMA_231_301/Q1                   tco                   0.109       3.084 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[6]/opit_0_inv_AQ_perm/Q
                                   net (fanout=7)        0.112       3.196         debug_dps_cnt_dir0[6]
 CLMA_231_307/B2                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[0]/opit_0_inv_L6Q_perm/I2

 Data arrival time                                                   3.196         Logic Levels: 0  
                                                                                   Logic: 0.109ns(49.321%), Route: 0.112ns(50.679%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=74)       0.321       3.565         _N115            
 CLMA_231_307/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[0]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                        -0.443       3.122                          
 clock uncertainty                                       0.000       3.122                          

 Hold time                                              -0.054       3.068                          

 Data required time                                                  3.068                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.068                          
 Data arrival time                                                   3.196                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.128                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[0]/opit_0_inv_L6Q_perm/I0
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.147  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.565
  Launch Clock Delay      :  2.975
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.275       2.975         _N114            
 CLMA_231_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[8]/opit_0_inv_AQ_perm/CLK

 CLMA_231_301/Q2                   tco                   0.109       3.084 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[7]/opit_0_inv_AQ_perm/Q
                                   net (fanout=7)        0.112       3.196         debug_dps_cnt_dir0[7]
 CLMA_231_307/B0                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[0]/opit_0_inv_L6Q_perm/I0

 Data arrival time                                                   3.196         Logic Levels: 0  
                                                                                   Logic: 0.109ns(49.321%), Route: 0.112ns(50.679%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=74)       0.321       3.565         _N115            
 CLMA_231_307/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[0]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                        -0.443       3.122                          
 clock uncertainty                                       0.000       3.122                          

 Hold time                                              -0.069       3.053                          

 Data required time                                                  3.053                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.053                          
 Data arrival time                                                   3.196                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.143                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_value[6]/opit_0_inv_L6Q_perm/I2
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.049  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.340
  Launch Clock Delay      :  4.433
  Clock Pessimism Removal :  1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.314       4.433         _N105            
 CLMA_219_265/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L6Q_perm/CLK

 CLMA_219_265/Q1                   tco                   0.125       4.558 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=13)       0.439       4.997         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dqs_gate_vld
 CLMA_201_276/Y2                   td                    0.122       5.119 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N40_13[2]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.236       5.355         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/_N14305
 CLMA_195_282/Y3                   td                    0.125       5.480 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N40_16[2]_3/gateop_perm/L6
                                   net (fanout=2)        0.160       5.640         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_next [2]
 CLMA_201_282/Y2                   td                    0.066       5.706 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N190_1/LUT6_inst_perm/L6
                                   net (fanout=2)        0.246       5.952         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/_N41732
 CLMS_195_283/Y1                   td                    0.070       6.022 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N222_1/LUT6_inst_perm/L6
                                   net (fanout=9)        0.243       6.265         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N276
 CLMS_195_265/Y1                   td                    0.066       6.331 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N230_3/gateop_perm/L6
                                   net (fanout=3)        0.075       6.406         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N230
 CLMS_195_265/Y0                   td                    0.070       6.476 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N223_7_maj1/LUT6_inst_perm/L6
                                   net (fanout=2)        0.075       6.551         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/_N4386
 CLMS_195_265/Y2                   td                    0.122       6.673 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N223_7_ac3/LUT6_inst_perm/L6
                                   net (fanout=3)        0.247       6.920         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/_N4393
 CLMA_201_276/Y1                   td                    0.125       7.045 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N223_7_ac4/LUT6_inst_perm/L6
                                   net (fanout=1)        0.267       7.312         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/_N4397
 CLMS_195_277/Y3                   td                    0.040       7.352 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/N223_7_sum6/LUT6_inst_perm/L6
                                   net (fanout=1)        0.222       7.574         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/nb5 [6]
 CLMA_195_282/C2                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_value[6]/opit_0_inv_L6Q_perm/I2

 Data arrival time                                                   7.574         Logic Levels: 9  
                                                                                   Logic: 0.931ns(29.640%), Route: 2.210ns(70.360%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.265      10.959         _N105            
 CLMA_195_282/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_value[6]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         1.044      12.003                          
 clock uncertainty                                      -0.150      11.853                          

 Setup time                                             -0.120      11.733                          

 Data required time                                                 11.733                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.733                          
 Data arrival time                                                   7.574                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.159                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/dll_90_bin[0]/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/wl_p_dll_bin[7]/opit_0_inv_L6Q_perm/I2
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.042  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.350
  Launch Clock Delay      :  4.436
  Clock Pessimism Removal :  1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.317       4.436         _N106            
 CLMA_219_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/dll_90_bin[0]/opit_0_inv/CLK

 CLMA_219_319/CR2                  tco                   0.140       4.576 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/dll_90_bin[0]/opit_0_inv/Q
                                   net (fanout=12)       0.396       4.972         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dll_90_bin [0]
 CLMA_219_306/COUT                 td                    0.245       5.217 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N255.fsub_4/gateop_perm/COUT
                                   net (fanout=1)        0.000       5.217         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N255.co [4]
 CLMA_219_312/Y2                   td                    0.093       5.310 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N255.fsub_7/gateop_perm/Y
                                   net (fanout=1)        0.358       5.668         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/wrcal_step_minus [6]
 CLMA_213_337/CR0                  td                    0.185       5.853 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[1]/opit_0_inv_L6Q_LUT6DQL5_perm/L5
                                   net (fanout=1)        0.402       6.255         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/_N15233
 CLMA_213_319/COUT                 td                    0.131       6.386 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N263_1_7/gateop_perm/COUT
                                   net (fanout=1)        0.000       6.386         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/_N7394
 CLMA_213_325/Y1                   td                    0.087       6.473 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N263_1_9/gateop_perm/Y
                                   net (fanout=1)        0.427       6.900         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N263 [8]
 CLMA_237_318/Y1                   td                    0.104       7.004 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N265_mux8/LUT6_inst_perm/L6
                                   net (fanout=1)        0.071       7.075         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N265
 CLMA_237_318/Y0                   td                    0.100       7.175 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/N513_83/gateop_perm/L6
                                   net (fanout=8)        0.376       7.551         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/_N15268
 CLMS_267_331/D2                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/wl_p_dll_bin[7]/opit_0_inv_L6Q_perm/I2

 Data arrival time                                                   7.551         Logic Levels: 7  
                                                                                   Logic: 1.085ns(34.831%), Route: 2.030ns(65.169%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.275      10.969         _N106            
 CLMS_267_331/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/wl_p_dll_bin[7]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         1.044      12.013                          
 clock uncertainty                                      -0.150      11.863                          

 Setup time                                             -0.110      11.753                          

 Data required time                                                 11.753                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.753                          
 Data arrival time                                                   7.551                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.202                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/dll_90_bin[1]/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/wl_p_dll_bin[6]/opit_0_inv_L6Q_perm/I3
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.018  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.329
  Launch Clock Delay      :  4.424
  Clock Pessimism Removal :  1.077

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.305       4.424         _N106            
 CLMS_195_361/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/dll_90_bin[1]/opit_0_inv/CLK

 CLMS_195_361/CR0                  tco                   0.140       4.564 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/dll_90_bin[1]/opit_0_inv/Q
                                   net (fanout=6)        0.428       4.992         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dll_90_bin [1]
 CLMA_201_372/COUT                 td                    0.198       5.190 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N255.fsub_4/gateop_perm/COUT
                                   net (fanout=1)        0.000       5.190         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N255.co [4]
 CLMA_201_378/Y3                   td                    0.140       5.330 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N255.fsub_8/gateop_perm/Y
                                   net (fanout=4)        0.326       5.656         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/wrcal_step_minus[7]_inv
 CLMA_201_366/CR2                  td                    0.138       5.794 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N260_8[0]/LUT6D_inst_perm/L5
                                   net (fanout=1)        0.267       6.061         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/_N11788
 CLMA_195_366/COUT                 td                    0.248       6.309 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N263_1_3/gateop_perm/COUT
                                   net (fanout=1)        0.000       6.309         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/_N7502
 CLMA_195_372/COUT                 td                    0.056       6.365 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N263_1_7/gateop_perm/COUT
                                   net (fanout=1)        0.000       6.365         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/_N7506
 CLMA_195_378/Y0                   td                    0.037       6.402 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N263_1_8/gateop_perm/Y
                                   net (fanout=2)        0.439       6.841         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N263 [7]
 CLMA_195_354/Y3                   td                    0.070       6.911 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N265_mux8/LUT6_inst_perm/L6
                                   net (fanout=1)        0.259       7.170         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N265
 CLMA_183_360/Y1                   td                    0.070       7.240 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N513_82/gateop_perm/L6
                                   net (fanout=8)        0.346       7.586         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/_N14351
 CLMS_195_373/B3                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/wl_p_dll_bin[6]/opit_0_inv_L6Q_perm/I3

 Data arrival time                                                   7.586         Logic Levels: 8  
                                                                                   Logic: 1.097ns(34.693%), Route: 2.065ns(65.307%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.254      10.948         _N106            
 CLMS_195_373/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/wl_p_dll_bin[6]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         1.077      12.025                          
 clock uncertainty                                      -0.150      11.875                          

 Setup time                                             -0.080      11.795                          

 Data required time                                                 11.795                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.795                          
 Data arrival time                                                   7.586                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.209                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[2]/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/opit_0_inv_32X2DL6QL5Q/WADDR[2]
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.053  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.421
  Launch Clock Delay      :  3.324
  Clock Pessimism Removal :  -1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.249       3.324         _N105            
 CLMA_183_205/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[2]/opit_0_inv_L6Q_perm/CLK

 CLMA_183_205/Q1                   tco                   0.109       3.433 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[2]/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=23)       0.205       3.638         I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/wr_addr [2]
 CLMS_195_217/D2                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/opit_0_inv_32X2DL6QL5Q/WADDR[2]

 Data arrival time                                                   3.638         Logic Levels: 0  
                                                                                   Logic: 0.109ns(34.713%), Route: 0.205ns(65.287%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.302       4.421         _N105            
 CLMS_195_217/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/opit_0_inv_32X2DL6QL5Q/CLK
 clock pessimism                                        -1.044       3.377                          
 clock uncertainty                                       0.000       3.377                          

 Hold time                                               0.161       3.538                          

 Data required time                                                  3.538                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.538                          
 Data arrival time                                                   3.638                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.100                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[2]/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[29]/opit_0_inv_32X2DL6QL5Q/WADDR[2]
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.053  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.421
  Launch Clock Delay      :  3.324
  Clock Pessimism Removal :  -1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.249       3.324         _N105            
 CLMA_183_205/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[2]/opit_0_inv_L6Q_perm/CLK

 CLMA_183_205/Q1                   tco                   0.109       3.433 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[2]/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=23)       0.205       3.638         I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/wr_addr [2]
 CLMS_195_217/D2                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[29]/opit_0_inv_32X2DL6QL5Q/WADDR[2]

 Data arrival time                                                   3.638         Logic Levels: 0  
                                                                                   Logic: 0.109ns(34.713%), Route: 0.205ns(65.287%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.302       4.421         _N105            
 CLMS_195_217/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[29]/opit_0_inv_32X2DL6QL5Q/CLK
 clock pessimism                                        -1.044       3.377                          
 clock uncertainty                                       0.000       3.377                          

 Hold time                                               0.161       3.538                          

 Data required time                                                  3.538                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.538                          
 Data arrival time                                                   3.638                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.100                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[2]/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[32]/opit_0_inv_32X2DL5Q/WADDR[2]
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.053  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.421
  Launch Clock Delay      :  3.324
  Clock Pessimism Removal :  -1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.249       3.324         _N105            
 CLMA_183_205/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[2]/opit_0_inv_L6Q_perm/CLK

 CLMA_183_205/Q1                   tco                   0.109       3.433 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[2]/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=23)       0.205       3.638         I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/wr_addr [2]
 CLMS_195_217/D2                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[32]/opit_0_inv_32X2DL5Q/WADDR[2]

 Data arrival time                                                   3.638         Logic Levels: 0  
                                                                                   Logic: 0.109ns(34.713%), Route: 0.205ns(65.287%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.302       4.421         _N105            
 CLMS_195_217/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[32]/opit_0_inv_32X2DL5Q/CLK
 clock pessimism                                        -1.044       3.377                          
 clock uncertainty                                       0.000       3.377                          

 Hold time                                               0.161       3.538                          

 Data required time                                                  3.538                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.538                          
 Data arrival time                                                   3.638                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.100                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[6]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    1.422  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.339
  Launch Clock Delay      :  2.076
  Clock Pessimism Removal :  0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.137       3.980         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_396/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_396/RX_DATA[6]          tco                   0.260       4.240 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/RX_DATA[6]
                                   net (fanout=1)        0.311       4.551         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [6]
 CLMA_285_415/CR1                  td                    0.067       4.618 f       CLKROUTE_69/CR   
                                   net (fanout=1)        0.164       4.782         _N76             
 CLMA_285_408/CR2                  td                    0.066       4.848 f       CLKROUTE_70/CR   
                                   net (fanout=1)        1.667       6.515         _N77             
 CLMS_273_397/M0                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[6]/opit_0_inv_srl/D

 Data arrival time                                                   6.515         Logic Levels: 2  
                                                                                   Logic: 0.393ns(15.503%), Route: 2.142ns(84.497%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.264      10.958         _N106            
 CLMS_273_397/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[6]/opit_0_inv_srl/CLK
 clock pessimism                                         0.159      11.117                          
 clock uncertainty                                      -0.550      10.567                          

 Setup time                                             -0.074      10.493                          

 Data required time                                                 10.493                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.493                          
 Data arrival time                                                   6.515                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.978                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[57]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    1.428  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.345
  Launch Clock Delay      :  2.076
  Clock Pessimism Removal :  0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.137       3.980         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_450/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_450/RX_DATA[1]          tco                   0.260       4.240 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/RX_DATA[1]
                                   net (fanout=1)        0.309       4.549         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [57]
 CLMS_279_445/CR3                  td                    0.065       4.614 f       CLKROUTE_87/CR   
                                   net (fanout=1)        0.405       5.019         _N94             
 CLMA_273_432/CR1                  td                    0.067       5.086 f       CLKROUTE_88/CR   
                                   net (fanout=1)        1.218       6.304         _N95             
 CLMA_279_366/M3                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[57]/opit_0_inv_srl/D

 Data arrival time                                                   6.304         Logic Levels: 2  
                                                                                   Logic: 0.392ns(16.867%), Route: 1.932ns(83.133%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.270      10.964         _N106            
 CLMA_279_366/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[57]/opit_0_inv_srl/CLK
 clock pessimism                                         0.159      11.123                          
 clock uncertainty                                      -0.550      10.573                          

 Setup time                                             -0.005      10.568                          

 Data required time                                                 10.568                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.568                          
 Data arrival time                                                   6.304                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.264                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[8]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    1.425  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.342
  Launch Clock Delay      :  2.076
  Clock Pessimism Removal :  0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.137       3.980         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_402/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_402/RX_DATA[0]          tco                   0.260       4.240 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/RX_DATA[0]
                                   net (fanout=1)        0.289       4.529         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [8]
 CLMA_285_402/CR2                  td                    0.066       4.595 f       CLKROUTE_71/CR   
                                   net (fanout=1)        1.629       6.224         _N78             
 CLMS_267_373/M1                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[8]/opit_0_inv_srl/D

 Data arrival time                                                   6.224         Logic Levels: 1  
                                                                                   Logic: 0.326ns(14.528%), Route: 1.918ns(85.472%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.267      10.961         _N106            
 CLMS_267_373/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[8]/opit_0_inv_srl/CLK
 clock pessimism                                         0.159      11.120                          
 clock uncertainty                                      -0.550      10.570                          

 Setup time                                             -0.074      10.496                          

 Data required time                                                 10.496                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.496                          
 Data arrival time                                                   6.224                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.272                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[6].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[52]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    2.526  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.437
  Launch Clock Delay      :  1.752
  Clock Pessimism Removal :  -0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    0.564      10.185 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.185         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      10.258 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      10.421         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      10.501 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      10.719         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      10.816 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      11.063         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      11.089 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      11.089         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      11.161 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.114      11.275         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_444/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[6].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_444/RX_DATA[4]          tco                   0.155      11.430 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[6].u_iobuf_dq/opit_1/RX_DATA[4]
                                   net (fanout=1)        1.093      12.523         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [52]
 CLMA_279_372/M1                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[52]/opit_0_inv_srl/D

 Data arrival time                                                  12.523         Logic Levels: 0  
                                                                                   Logic: 0.155ns(12.420%), Route: 1.093ns(87.580%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.318      12.056         _N106            
 CLMA_279_372/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[52]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.159      11.897                          
 clock uncertainty                                       0.550      12.447                          

 Hold time                                              -0.025      12.422                          

 Data required time                                                 12.422                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.422                          
 Data arrival time                                                  12.523                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[0]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    2.520  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.431
  Launch Clock Delay      :  1.752
  Clock Pessimism Removal :  -0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    0.564      10.185 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.185         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      10.258 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      10.421         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      10.501 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      10.719         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      10.816 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      11.063         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      11.089 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      11.089         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      11.161 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.114      11.275         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_396/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_396/RX_DATA[0]          tco                   0.155      11.430 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/RX_DATA[0]
                                   net (fanout=1)        1.088      12.518         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [0]
 CLMS_273_397/M1                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[0]/opit_0_inv_srl/D

 Data arrival time                                                  12.518         Logic Levels: 0  
                                                                                   Logic: 0.155ns(12.470%), Route: 1.088ns(87.530%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.312      12.050         _N106            
 CLMS_273_397/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[0]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.159      11.891                          
 clock uncertainty                                       0.550      12.441                          

 Hold time                                              -0.025      12.416                          

 Data required time                                                 12.416                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.416                          
 Data arrival time                                                  12.518                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.102                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[42]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    2.530  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.441
  Launch Clock Delay      :  1.752
  Clock Pessimism Removal :  -0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    0.564      10.185 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.185         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      10.258 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      10.421         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      10.501 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      10.719         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      10.816 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      11.063         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      11.089 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      11.089         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      11.161 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.114      11.275         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_360/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_360/RX_DATA[2]          tco                   0.155      11.430 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/RX_DATA[2]
                                   net (fanout=1)        1.151      12.581         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_rdata [42]
 CLMA_285_354/M3                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[42]/opit_0_inv_srl/D

 Data arrival time                                                  12.581         Logic Levels: 0  
                                                                                   Logic: 0.155ns(11.868%), Route: 1.151ns(88.132%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.322      12.060         _N106            
 CLMA_285_354/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[42]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.159      11.901                          
 clock uncertainty                                       0.550      12.451                          

 Hold time                                               0.026      12.477                          

 Data required time                                                 12.477                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.477                          
 Data arrival time                                                  12.581                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.104                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
Endpoint    : I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    1.700  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.338
  Launch Clock Delay      :  1.939
  Clock Pessimism Removal :  0.301

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.843         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 DDRPHY_CPD_297_4/PPLL_SYSCLK                                              r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY

 DDRPHY_CPD_297_4/CPD_UP_DNB       tco                   0.069       3.912 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/FLAG_PD
                                   net (fanout=2)        1.909       5.821         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_up_dnb
 CLMA_213_253/M2                                                           f       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D

 Data arrival time                                                   5.821         Logic Levels: 0  
                                                                                   Logic: 0.069ns(3.488%), Route: 1.909ns(96.512%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.263      10.957         _N105            
 CLMA_213_253/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                         0.301      11.258                          
 clock uncertainty                                      -0.550      10.708                          

 Setup time                                             -0.074      10.634                          

 Data required time                                                 10.634                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.634                          
 Data arrival time                                                   5.821                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.813                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
Endpoint    : I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    2.491  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.430
  Launch Clock Delay      :  1.638
  Clock Pessimism Removal :  -0.301

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    0.564      10.185 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.185         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      10.258 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      10.421         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      10.501 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      10.719         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097      10.816 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      11.063         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026      11.089 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      11.089         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072      11.161 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      11.161         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 DDRPHY_CPD_297_4/PPLL_SYSCLK                                              r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY

 DDRPHY_CPD_297_4/CPD_UP_DNB       tco                   0.042      11.203 r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/FLAG_PD
                                   net (fanout=2)        1.316      12.519         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_up_dnb
 CLMA_213_253/M2                                                           r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D

 Data arrival time                                                  12.519         Logic Levels: 0  
                                                                                   Logic: 0.042ns(3.093%), Route: 1.316ns(96.907%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.311      12.049         _N105            
 CLMA_213_253/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.301      11.748                          
 clock uncertainty                                       0.550      12.298                          

 Hold time                                              -0.025      12.273                          

 Data required time                                                 12.273                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.273                          
 Data arrival time                                                  12.519                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.246                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[7].u_outbuft_addr0/opit_1/TX_DATA[1]
Path Group  : phy_dq_sysclk_0
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.388  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.442
  Clock Pessimism Removal :  0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.323      12.061         _N105            
 CLMA_279_252/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_279_252/Q0                   tco                   0.125      12.186 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        0.673      12.859         debug_data[135]  
 CLMA_285_186/Y0                   td                    0.066      12.925 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       0.484      13.409         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_253/Y0                   td                    0.122      13.531 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_63:56_2[1]/LUT6D_inst_perm/L6
                                   net (fanout=2)        1.150      14.681         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [57]
 IOLHR_292_252/TX_DATA[1]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[7].u_outbuft_addr0/opit_1/TX_DATA[1]

 Data arrival time                                                  14.681         Logic Levels: 2  
                                                                                   Logic: 0.313ns(11.947%), Route: 2.307ns(88.053%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_252/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[7].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.301      19.196                          
 clock uncertainty                                      -0.550      18.646                          

 Setup time                                             -0.189      18.457                          

 Data required time                                                 18.457                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.457                          
 Data arrival time                                                  14.681                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.776                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[3].u_outbuft_addr0/opit_1/TX_DATA[6]
Path Group  : phy_dq_sysclk_0
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.388  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.442
  Clock Pessimism Removal :  0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.323      12.061         _N105            
 CLMA_279_252/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_279_252/Q0                   tco                   0.125      12.186 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        0.673      12.859         debug_data[135]  
 CLMA_285_186/Y0                   td                    0.066      12.925 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       0.572      13.497         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_276/Y1                   td                    0.066      13.563 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_31:24_2[3]/LUT6D_inst_perm/L6
                                   net (fanout=2)        1.066      14.629         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [29]
 IOLHR_292_276/TX_DATA[6]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[3].u_outbuft_addr0/opit_1/TX_DATA[6]

 Data arrival time                                                  14.629         Logic Levels: 2  
                                                                                   Logic: 0.257ns(10.008%), Route: 2.311ns(89.992%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_276/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[3].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.301      19.196                          
 clock uncertainty                                      -0.550      18.646                          

 Setup time                                             -0.189      18.457                          

 Data required time                                                 18.457                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.457                          
 Data arrival time                                                  14.629                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.828                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/TX_DATA[6]
Path Group  : phy_dq_sysclk_0
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.388  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.442
  Clock Pessimism Removal :  0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.323      12.061         _N105            
 CLMA_279_252/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_279_252/Q0                   tco                   0.125      12.186 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        0.673      12.859         debug_data[135]  
 CLMA_285_186/Y0                   td                    0.066      12.925 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       0.624      13.549         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_258/CR2                  td                    0.185      13.734 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_39:32_2[2]/LUT6D_inst_perm/L5
                                   net (fanout=2)        0.881      14.615         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [37]
 IOLHR_292_270/TX_DATA[6]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/TX_DATA[6]

 Data arrival time                                                  14.615         Logic Levels: 2  
                                                                                   Logic: 0.376ns(14.722%), Route: 2.178ns(85.278%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_270/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.301      19.196                          
 clock uncertainty                                      -0.550      18.646                          

 Setup time                                             -0.189      18.457                          

 Data required time                                                 18.457                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.457                          
 Data arrival time                                                  14.615                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.842                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[0].u_outbuft_ba/opit_1/TX_DATA[4]
Path Group  : phy_dq_sysclk_0
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.567  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.343
  Clock Pessimism Removal :  -0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.268       3.343         _N105            
 CLMA_261_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_261_235/Q2                   tco                   0.109       3.452 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=11)       0.561       4.013         I_ips_ddr_top/u_ddrphy_top/phy_ba [0]
 CLMA_285_198/Y1                   td                    0.052       4.065 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_ba_7:0_2[2]/LUT6D_inst_perm/L6
                                   net (fanout=2)        0.240       4.305         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_ba [3]
 IOLHR_292_192/TX_DATA[4]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[0].u_outbuft_ba/opit_1/TX_DATA[4]

 Data arrival time                                                   4.305         Logic Levels: 1  
                                                                                   Logic: 0.161ns(16.736%), Route: 0.801ns(83.264%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_192/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[0].u_outbuft_ba/opit_1/OCLKDIV
 clock pessimism                                        -0.301       3.680                          
 clock uncertainty                                       0.550       4.230                          

 Hold time                                              -0.024       4.206                          

 Data required time                                                  4.206                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.206                          
 Data arrival time                                                   4.305                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.099                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[8].u_outbuft_addr0/opit_1/TX_DATA[5]
Path Group  : phy_dq_sysclk_0
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.570  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.346
  Clock Pessimism Removal :  -0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.271       3.346         _N105            
 CLMA_285_229/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_srl/CLK

 CLMA_285_229/Q1                   tco                   0.109       3.455 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_srl/Q0
                                   net (fanout=6)        0.169       3.624         I_ips_ddr_top/u_ddrphy_top/phy_addr [38]
 CLMA_285_241/CR2                  td                    0.116       3.740 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_71:64_2[2]/LUT6D_inst_perm/L5
                                   net (fanout=2)        0.567       4.307         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [69]
 IOLHR_292_246/TX_DATA[5]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[8].u_outbuft_addr0/opit_1/TX_DATA[5]

 Data arrival time                                                   4.307         Logic Levels: 1  
                                                                                   Logic: 0.225ns(23.413%), Route: 0.736ns(76.587%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_246/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[8].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                        -0.301       3.680                          
 clock uncertainty                                       0.550       4.230                          

 Hold time                                              -0.024       4.206                          

 Data required time                                                  4.206                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.206                          
 Data arrival time                                                   4.307                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[5].u_outbuft_addr0/opit_1/TX_DATA[0]
Path Group  : phy_dq_sysclk_0
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.578  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.354
  Clock Pessimism Removal :  -0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.279       3.354         _N105            
 CLMA_285_271/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/opit_0_inv_srl/CLK

 CLMA_285_271/CR1                  tco                   0.124       3.478 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/opit_0_inv_srl/CR0
                                   net (fanout=1)        0.168       3.646         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r [22]
 CLMA_285_264/CR2                  td                    0.112       3.758 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_39:32_2[4]/LUT6D_inst_perm/L5
                                   net (fanout=1)        0.550       4.308         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [40]
 IOLHR_292_264/TX_DATA[0]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[5].u_outbuft_addr0/opit_1/TX_DATA[0]

 Data arrival time                                                   4.308         Logic Levels: 1  
                                                                                   Logic: 0.236ns(24.738%), Route: 0.718ns(75.262%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_264/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[5].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                        -0.301       3.680                          
 clock uncertainty                                       0.550       4.230                          

 Hold time                                              -0.024       4.206                          

 Data required time                                                  4.206                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.206                          
 Data arrival time                                                   4.308                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.102                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[5]
Path Group  : phy_dq_sysclk_1
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.523  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.435
  Clock Pessimism Removal :  0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.316      12.054         _N106            
 CLMA_285_390/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/CLK

 CLMA_285_390/CR0                  tco                   0.140      12.194 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/L6QQ
                                   net (fanout=12)       1.099      13.293         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r [3]
 CLMA_285_391/Y2                   td                    0.066      13.359 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/N28[5]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.380      13.739         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdq_en [5]
 CLMA_285_361/CR2                  td                    0.066      13.805 f       CLKROUTE_18/CR   
                                   net (fanout=2)        1.206      15.011         _N25             
 TSERDES_299_307/TS_CTRL[5]                                                f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[5]

 Data arrival time                                                  15.011         Logic Levels: 2  
                                                                                   Logic: 0.272ns(9.199%), Route: 2.685ns(90.801%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 TSERDES_299_307/OCLKDIV                                                   r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/OCLKDIV
 clock pessimism                                         0.159      19.054                          
 clock uncertainty                                      -0.550      18.504                          

 Setup time                                             -0.128      18.376                          

 Data required time                                                 18.376                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.376                          
 Data arrival time                                                  15.011                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.365                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[0]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[5]
Path Group  : phy_dq_sysclk_1
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.521  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.433
  Clock Pessimism Removal :  0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.314      12.052         _N106            
 CLMA_285_396/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[0]/opit_0_inv_L6QQ_perm/CLK

 CLMA_285_396/Q0                   tco                   0.125      12.177 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[0]/opit_0_inv_L6QQ_perm/L6Q
                                   net (fanout=12)       0.954      13.131         I_ips_ddr_top/u_ddrphy_top/phy_wrdata_en [0]
 CLMA_285_403/Y3                   td                    0.070      13.201 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/N28[5]/LUT6_inst_perm/L6
                                   net (fanout=2)        1.691      14.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdq_en [5]
 TSERDES_299_309/TS_CTRL[5]                                                f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[5]

 Data arrival time                                                  14.892         Logic Levels: 1  
                                                                                   Logic: 0.195ns(6.866%), Route: 2.645ns(93.134%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 TSERDES_299_309/OCLKDIV                                                   r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/OCLKDIV
 clock pessimism                                         0.159      19.054                          
 clock uncertainty                                      -0.550      18.504                          

 Setup time                                             -0.128      18.376                          

 Data required time                                                 18.376                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.376                          
 Data arrival time                                                  14.892                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.484                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[11]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/TX_DATA[6]
Path Group  : phy_dq_sysclk_1
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.517  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.429
  Clock Pessimism Removal :  0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.310      12.048         _N106            
 CLMS_267_403/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[11]/opit_0_inv_L6QQ_perm/CLK

 CLMS_267_403/Q2                   tco                   0.125      12.173 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[11]/opit_0_inv_L6QQ_perm/L6Q
                                   net (fanout=4)        1.104      13.277         I_ips_ddr_top/u_ddrphy_top/phy_wrdata [49]
 CLMS_267_397/Y1                   td                    0.039      13.316 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[26]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.319      13.635         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdq [14]
 CLMA_267_402/CR2                  td                    0.066      13.701 f       CLKROUTE_49/CR   
                                   net (fanout=1)        1.083      14.784         _N56             
 IOLHR_292_402/TX_DATA[6]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/TX_DATA[6]

 Data arrival time                                                  14.784         Logic Levels: 2  
                                                                                   Logic: 0.230ns(8.406%), Route: 2.506ns(91.594%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_402/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/OCLKDIV
 clock pessimism                                         0.159      19.054                          
 clock uncertainty                                      -0.550      18.504                          

 Setup time                                             -0.189      18.315                          

 Data required time                                                 18.315                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.315                          
 Data arrival time                                                  14.784                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.531                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[2]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/TS_CTRL[7]
Path Group  : phy_dq_sysclk_1
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.423  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.341
  Clock Pessimism Removal :  -0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.266       3.341         _N106            
 CLMA_285_396/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[2]/opit_0_inv_L6QQ_perm/CLK

 CLMA_285_396/Q2                   tco                   0.103       3.444 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[2]/opit_0_inv_L6QQ_perm/L6Q
                                   net (fanout=6)        0.119       3.563         I_ips_ddr_top/u_ddrphy_top/phy_wrdata_en [2]
 CLMA_285_409/Y2                   td                    0.047       3.610 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/N657_8[3]/gateop_perm/L6
                                   net (fanout=1)        0.112       3.722         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/_N15378
 CLMA_285_409/Y0                   td                    0.089       3.811 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/N659[6]/LUT6_inst_perm/L6
                                   net (fanout=2)        0.651       4.462         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdqs_en [6]
 TSERDES_299_310/TS_CTRL[7]                                                r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/TS_CTRL[7]

 Data arrival time                                                   4.462         Logic Levels: 2  
                                                                                   Logic: 0.239ns(21.320%), Route: 0.882ns(78.680%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 TSERDES_299_310/OCLKDIV                                                   r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/OCLKDIV
 clock pessimism                                        -0.159       3.822                          
 clock uncertainty                                       0.550       4.372                          

 Hold time                                              -0.007       4.365                          

 Data required time                                                  4.365                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.365                          
 Data arrival time                                                   4.462                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.097                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/TS_CTRL[6]
Path Group  : phy_dq_sysclk_1
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.428  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.346
  Clock Pessimism Removal :  -0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.271       3.346         _N106            
 CLMS_279_361/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/CLK

 CLMS_279_361/CR0                  tco                   0.122       3.468 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/L5Q
                                   net (fanout=82)       0.220       3.688         debug_data[67]   
 CLMA_285_402/Y0                   td                    0.102       3.790 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/N659[6]/LUT6_inst_perm/L6
                                   net (fanout=2)        0.676       4.466         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdqs_en [6]
 TSERDES_299_308/TS_CTRL[6]                                                r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/TS_CTRL[6]

 Data arrival time                                                   4.466         Logic Levels: 1  
                                                                                   Logic: 0.224ns(20.000%), Route: 0.896ns(80.000%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 TSERDES_299_308/OCLKDIV                                                   r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/OCLKDIV
 clock pessimism                                        -0.159       3.822                          
 clock uncertainty                                       0.550       4.372                          

 Hold time                                              -0.007       4.365                          

 Data required time                                                  4.365                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.365                          
 Data arrival time                                                   4.466                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[23]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/TX_DATA[6]
Path Group  : phy_dq_sysclk_1
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.418  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.336
  Clock Pessimism Removal :  -0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.261       3.336         _N106            
 CLMS_267_409/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[23]/opit_0_inv_L6QQ_perm/CLK

 CLMS_267_409/CR0                  tco                   0.123       3.459 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[23]/opit_0_inv_L6QQ_perm/L6QQ
                                   net (fanout=8)        0.177       3.636         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r [23]
 CLMA_279_414/Y1                   td                    0.047       3.683 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[34]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.766       4.449         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdq [22]
 IOLHR_292_408/TX_DATA[6]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/TX_DATA[6]

 Data arrival time                                                   4.449         Logic Levels: 1  
                                                                                   Logic: 0.170ns(15.274%), Route: 0.943ns(84.726%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_408/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/OCLKDIV
 clock pessimism                                        -0.159       3.822                          
 clock uncertainty                                       0.550       4.372                          

 Hold time                                              -0.024       4.348                          

 Data required time                                                  4.348                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.348                          
 Data arrival time                                                   4.449                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[10]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.167  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.100
  Launch Clock Delay      :  2.490
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.312       2.490         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.141       2.631 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.454       3.085         free_clk_rst_n   
 CLMA_177_336/RSCO                 td                    0.052       3.137 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.137         ntR298           
 CLMA_177_342/RSCO                 td                    0.049       3.186 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.186         ntR297           
 CLMA_177_348/RSCO                 td                    0.049       3.235 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[31]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=5)        0.000       3.235         ntR296           
 CLMA_177_354/RSCO                 td                    0.049       3.284 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[31]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       3.284         ntR295           
 CLMA_177_360/RSCO                 td                    0.049       3.333 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_7[23]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.333         ntR294           
 CLMA_177_366/RSCO                 td                    0.049       3.382 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[15]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       3.382         ntR293           
 CLMA_177_372/RSCO                 td                    0.049       3.431 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[15]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.431         ntR292           
 CLMA_177_378/RSCO                 td                    0.049       3.480 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[27]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=3)        0.000       3.480         ntR291           
 CLMA_177_384/RSCO                 td                    0.049       3.529 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[28]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.529         ntR290           
 CLMA_177_390/RSCO                 td                    0.049       3.578 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_2[28]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       3.578         ntR289           
 CLMA_177_396/RSCO                 td                    0.049       3.627 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[28]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.627         ntR288           
 CLMA_177_402/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[10]/opit_0_inv/RS

 Data arrival time                                                   3.627         Logic Levels: 11 
                                                                                   Logic: 0.683ns(60.070%), Route: 0.454ns(39.930%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.246      42.100         _N111            
 CLMA_177_402/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[10]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.323                          
 clock uncertainty                                      -0.050      42.273                          

 Recovery time                                          -0.116      42.157                          

 Data required time                                                 42.157                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.157                          
 Data arrival time                                                   3.627                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.530                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[26]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.167  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.100
  Launch Clock Delay      :  2.490
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.312       2.490         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.141       2.631 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.454       3.085         free_clk_rst_n   
 CLMA_177_336/RSCO                 td                    0.052       3.137 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.137         ntR298           
 CLMA_177_342/RSCO                 td                    0.049       3.186 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.186         ntR297           
 CLMA_177_348/RSCO                 td                    0.049       3.235 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[31]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=5)        0.000       3.235         ntR296           
 CLMA_177_354/RSCO                 td                    0.049       3.284 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[31]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       3.284         ntR295           
 CLMA_177_360/RSCO                 td                    0.049       3.333 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_7[23]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.333         ntR294           
 CLMA_177_366/RSCO                 td                    0.049       3.382 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[15]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       3.382         ntR293           
 CLMA_177_372/RSCO                 td                    0.049       3.431 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[15]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.431         ntR292           
 CLMA_177_378/RSCO                 td                    0.049       3.480 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[27]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=3)        0.000       3.480         ntR291           
 CLMA_177_384/RSCO                 td                    0.049       3.529 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[28]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.529         ntR290           
 CLMA_177_390/RSCO                 td                    0.049       3.578 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_2[28]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       3.578         ntR289           
 CLMA_177_396/RSCO                 td                    0.049       3.627 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[28]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.627         ntR288           
 CLMA_177_402/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[26]/opit_0_inv/RS

 Data arrival time                                                   3.627         Logic Levels: 11 
                                                                                   Logic: 0.683ns(60.070%), Route: 0.454ns(39.930%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.246      42.100         _N111            
 CLMA_177_402/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[26]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.323                          
 clock uncertainty                                      -0.050      42.273                          

 Recovery time                                          -0.116      42.157                          

 Data required time                                                 42.157                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.157                          
 Data arrival time                                                   3.627                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.530                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[28]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.167  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.100
  Launch Clock Delay      :  2.490
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.312       2.490         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.141       2.631 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.454       3.085         free_clk_rst_n   
 CLMA_177_336/RSCO                 td                    0.052       3.137 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.137         ntR298           
 CLMA_177_342/RSCO                 td                    0.049       3.186 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[31]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.186         ntR297           
 CLMA_177_348/RSCO                 td                    0.049       3.235 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[31]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=5)        0.000       3.235         ntR296           
 CLMA_177_354/RSCO                 td                    0.049       3.284 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[31]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       3.284         ntR295           
 CLMA_177_360/RSCO                 td                    0.049       3.333 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_7[23]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.333         ntR294           
 CLMA_177_366/RSCO                 td                    0.049       3.382 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[15]/opit_0_inv/RSCO
                                   net (fanout=6)        0.000       3.382         ntR293           
 CLMA_177_372/RSCO                 td                    0.049       3.431 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[15]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.431         ntR292           
 CLMA_177_378/RSCO                 td                    0.049       3.480 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[27]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=3)        0.000       3.480         ntR291           
 CLMA_177_384/RSCO                 td                    0.049       3.529 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[28]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.529         ntR290           
 CLMA_177_390/RSCO                 td                    0.049       3.578 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_2[28]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       3.578         ntR289           
 CLMA_177_396/RSCO                 td                    0.049       3.627 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[28]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.627         ntR288           
 CLMA_177_402/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[28]/opit_0_inv/RS

 Data arrival time                                                   3.627         Logic Levels: 11 
                                                                                   Logic: 0.683ns(60.070%), Route: 0.454ns(39.930%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.246      42.100         _N111            
 CLMA_177_402/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[28]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.323                          
 clock uncertainty                                      -0.050      42.273                          

 Recovery time                                          -0.116      42.157                          

 Data required time                                                 42.157                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.157                          
 Data arrival time                                                   3.627                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.530                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[4]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.146  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.487
  Launch Clock Delay      :  2.118
  Clock Pessimism Removal :  -0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.264       2.118         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.123       2.241 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.222       2.463         free_clk_rst_n   
 CLMS_177_319/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[4]/opit_0_inv/RS

 Data arrival time                                                   2.463         Logic Levels: 0  
                                                                                   Logic: 0.123ns(35.652%), Route: 0.222ns(64.348%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.309       2.487         _N111            
 CLMS_177_319/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[4]/opit_0_inv/CLK
 clock pessimism                                        -0.223       2.264                          
 clock uncertainty                                       0.000       2.264                          

 Removal time                                           -0.038       2.226                          

 Data required time                                                  2.226                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.226                          
 Data arrival time                                                   2.463                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.237                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[7]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.146  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.487
  Launch Clock Delay      :  2.118
  Clock Pessimism Removal :  -0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.264       2.118         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.123       2.241 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.222       2.463         free_clk_rst_n   
 CLMS_177_319/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[7]/opit_0_inv/RS

 Data arrival time                                                   2.463         Logic Levels: 0  
                                                                                   Logic: 0.123ns(35.652%), Route: 0.222ns(64.348%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=386)      0.309       2.487         _N111            
 CLMS_177_319/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[7]/opit_0_inv/CLK
 clock pessimism                                        -0.223       2.264                          
 clock uncertainty                                       0.000       2.264                          

 Removal time                                           -0.038       2.226                          

 Data required time                                                  2.226                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.226                          
 Data arrival time                                                   2.463                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.237                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[16]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.014  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.489
  Launch Clock Delay      :  2.118
  Clock Pessimism Removal :  -0.357

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.264       2.118         _N109            
 CLMA_147_312/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_312/CR0                  tco                   0.123       2.241 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=177)      0.103       2.344         free_clk_rst_n   
 CLMA_147_318/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[16]/opit_0_inv/RS

 Data arrival time                                                   2.344         Logic Levels: 0  
                                                                                   Logic: 0.123ns(54.425%), Route: 0.103ns(45.575%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=157)      0.311       2.489         _N109            
 CLMA_147_318/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[16]/opit_0_inv/CLK
 clock pessimism                                        -0.357       2.132                          
 clock uncertainty                                       0.000       2.132                          

 Removal time                                           -0.038       2.094                          

 Data required time                                                  2.094                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.094                          
 Data arrival time                                                   2.344                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.250                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/RS
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.147  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.962
  Launch Clock Delay      :  3.552
  Clock Pessimism Removal :  0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.308       3.552         _N114            
 CLMA_213_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_213_235/CR0                  tco                   0.141       3.693 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=40)       0.898       4.591         I_ips_ddr_top/u_ddrphy_top/rst_seq_rstn
 CLMA_147_319/RSCO                 td                    0.052       4.643 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=1)        0.000       4.643         ntR543           
 CLMA_147_325/RSCI                                                         r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/RS

 Data arrival time                                                   4.643         Logic Levels: 1  
                                                                                   Logic: 0.193ns(17.690%), Route: 0.898ns(82.310%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.262      42.962         _N116            
 CLMA_147_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.443      43.405                          
 clock uncertainty                                      -0.150      43.255                          

 Recovery time                                          -0.116      43.139                          

 Data required time                                                 43.139                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.139                          
 Data arrival time                                                   4.643                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.496                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv/RS
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.035  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.973
  Launch Clock Delay      :  3.552
  Clock Pessimism Removal :  0.544

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.308       3.552         _N114            
 CLMA_213_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_213_235/CR0                  tco                   0.141       3.693 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=40)       1.031       4.724         I_ips_ddr_top/u_ddrphy_top/rst_seq_rstn
 CLMA_285_54/RS                                                            f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv/RS

 Data arrival time                                                   4.724         Logic Levels: 0  
                                                                                   Logic: 0.141ns(12.031%), Route: 1.031ns(87.969%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.273      42.973         _N114            
 CLMA_285_54/CLK                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv/CLK
 clock pessimism                                         0.544      43.517                          
 clock uncertainty                                      -0.150      43.367                          

 Recovery time                                          -0.072      43.295                          

 Data required time                                                 43.295                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.295                          
 Data arrival time                                                   4.724                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.571                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.146  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.963
  Launch Clock Delay      :  3.552
  Clock Pessimism Removal :  0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=21)       0.308       3.552         _N114            
 CLMA_213_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_213_235/CR0                  tco                   0.141       3.693 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=40)       0.898       4.591         I_ips_ddr_top/u_ddrphy_top/rst_seq_rstn
 CLMA_147_319/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   4.591         Logic Levels: 0  
                                                                                   Logic: 0.141ns(13.571%), Route: 0.898ns(86.429%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.263      42.963         _N116            
 CLMA_147_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                         0.443      43.406                          
 clock uncertainty                                      -0.150      43.256                          

 Recovery time                                          -0.072      43.184                          

 Data required time                                                 43.184                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.184                          
 Data arrival time                                                   4.591                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.593                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/ddrphy_cpd_start_d0/opit_0_inv_srl/RS
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.153  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.557
  Launch Clock Delay      :  2.961
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.261       2.961         _N116            
 CLMS_159_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_319/CR0                  tco                   0.123       3.084 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=61)       0.231       3.315         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_159_300/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/ddrphy_cpd_start_d0/opit_0_inv_srl/RS

 Data arrival time                                                   3.315         Logic Levels: 0  
                                                                                   Logic: 0.123ns(34.746%), Route: 0.231ns(65.254%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_171/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_8/CLKOUT
                                   net (fanout=6)        0.313       3.557         _N113            
 CLMA_159_300/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/ddrphy_cpd_start_d0/opit_0_inv_srl/CLK
 clock pessimism                                        -0.443       3.114                          
 clock uncertainty                                       0.000       3.114                          

 Removal time                                           -0.038       3.076                          

 Data required time                                                  3.076                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.076                          
 Data arrival time                                                   3.315                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.239                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[0]/opit_0_inv/RS
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.147  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.551
  Launch Clock Delay      :  2.961
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.261       2.961         _N116            
 CLMS_159_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_319/CR0                  tco                   0.123       3.084 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=61)       0.232       3.316         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_171_324/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[0]/opit_0_inv/RS

 Data arrival time                                                   3.316         Logic Levels: 0  
                                                                                   Logic: 0.123ns(34.648%), Route: 0.232ns(65.352%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=74)       0.307       3.551         _N115            
 CLMA_171_324/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[0]/opit_0_inv/CLK
 clock pessimism                                        -0.443       3.108                          
 clock uncertainty                                       0.000       3.108                          

 Removal time                                           -0.038       3.070                          

 Data required time                                                  3.070                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.070                          
 Data arrival time                                                   3.316                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.246                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.147  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.551
  Launch Clock Delay      :  2.961
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N117            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=62)       0.261       2.961         _N116            
 CLMS_159_319/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_319/CR0                  tco                   0.123       3.084 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=61)       0.232       3.316         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_171_324/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   3.316         Logic Levels: 0  
                                                                                   Logic: 0.123ns(34.648%), Route: 0.232ns(65.352%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N117            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=74)       0.307       3.551         _N115            
 CLMA_171_324/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                        -0.443       3.108                          
 clock uncertainty                                       0.000       3.108                          

 Removal time                                           -0.038       3.070                          

 Data required time                                                  3.070                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.070                          
 Data arrival time                                                   3.316                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.246                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.046  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.337
  Launch Clock Delay      :  4.427
  Clock Pessimism Removal :  1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.308       4.427         _N105            
 CLMA_243_205/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_243_205/CR0                  tco                   0.141       4.568 f       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=437)      0.597       5.165         I_ips_ddr_top/ddrc_rstn
 CLMS_177_193/RSCO                 td                    0.052       5.217 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[1]/opit_0_inv_32X2DL6Q/RSCO
                                   net (fanout=1)        0.000       5.217         ntR359           
 CLMS_177_199/RSCO                 td                    0.049       5.266 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[1]/opit_0_inv_32X2DL6Q/RSCO
                                   net (fanout=2)        0.000       5.266         ntR358           
 CLMS_177_205/RSCO                 td                    0.049       5.315 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       5.315         ntR357           
 CLMS_177_211/RSCO                 td                    0.049       5.364 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[17]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       5.364         ntR356           
 CLMS_177_217/RSCO                 td                    0.049       5.413 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[15]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       5.413         ntR355           
 CLMS_177_223/RSCO                 td                    0.049       5.462 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[25]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=1)        0.000       5.462         ntR354           
 CLMS_177_229/RSCO                 td                    0.049       5.511 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[25]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=1)        0.000       5.511         ntR353           
 CLMS_177_235/RSCO                 td                    0.049       5.560 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=2)        0.000       5.560         ntR352           
 CLMS_177_241/RSCO                 td                    0.049       5.609 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][2]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.609         ntR351           
 CLMS_177_247/RSCO                 td                    0.049       5.658 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L6QL5Q_perm/RSCO
                                   net (fanout=3)        0.000       5.658         ntR350           
 CLMS_177_253/RSCO                 td                    0.049       5.707 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][14]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.707         ntR349           
 CLMS_177_259/RSCO                 td                    0.049       5.756 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][14]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.756         ntR348           
 CLMS_177_265/RSCO                 td                    0.049       5.805 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][13]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       5.805         ntR347           
 CLMS_177_271/RSCO                 td                    0.049       5.854 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][14]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.854         ntR346           
 CLMS_177_277/RSCO                 td                    0.049       5.903 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=2)        0.000       5.903         ntR345           
 CLMS_177_283/RSCI                                                         r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   5.903         Logic Levels: 15 
                                                                                   Logic: 0.879ns(59.553%), Route: 0.597ns(40.447%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.262      10.956         _N105            
 CLMS_177_283/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                         1.044      12.000                          
 clock uncertainty                                      -0.150      11.850                          

 Recovery time                                          -0.116      11.734                          

 Data required time                                                 11.734                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.734                          
 Data arrival time                                                   5.903                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         5.831                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.046  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.337
  Launch Clock Delay      :  4.427
  Clock Pessimism Removal :  1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.308       4.427         _N105            
 CLMA_243_205/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_243_205/CR0                  tco                   0.141       4.568 f       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=437)      0.597       5.165         I_ips_ddr_top/ddrc_rstn
 CLMS_177_193/RSCO                 td                    0.052       5.217 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[1]/opit_0_inv_32X2DL6Q/RSCO
                                   net (fanout=1)        0.000       5.217         ntR359           
 CLMS_177_199/RSCO                 td                    0.049       5.266 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[1]/opit_0_inv_32X2DL6Q/RSCO
                                   net (fanout=2)        0.000       5.266         ntR358           
 CLMS_177_205/RSCO                 td                    0.049       5.315 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       5.315         ntR357           
 CLMS_177_211/RSCO                 td                    0.049       5.364 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[17]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       5.364         ntR356           
 CLMS_177_217/RSCO                 td                    0.049       5.413 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[15]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=3)        0.000       5.413         ntR355           
 CLMS_177_223/RSCO                 td                    0.049       5.462 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[25]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=1)        0.000       5.462         ntR354           
 CLMS_177_229/RSCO                 td                    0.049       5.511 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[25]/opit_0_inv_32X2DL6QL5Q/RSCO
                                   net (fanout=1)        0.000       5.511         ntR353           
 CLMS_177_235/RSCO                 td                    0.049       5.560 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=2)        0.000       5.560         ntR352           
 CLMS_177_241/RSCO                 td                    0.049       5.609 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][2]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.609         ntR351           
 CLMS_177_247/RSCO                 td                    0.049       5.658 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L6QL5Q_perm/RSCO
                                   net (fanout=3)        0.000       5.658         ntR350           
 CLMS_177_253/RSCO                 td                    0.049       5.707 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][14]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.707         ntR349           
 CLMS_177_259/RSCO                 td                    0.049       5.756 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][14]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.756         ntR348           
 CLMS_177_265/RSCO                 td                    0.049       5.805 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][13]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       5.805         ntR347           
 CLMS_177_271/RSCO                 td                    0.049       5.854 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][14]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.854         ntR346           
 CLMS_177_277/RSCO                 td                    0.049       5.903 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=2)        0.000       5.903         ntR345           
 CLMS_177_283/RSCI                                                         r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm/RS

 Data arrival time                                                   5.903         Logic Levels: 15 
                                                                                   Logic: 0.879ns(59.553%), Route: 0.597ns(40.447%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.262      10.956         _N105            
 CLMS_177_283/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm/CLK
 clock pessimism                                         1.044      12.000                          
 clock uncertainty                                      -0.150      11.850                          

 Recovery time                                          -0.116      11.734                          

 Data required time                                                 11.734                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.734                          
 Data arrival time                                                   5.903                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         5.831                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][7]/opit_0_inv/RS
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.147  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.337
  Launch Clock Delay      :  4.427
  Clock Pessimism Removal :  0.943

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.308       4.427         _N105            
 CLMA_243_205/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_243_205/CR0                  tco                   0.141       4.568 f       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=437)      0.678       5.246         I_ips_ddr_top/ddrc_rstn
 CLMA_159_216/RSCO                 td                    0.052       5.298 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[24]/opit_0_inv/RSCO
                                   net (fanout=5)        0.000       5.298         ntR409           
 CLMA_159_222/RSCO                 td                    0.049       5.347 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[25]/opit_0_inv/RSCO
                                   net (fanout=7)        0.000       5.347         ntR408           
 CLMA_159_228/RSCO                 td                    0.049       5.396 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[51]/opit_0_inv/RSCO
                                   net (fanout=7)        0.000       5.396         ntR407           
 CLMA_159_234/RSCO                 td                    0.049       5.445 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[15]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.445         ntR406           
 CLMA_159_240/RSCO                 td                    0.049       5.494 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[25]/opit_0_inv_L6QL5Q_perm/RSCO
                                   net (fanout=3)        0.000       5.494         ntR405           
 CLMA_159_246/RSCO                 td                    0.049       5.543 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][11]/opit_0_inv/RSCO
                                   net (fanout=5)        0.000       5.543         ntR404           
 CLMA_159_252/RSCO                 td                    0.049       5.592 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][11]/opit_0_inv/RSCO
                                   net (fanout=7)        0.000       5.592         ntR403           
 CLMA_159_258/RSCO                 td                    0.049       5.641 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[50]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.641         ntR402           
 CLMA_159_264/RSCO                 td                    0.049       5.690 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[47]/opit_0_inv_L7Q_perm/RSCO
                                   net (fanout=2)        0.000       5.690         ntR401           
 CLMA_159_270/RSCO                 td                    0.049       5.739 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[48]/opit_0_inv_L7Q_perm/RSCO
                                   net (fanout=2)        0.000       5.739         ntR400           
 CLMA_159_276/RSCO                 td                    0.049       5.788 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][8]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.788         ntR399           
 CLMA_159_282/RSCI                                                         r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][7]/opit_0_inv/RS

 Data arrival time                                                   5.788         Logic Levels: 11 
                                                                                   Logic: 0.683ns(50.184%), Route: 0.678ns(49.816%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_160/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_2/CLKOUT
                                   net (fanout=246)      0.262      10.956         _N107            
 CLMA_159_282/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][7]/opit_0_inv/CLK
 clock pessimism                                         0.943      11.899                          
 clock uncertainty                                      -0.150      11.749                          

 Recovery time                                          -0.116      11.633                          

 Data required time                                                 11.633                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.633                          
 Data arrival time                                                   5.788                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         5.845                          
====================================================================================================

====================================================================================================

Startpoint  : u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK
Endpoint    : u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[25]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.151  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.431
  Launch Clock Delay      :  3.337
  Clock Pessimism Removal :  -0.943

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.262       3.337         _N106            
 CLMA_171_307/CLK                                                          r       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK

 CLMA_171_307/CR0                  tco                   0.123       3.460 f       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/L6QQ
                                   net (fanout=512)      0.166       3.626         core_clk_rst_n   
 CLMA_171_300/RS                                                           f       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[25]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   3.626         Logic Levels: 0  
                                                                                   Logic: 0.123ns(42.561%), Route: 0.166ns(57.439%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.312       4.431         _N105            
 CLMA_171_300/CLK                                                          r       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[25]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                        -0.943       3.488                          
 clock uncertainty                                       0.000       3.488                          

 Removal time                                           -0.038       3.450                          

 Data required time                                                  3.450                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.450                          
 Data arrival time                                                   3.626                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.176                          
====================================================================================================

====================================================================================================

Startpoint  : u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK
Endpoint    : u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[104]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.151  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.431
  Launch Clock Delay      :  3.337
  Clock Pessimism Removal :  -0.943

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.262       3.337         _N106            
 CLMA_171_307/CLK                                                          r       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK

 CLMA_171_307/CR0                  tco                   0.123       3.460 f       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/L6QQ
                                   net (fanout=512)      0.166       3.626         core_clk_rst_n   
 CLMA_171_300/RS                                                           f       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[104]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   3.626         Logic Levels: 0  
                                                                                   Logic: 0.123ns(42.561%), Route: 0.166ns(57.439%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.312       4.431         _N105            
 CLMA_171_300/CLK                                                          r       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[104]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                        -0.943       3.488                          
 clock uncertainty                                       0.000       3.488                          

 Removal time                                           -0.038       3.450                          

 Data required time                                                  3.450                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.450                          
 Data arrival time                                                   3.626                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.176                          
====================================================================================================

====================================================================================================

Startpoint  : u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK
Endpoint    : u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[105]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.151  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.431
  Launch Clock Delay      :  3.337
  Clock Pessimism Removal :  -0.943

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1617)     0.262       3.337         _N106            
 CLMA_171_307/CLK                                                          r       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK

 CLMA_171_307/CR0                  tco                   0.123       3.460 f       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/L6QQ
                                   net (fanout=512)      0.166       3.626         core_clk_rst_n   
 CLMA_171_300/RS                                                           f       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[105]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   3.626         Logic Levels: 0  
                                                                                   Logic: 0.123ns(42.561%), Route: 0.166ns(57.439%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.312       4.431         _N105            
 CLMA_171_300/CLK                                                          r       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[105]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                        -0.943       3.488                          
 clock uncertainty                                       0.000       3.488                          

 Removal time                                           -0.038       3.450                          

 Data required time                                                  3.450                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.450                          
 Data arrival time                                                   3.626                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.176                          
====================================================================================================

====================================================================================================

Startpoint  : u_axi_bist_top/u_test_rd_ctrl/err_flag_led/opit_0_inv_L5Q_perm/CLK
Endpoint    : err_flag_led (port)
Path Group  : **default**
Path Type   : max (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.328       4.447         _N105            
 CLMA_261_301/CLK                                                          r       u_axi_bist_top/u_test_rd_ctrl/err_flag_led/opit_0_inv_L5Q_perm/CLK

 CLMA_261_301/CR3                  tco                   0.140       4.587 f       u_axi_bist_top/u_test_rd_ctrl/err_flag_led/opit_0_inv_L5Q_perm/L5Q
                                   net (fanout=36)       0.743       5.330         err_flag         
 CLMS_159_289/CR3                  td                    0.167       5.497 f       u_axi_bist_top/u_test_rd_ctrl/execute_rd_cnt[0]/opit_0_inv_L6Q_LUT6DQL5_perm/L5
                                   net (fanout=1)        1.557       7.054         nt_err_flag_led  
 IOLHR_16_606/DO_P                 td                    0.353       7.407 f       err_flag_led_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000       7.407         err_flag_led_obuf/ntO
 IOBS_0_606/PAD                    td                    1.098       8.505 f       err_flag_led_obuf/opit_0/O
                                   net (fanout=1)        0.039       8.544         err_flag_led     
 J16                                                                       f       err_flag_led (port)

 Data arrival time                                                   8.544         Logic Levels: 3  
                                                                                   Logic: 1.758ns(42.909%), Route: 2.339ns(57.091%)
====================================================================================================

====================================================================================================

Startpoint  : heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/CLK
Endpoint    : heart_beat_led (port)
Path Group  : **default**
Path Type   : max (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1728)     0.308       4.427         _N105            
 CLMA_201_246/CLK                                                          r       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/CLK

 CLMA_201_246/Q0                   tco                   0.125       4.552 f       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/L6Q
                                   net (fanout=3)        1.076       5.628         nt_heart_beat_led
 IOLHR_16_306/DO_P                 td                    0.353       5.981 f       heart_beat_led_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000       5.981         heart_beat_led_obuf/ntO
 IOBS_0_306/PAD                    td                    1.098       7.079 f       heart_beat_led_obuf/opit_0/O
                                   net (fanout=1)        0.053       7.132         heart_beat_led   
 M17                                                                       f       heart_beat_led (port)

 Data arrival time                                                   7.132         Logic Levels: 2  
                                                                                   Logic: 1.576ns(58.262%), Route: 1.129ns(41.738%)
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/CLK
Endpoint    : mem_rst_n (port)
Path Group  : **default**
Path Type   : max (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_160/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_2/CLKOUT
                                   net (fanout=246)      0.307       4.426         _N107            
 CLMA_147_252/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/CLK

 CLMA_147_252/CR3                  tco                   0.140       4.566 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/L6QQ
                                   net (fanout=1)        0.930       5.496         I_ips_ddr_top/u_ddrphy_top/calib_rst
 CLMA_285_289/Y0                   td                    0.122       5.618 f       u_axi_bist_top/u_test_rd_ctrl/axi_rdata_d1[0]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=1)        0.249       5.867         nt_mem_rst_n     
 IOLHR_292_300/DO_P                td                    0.353       6.220 f       mem_rst_n_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000       6.220         mem_rst_n_obuf/ntO
 IOBS_300_300/PAD                  td                    0.753       6.973 f       mem_rst_n_obuf/opit_0/O
                                   net (fanout=1)        0.092       7.065         mem_rst_n        
 T3                                                                        f       mem_rst_n (port) 

 Data arrival time                                                   7.065         Logic Levels: 3  
                                                                                   Logic: 1.368ns(51.838%), Route: 1.271ns(48.162%)
====================================================================================================

====================================================================================================

Startpoint  : uart_rxd (port)
Endpoint    : u_ips2l_uart_ctrl/u_uart_top/u_ips2l_seu_uart_rx/rxd_d[0]/opit_0_inv_srl/D
Path Group  : **default**
Path Type   : min (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 M16                                                     0.000       0.000 r       uart_rxd (port)  
                                   net (fanout=1)        0.052       0.052         uart_rxd         
 IOBS_0_312/DIN                    td                    0.445       0.497 r       uart_rxd_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.497         uart_rxd_ibuf/ntD
 IOLHR_16_312/DI_TO_CLK            td                    0.073       0.570 r       uart_rxd_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=1)        0.603       1.173         nt_uart_rxd      
 CLMA_147_337/M3                                                           r       u_ips2l_uart_ctrl/u_uart_top/u_ips2l_seu_uart_rx/rxd_d[0]/opit_0_inv_srl/D

 Data arrival time                                                   1.173         Logic Levels: 2  
                                                                                   Logic: 0.518ns(44.160%), Route: 0.655ns(55.840%)
====================================================================================================

====================================================================================================

Startpoint  : rst_board (port)
Endpoint    : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/RS
Path Group  : **default**
Path Type   : min (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 M15                                                     0.000       0.000 f       rst_board (port) 
                                   net (fanout=1)        0.052       0.052         rst_board        
 IOBD_0_318/DIN                    td                    0.515       0.567 f       rst_board_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.567         rst_board_ibuf/ntD
 IOLHR_16_318/DI_TO_CLK            td                    0.073       0.640 f       rst_board_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=2)        0.578       1.218         nt_rst_board     
 CLMA_147_312/RS                                                           f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/RS

 Data arrival time                                                   1.218         Logic Levels: 2  
                                                                                   Logic: 0.588ns(48.276%), Route: 0.630ns(51.724%)
====================================================================================================

====================================================================================================

Startpoint  : mem_dq[5] (port)
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L6Q_perm/I2
Path Group  : **default**
Path Type   : min (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 P1                                                      0.000       0.000 r       mem_dq[5] (port) 
                                   net (fanout=1)        0.103       0.103         nt_mem_dq[5]     
 IOBS_300_360/DIN                  td                    0.479       0.582 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_0/O
                                   net (fanout=1)        0.000       0.582         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/ntI
 IOLHR_292_360/DI_TO_CLK           td                    0.516       1.098 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/DI_TO_CLK
                                   net (fanout=2)        0.164       1.262         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_in_dly [5]
 CLMA_285_355/A2                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L6Q_perm/I2

 Data arrival time                                                   1.262         Logic Levels: 2  
                                                                                   Logic: 0.995ns(78.843%), Route: 0.267ns(21.157%)
====================================================================================================

{ref_clk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 19.800      20.000          0.200           High Pulse Width  CLMA_147_432/CLK        u_adc_ctrl/dbg_temp_rd_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_147_432/CLK        u_adc_ctrl/dbg_temp_rd_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           High Pulse Width  CLMA_147_432/CLK        u_adc_ctrl/dbg_temp_rd_pos_d[1]/opit_0_inv/CLK
====================================================================================================

{rst_clk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 19.800      20.000          0.200           High Pulse Width  CLMA_201_288/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_201_288/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_171_360/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[0]/opit_0_inv_L5Q_perm/CLK
====================================================================================================

{ddrphy_sysclk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 3.609       3.809           0.200           High Pulse Width  CLMA_243_205/CLK        I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
 3.609       3.809           0.200           High Pulse Width  CLMA_261_241/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_calib_mux/calib_address[0]/opit_0_inv_L6Q_perm/CLK
 3.609       3.809           0.200           High Pulse Width  CLMA_273_246/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_calib_mux/calib_address[1]/opit_0_inv_L6Q_perm/CLK
====================================================================================================

{phy_dq_clk_0} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 0.011       0.476           0.465           High Pulse Width  DDR_PHY_297_159/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst/CLKA
 0.011       0.476           0.465           Low Pulse Width   DDR_PHY_297_159/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst/CLKA
 0.011       0.476           0.465           High Pulse Width  TSERDES_299_159/SERCLK  I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_tserdes_ca0/oserdes_inst/SERCLK
====================================================================================================

{phy_dq_sysclk_0} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 1.659       3.809           2.150           Low Pulse Width   DDRPHY_CPD_297_4/PPLL_SYSCLK
                                                                                       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
 1.660       3.810           2.150           High Pulse Width  DDRPHY_CPD_297_4/PPLL_SYSCLK
                                                                                       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
 2.209       3.809           1.600           Low Pulse Width   TSERDES_299_159/OCLKDIV I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_tserdes_ca0/oserdes_inst/OCLKDIV
====================================================================================================

{phy_dq_clk_1} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 0.011       0.476           0.465           High Pulse Width  DDR_PHY_297_307/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY/CLKA
 0.011       0.476           0.465           Low Pulse Width   DDR_PHY_297_307/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY/CLKA
 0.011       0.476           0.465           Low Pulse Width   TSERDES_299_308/SERCLK  I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/SERCLK
====================================================================================================

{phy_dq_sysclk_1} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_318/ICLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_318/OCLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/OCLKDIV
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_324/ICLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV
====================================================================================================

====================================================================================================

Inputs and Outputs :
+--------------------------------------------------------------------------------------------------+
| Type       | File Name                                                                          
+--------------------------------------------------------------------------------------------------+
| Input      | D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/place_route/test_ddr_pnr.adf       
| Output     | D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/report_timing/test_ddr_rtp.adf     
|            | D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/report_timing/test_ddr.rtr         
|            | D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/report_timing/rtr.db               
+--------------------------------------------------------------------------------------------------+


Flow Command: report_timing 
Peak memory: 1,117 MB
Total CPU time to report_timing completion : 0h:0m:4s
Process Total CPU time to report_timing completion : 0h:0m:5s
Total real time to report_timing completion : 0h:0m:12s
