IP Generator (Version 2022.2-SP6.4 build 146967)
Check out license ...
Start generating at 2025-10-12 12:18
Instance: pcie_test (D:\DMYWdownloadsoftware\PDS\project\project_bs\PCIe_LC\pcie_dma_test\ipcore\pcie_test\pcie_test.idf)
IP: Pango PCI Express (1.8)
Part: Logos2-PG2L50H-FBG484--6
Create directory 'example_design' ...
Create directory 'example_design\bench' ...
Create directory 'example_design\rtl' ...
Create directory 'example_design\rtl\pcie_cfg_ctrl' ...
Create directory 'example_design\rtl\pcie_cfg_ctrl\rtl' ...
Create directory 'example_design\rtl\pcie_dma_ctrl' ...
Create directory 'example_design\rtl\pcie_dma_ctrl\fifo' ...
Create directory 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_ram' ...
Create directory 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_ram\rtl' ...
Create directory 'example_design\rtl\uart2apb_32bit' ...
Create directory 'example_design\rtl\uart2apb_32bit\fifo' ...
Create directory 'pnr' ...
Create directory 'pnr\core_only' ...
Create directory 'pnr\example_design' ...
Create directory 'rtl' ...
Create directory 'rtl\external_ram' ...
Create directory 'rtl\external_ram\rcv_data_ram' ...
Create directory 'rtl\external_ram\rcv_data_ram\rtl' ...
Create directory 'rtl\external_ram\rcv_header_ram' ...
Create directory 'rtl\external_ram\rcv_header_ram\rtl' ...
Create directory 'rtl\external_ram\retry_data_ram' ...
Create directory 'rtl\external_ram\retry_data_ram\rtl' ...
Create directory 'rtl\hsst_pipe' ...
Create directory 'rtl\hsstlp' ...
Create directory 'rtl\hsstlp\rtl' ...
Create directory 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Create directory 'sim' ...
Create directory 'sim\modelsim' ...
Create directory 'sim_lib' ...
Create directory 'sim_lib\modelsim' ...
Copy 'example_design\bench\pango_pcie_top_tb.v.xml' to 'example_design\bench' ...
Copy 'example_design\bench\pango_pcie_top.v.xml' to 'example_design\bench' ...
Copy 'example_design\bench\pango_pcie_top_sim.v.xml' to 'example_design\bench' ...
Copy 'example_design\bench\ips2l_pcie_wrap_v1_8_sim.v.xml' to 'example_design\bench' ...
Copy 'example_design\rtl\pcie_cfg_ctrl\rtl\pcie_cfg_ctrl.v' to 'example_design\rtl\pcie_cfg_ctrl\rtl' ...
Copy 'example_design\rtl\pcie_cfg_ctrl\rtl\pcie_cfg_ctrl_apb.v' to 'example_design\rtl\pcie_cfg_ctrl\rtl' ...
Copy 'example_design\rtl\pcie_cfg_ctrl\rtl\pcie_cfg_trans.v' to 'example_design\rtl\pcie_cfg_ctrl\rtl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\fifo\ipm_distributed_sdpram_v1_2_distributed_fifo.v' to 'example_design\rtl\pcie_dma_ctrl\fifo' ...
Copy 'example_design\rtl\pcie_dma_ctrl\fifo\pgs_pciex4_fifo_ctrl.v' to 'example_design\rtl\pcie_dma_ctrl\fifo' ...
Copy 'example_design\rtl\pcie_dma_ctrl\fifo\pgs_pciex4_fifo_v1_2.v' to 'example_design\rtl\pcie_dma_ctrl\fifo' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_ram\ips2l_pcie_dma_ram.v' to 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_ram' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_ram\rtl\ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v' to 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_ram\rtl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_ram\rtl\ips2l_pcie_dma_ram_init_param.v' to 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_ram\rtl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_ram\rtl\ips2l_pcie_dma_ram_Reset_Value.v' to 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_ram\rtl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ipm_distributed_sdpram_v1_2.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_expd_apb_mux.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_controller.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_cpld_tx_ctrl.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_mrd_tx_ctrl.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_mwr_tx_ctrl.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_rd_ctrl.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_rx_cpld_wr_ctrl.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_rx_mwr_wr_ctrl.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_rx_top.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_tlp_rcv.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_tlp_tx_mux.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_tx_cpld_rd_ctrl.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_tx_mwr_rd_ctrl.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_tx_top.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_dma_wr_ctrl.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\ips2l_pcie_reg.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\pcie_dma_ctrl\pgs_pciex4_prefetch_fifo_v1_2.v' to 'example_design\rtl\pcie_dma_ctrl' ...
Copy 'example_design\rtl\uart2apb_32bit\pgr_apb_ctr_32bit.v' to 'example_design\rtl\uart2apb_32bit' ...
Copy 'example_design\rtl\uart2apb_32bit\pgr_apb_mif_32bit.v' to 'example_design\rtl\uart2apb_32bit' ...
Copy 'example_design\rtl\uart2apb_32bit\pgr_clk_gen_32bit.v' to 'example_design\rtl\uart2apb_32bit' ...
Copy 'example_design\rtl\uart2apb_32bit\pgr_cmd_parser_32bit.v' to 'example_design\rtl\uart2apb_32bit' ...
Copy 'example_design\rtl\uart2apb_32bit\pgr_fifo_top_32bit.v' to 'example_design\rtl\uart2apb_32bit' ...
Copy 'example_design\rtl\uart2apb_32bit\pgr_uart2apb_top_32bit.v' to 'example_design\rtl\uart2apb_32bit' ...
Copy 'example_design\rtl\uart2apb_32bit\pgr_uart_rx_32bit.v' to 'example_design\rtl\uart2apb_32bit' ...
Copy 'example_design\rtl\uart2apb_32bit\pgr_uart_top_32bit.v' to 'example_design\rtl\uart2apb_32bit' ...
Copy 'example_design\rtl\uart2apb_32bit\pgr_uart_tx_32bit.v' to 'example_design\rtl\uart2apb_32bit' ...
Copy 'example_design\rtl\uart2apb_32bit\rstn_sync_32bit.v' to 'example_design\rtl\uart2apb_32bit' ...
Copy 'example_design\rtl\uart2apb_32bit\fifo\pgm_distributed_fifo_ctr_v1_0.v' to 'example_design\rtl\uart2apb_32bit\fifo' ...
Copy 'example_design\rtl\uart2apb_32bit\fifo\pgm_distributed_fifo_v1_1.v' to 'example_design\rtl\uart2apb_32bit\fifo' ...
Copy 'example_design\rtl\uart2apb_32bit\fifo\pgm_distributed_sdpram_v1_1.v' to 'example_design\rtl\uart2apb_32bit\fifo' ...
Copy 'example_design\rtl\uart2apb_32bit\fifo\pgr_prefetch_fifo.v' to 'example_design\rtl\uart2apb_32bit\fifo' ...
Copy 'pnr\core_only' to 'pnr' ...
Copy 'pnr\example_design' to 'pnr' ...
Copy 'rtl\ips2l_pcie_apb2dbi_v1_1.v' to 'rtl' ...
Copy 'rtl\ips2l_pcie_apb_cross_v1_0.v' to 'rtl' ...
Copy 'rtl\ips2l_pcie_apb_mux_v1_0.v' to 'rtl' ...
Copy 'rtl\ips2l_pcie_cfg_init_v1_7.v' to 'rtl' ...
Copy 'rtl\ips2l_pcie_hard_ctrl_v1_8.v' to 'rtl' ...
Copy 'rtl\ips2l_pcie_pll_v1_0.v' to 'rtl' ...
Copy 'rtl\ips2l_pcie_seio_intf_v1_2.v' to 'rtl' ...
Copy 'rtl\ips2l_pcie_soft_phy_v1_3.v' to 'rtl' ...
Copy 'rtl\ips2l_pcie_top_v1_8.v' to 'rtl' ...
Copy 'rtl\external_ram\rcv_data_ram\rcv_data_ram.v' to 'rtl\external_ram\rcv_data_ram' ...
Copy 'rtl\external_ram\rcv_data_ram\rtl\ipm2l_sdpram_v1_0_rcv_data_ram.v' to 'rtl\external_ram\rcv_data_ram\rtl' ...
Copy 'rtl\external_ram\rcv_data_ram\rtl\rcv_data_ram_init_param.v' to 'rtl\external_ram\rcv_data_ram\rtl' ...
Copy 'rtl\external_ram\rcv_data_ram\rtl\rcv_data_ram_Reset_Value.v' to 'rtl\external_ram\rcv_data_ram\rtl' ...
Copy 'rtl\external_ram\rcv_header_ram\rcv_header_ram.v' to 'rtl\external_ram\rcv_header_ram' ...
Copy 'rtl\external_ram\rcv_header_ram\rtl\ipm2l_sdpram_v1_0_rcv_header_ram.v' to 'rtl\external_ram\rcv_header_ram\rtl' ...
Copy 'rtl\external_ram\rcv_header_ram\rtl\rcv_header_ram_init_param.v' to 'rtl\external_ram\rcv_header_ram\rtl' ...
Copy 'rtl\external_ram\rcv_header_ram\rtl\rcv_header_ram_Reset_Value.v' to 'rtl\external_ram\rcv_header_ram\rtl' ...
Copy 'rtl\external_ram\retry_data_ram\retry_data_ram.v' to 'rtl\external_ram\retry_data_ram' ...
Copy 'rtl\external_ram\retry_data_ram\rtl\ipm2l_spram_v1_0_retry_data_ram.v' to 'rtl\external_ram\retry_data_ram\rtl' ...
Copy 'rtl\external_ram\retry_data_ram\rtl\retry_data_ram_init_param.v' to 'rtl\external_ram\retry_data_ram\rtl' ...
Copy 'rtl\external_ram\retry_data_ram\rtl\retry_data_ram_Reset_Value.v' to 'rtl\external_ram\retry_data_ram\rtl' ...
Copy 'rtl\hsst_pipe\hsst_rst_cross_sync_v1_0.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\hsst_rst_debounce_v1_0.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\hsst_rst_sync_v1_0.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\hsst_rst_wtchdg_v1_0.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\hsstl_phy_mac_rdata_proc.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\hsstl_rst4mcrsw_rx_init_v1_0.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\hsstl_rst4mcrsw_rx_rst_fsm_v1_0.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\hsstl_rst4mcrsw_rx_v1_0.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\hsstl_rst4mcrsw_tx_rst_fsm_v1_1.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\hsstl_rst4mcrsw_tx_v1_0.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\hsstl_rst4mcrsw_v1_0.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsst_pipe\ips_hsst_rst_sync_v1_0.v' to 'rtl\hsst_pipe' ...
Copy 'rtl\hsstlp\ipm2l_pcie_hsstlp_x1_top.v.xml' to 'rtl\hsstlp' ...
Copy 'rtl\hsstlp\ipm2l_pcie_hsstlp_x2_top.v.xml' to 'rtl\hsstlp' ...
Copy 'rtl\hsstlp\ipm2l_pcie_hsstlp_x4_top.v.xml' to 'rtl\hsstlp' ...
Copy 'rtl\hsstlp\rtl\ipm2l_pcie_hsstlp_apb_bridge_v1_2.v' to 'rtl\hsstlp\rtl' ...
Copy 'rtl\hsstlp\rtl\ipm2l_pcie_hsstlp_wrapper_v1_6.v' to 'rtl\hsstlp\rtl' ...
Copy 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst\ipm2l_hsstlp_fifo_clr_v1_3.v' to 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Copy 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst\ipm2l_hsstlp_pll_rst_fsm_v1_0.v' to 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Copy 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst\ipm2l_hsstlp_rst_debounce_v1_0.v' to 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Copy 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst\ipm2l_hsstlp_rst_pll_v1_0.v' to 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Copy 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst\ipm2l_hsstlp_rst_rx_v1_6.v' to 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Copy 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst\ipm2l_hsstlp_rst_sync_v1_0.v' to 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Copy 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst\ipm2l_hsstlp_rst_tx_v1_6.v' to 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Copy 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst\ipm2l_hsstlp_rst_v1_6.v' to 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Copy 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst\ipm2l_hsstlp_rst_wtchdg_v1_0.v' to 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Copy 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst\ipm2l_hsstlp_rxlane_rst_fsm_v1_6.v' to 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Copy 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst\ipm2l_hsstlp_txlane_rst_fsm_v1_6.v' to 'rtl\hsstlp\rtl\ipm2l_hsstlp_rst' ...
Copy 'sim\modelsim' to 'sim' ...
Copy 'sim_lib\modelsim' to 'sim_lib' ...
Copy 'readme.txt' ...
Copy 'ips2l_pcie_wrap_v1_8.v.xml' ...
Compile file 'ips2l_pcie_wrap_v1_8.v.xml' to 'pcie_test.v' ...
Found top module 'pcie_test' in file 'pcie_test.v'.
Compile file 'rtl\hsstlp\ipm2l_pcie_hsstlp_x1_top.v.xml' to 'rtl\hsstlp\ipm2l_pcie_hsstlp_x1_top.v' ...
Compile file 'rtl\hsstlp\ipm2l_pcie_hsstlp_x2_top.v.xml' to 'rtl\hsstlp\ipm2l_pcie_hsstlp_x2_top.v' ...
Compile file 'rtl\hsstlp\ipm2l_pcie_hsstlp_x4_top.v.xml' to 'rtl\hsstlp\ipm2l_pcie_hsstlp_x4_top.v' ...
Compile file 'example_design\bench\pango_pcie_top_tb.v.xml' to 'example_design\bench\pango_pcie_top_tb.v' ...
Compile file 'example_design\bench\pango_pcie_top.v.xml' to 'example_design\bench\pango_pcie_top.v' ...
Compile file 'example_design\bench\pango_pcie_top_sim.v.xml' to 'example_design\bench\pango_pcie_top_sim.v' ...
Compile file 'example_design\bench\ips2l_pcie_wrap_v1_8_sim.v.xml' to 'example_design\bench\ips2l_pcie_wrap_v1_8_sim.v' ...
Run file 'createFiles.tcl' ...
Create template file 'pcie_test_tmpl.v' ...
Create template file 'pcie_test_tmpl.vhdl' ...
There are 45 source files to synthesize.
Synthesis is disabled.
Done: 0 error(s), 0 warning(s)
