#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: E:\PDS_FPGA\PDS_2022.2-SP6.4\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.26100
#Hostname: 傻额宁儿
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Fri Nov  7 01:15:35 2025
License checkout: fabric_ads from E:\PDS_FPGA\PDS_2022.2-SP6.4\new_pds_F4A80DA47D72.lic
Compiling verification operator library.
Loading technology operator library.
Compiling technology operator library.
Compiling technology operator (valence) library.
W: Flow-4058: The device information PGL50H-6FBG484 of IP 'E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/read_ddr_fifo.idf' is not the same as the current project.
W: Flow-4058: The device information PGL50H-6FBG484 of IP 'E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/write_ddr_fifo.idf' is not the same as the current project.
W: Flow-4058: The device information PGL50H-6FBG484 of IP 'E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/eth_pkt_fifo.idf' is not the same as the current project.
W: Flow-4058: The device information PGL50H-6FBG484 of IP 'E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/hdmi_pcie_fifo.idf' is not the same as the current project.
I: Enable Verilog2k features and keywords
Start rtl-analyze.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_ctr_32bit.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_ctr_32bit.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_ctr_32bit.v(line number: 6)] Analyzing module pgr_apb_ctr_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_ctr_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_mif_32bit.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_mif_32bit.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_mif_32bit.v(line number: 6)] Analyzing module pgr_apb_mif_32bit (library work)
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_mif_32bit.v(line number: 111)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_mif_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_clk_gen_32bit.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_clk_gen_32bit.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_clk_gen_32bit.v(line number: 6)] Analyzing module pgr_clk_gen_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_clk_gen_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_cmd_parser_32bit.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_cmd_parser_32bit.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_cmd_parser_32bit.v(line number: 6)] Analyzing module pgr_cmd_parser_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_cmd_parser_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_fifo_top_32bit.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_fifo_top_32bit.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_fifo_top_32bit.v(line number: 6)] Analyzing module pgr_fifo_top_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_fifo_top_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_rx_32bit.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_rx_32bit.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_rx_32bit.v(line number: 6)] Analyzing module pgr_uart_rx_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_rx_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_top_32bit.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_top_32bit.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_top_32bit.v(line number: 6)] Analyzing module pgr_uart_top_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_top_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_tx_32bit.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_tx_32bit.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_tx_32bit.v(line number: 6)] Analyzing module pgr_uart_tx_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_tx_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart2apb_top_32bit.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart2apb_top_32bit.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart2apb_top_32bit.v(line number: 6)] Analyzing module pgr_uart2apb_top_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart2apb_top_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_ctr_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_ctr_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_ctr_v1_0.v(line number: 18)] Analyzing module pgm_distributed_fifo_ctr_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_ctr_v1_0.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_v1_1.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_v1_1.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_v1_1.v(line number: 18)] Analyzing module pgm_distributed_fifo_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_v1_1.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_sdpram_v1_1.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_sdpram_v1_1.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_sdpram_v1_1.v(line number: 22)] Analyzing module pgm_distributed_sdpram_v1_1 (library work)
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_sdpram_v1_1.v(line number: 31)] Convert attribute name from syn_ramstyle to PAP_RAM_STYLE
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_sdpram_v1_1.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgr_prefetch_fifo.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgr_prefetch_fifo.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgr_prefetch_fifo.v(line number: 8)] Analyzing module pgr_prefetch_fifo (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgr_prefetch_fifo.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ipm_distributed_sdpram_v1_2.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ipm_distributed_sdpram_v1_2.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ipm_distributed_sdpram_v1_2.v(line number: 18)] Analyzing module ipm_distributed_sdpram_v1_2 (library work)
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ipm_distributed_sdpram_v1_2.v(line number: 27)] Convert attribute name from syn_ramstyle to PAP_RAM_STYLE
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ipm_distributed_sdpram_v1_2.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_expd_apb_mux.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_expd_apb_mux.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_expd_apb_mux.v(line number: 11)] Analyzing module ips2l_expd_apb_mux (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_expd_apb_mux.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma.v(line number: 15)] Analyzing module ips2l_pcie_dma (library work)
W: Verilog-2015: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma.v(line number: 153)] bar0_rd_clk_en is already declared in this scope
W: Verilog-2015: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma.v(line number: 154)] bar0_rd_addr is already declared in this scope
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_controller.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_controller.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_controller.v(line number: 15)] Analyzing module ips2l_pcie_dma_controller (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_controller.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_cpld_tx_ctrl.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_cpld_tx_ctrl.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_cpld_tx_ctrl.v(line number: 15)] Analyzing module ips2l_pcie_dma_cpld_tx_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_cpld_tx_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mrd_tx_ctrl.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mrd_tx_ctrl.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mrd_tx_ctrl.v(line number: 15)] Analyzing module ips2l_pcie_dma_mrd_tx_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mrd_tx_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mwr_tx_ctrl.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mwr_tx_ctrl.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mwr_tx_ctrl.v(line number: 15)] Analyzing module ips2l_pcie_dma_mwr_tx_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mwr_tx_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rd_ctrl.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rd_ctrl.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rd_ctrl.v(line number: 15)] Analyzing module ips2l_pcie_dma_rd_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rd_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_cpld_wr_ctrl.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_cpld_wr_ctrl.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_cpld_wr_ctrl.v(line number: 15)] Analyzing module ips2l_pcie_dma_rx_cpld_wr_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_cpld_wr_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_mwr_wr_ctrl.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_mwr_wr_ctrl.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_mwr_wr_ctrl.v(line number: 15)] Analyzing module ips2l_pcie_dma_rx_mwr_wr_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_mwr_wr_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_top.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_top.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_top.v(line number: 15)] Analyzing module ips2l_pcie_dma_rx_top (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_top.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tlp_rcv.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tlp_rcv.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tlp_rcv.v(line number: 15)] Analyzing module ips2l_pcie_dma_tlp_rcv (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tlp_rcv.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tlp_tx_mux.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tlp_tx_mux.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tlp_tx_mux.v(line number: 15)] Analyzing module ips2l_pcie_dma_tlp_tx_mux (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tlp_tx_mux.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_cpld_rd_ctrl.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_cpld_rd_ctrl.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_cpld_rd_ctrl.v(line number: 15)] Analyzing module ips2l_pcie_dma_tx_cpld_rd_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_cpld_rd_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_mwr_rd_ctrl.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_mwr_rd_ctrl.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_mwr_rd_ctrl.v(line number: 15)] Analyzing module ips2l_pcie_dma_tx_mwr_rd_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_mwr_rd_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v(line number: 15)] Analyzing module ips2l_pcie_dma_tx_top (library work)
W: Verilog-2015: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v(line number: 116)] cpld_last_data is already declared in this scope
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_wr_ctrl.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_wr_ctrl.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_wr_ctrl.v(line number: 15)] Analyzing module ips2l_pcie_dma_wr_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_wr_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/pgs_pciex4_prefetch_fifo_v1_2.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/pgs_pciex4_prefetch_fifo_v1_2.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/pgs_pciex4_prefetch_fifo_v1_2.v(line number: 8)] Analyzing module pgs_pciex4_prefetch_fifo_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/pgs_pciex4_prefetch_fifo_v1_2.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_ctrl.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_ctrl.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_ctrl.v(line number: 8)] Analyzing module pgs_pciex4_fifo_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_v1_2.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_v1_2.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_v1_2.v(line number: 8)] Analyzing module pgs_pciex4_fifo_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_v1_2.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/ips2l_pcie_dma_ram.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/ips2l_pcie_dma_ram.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/ips2l_pcie_dma_ram.v(line number: 18)] Analyzing module ips2l_pcie_dma_ram (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/ips2l_pcie_dma_ram.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/ipm_distributed_sdpram_v1_2_distributed_fifo.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/ipm_distributed_sdpram_v1_2_distributed_fifo.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/ipm_distributed_sdpram_v1_2_distributed_fifo.v(line number: 22)] Analyzing module ipm_distributed_sdpram_v1_2_distributed_fifo (library work)
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/ipm_distributed_sdpram_v1_2_distributed_fifo.v(line number: 31)] Convert attribute name from syn_ramstyle to PAP_RAM_STYLE
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/ipm_distributed_sdpram_v1_2_distributed_fifo.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 20)] Analyzing module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram (library work)
I: Found Verilog include file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ips2l_pcie_dma_ram_init_param.v
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 292)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 293)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 296)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 300)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 304)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 308)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 316)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 317)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 320)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 321)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 324)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 325)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 328)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 329)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 332)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 333)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 336)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 337)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 340)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 341)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 344)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 345)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 348)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 349)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 352)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 353)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 356)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 357)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 360)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 361)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 364)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 365)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 368)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 369)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 373)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 374)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 377)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 378)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 382)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 383)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 386)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 387)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 390)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 391)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 396)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 397)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 400)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 401)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 406)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 407)] Ignore 'system task' $finish
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 9)] Analyzing module pcie_dma_test (library work)
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 93)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 95)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 97)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 127)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave.v
I: Found Verilog include file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave_define.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave.v(line number: 43)] Analyzing module i2cSlave (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave.v successfully.
W: Public-4030: File 'F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave_define.v' has been added. It is skipped.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave_define.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave_define.v
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave_define.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v
I: Found Verilog include file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave_define.v
W: Public-4030: File 'F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave_define.v' has been added. It is skipped.
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number: 43)] Analyzing module registerInterface (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/serialInterface.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/serialInterface.v
I: Found Verilog include file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/timescale.v
I: Found Verilog include file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave_define.v
W: Public-4030: File 'F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave_define.v' has been added. It is skipped.
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/serialInterface.v(line number: 53)] Analyzing module serialInterface (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/serialInterface.v successfully.
W: Public-4030: File 'F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/timescale.v' has been added. It is skipped.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/timescale.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/timescale.v
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/timescale.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/cmos_8_16bit.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/cmos_8_16bit.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/cmos_8_16bit.v(line number: 12)] Analyzing module cmos_8_16bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/cmos_8_16bit.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/i2c_com.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/i2c_com.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/i2c_com.v(line number: 21)] Analyzing module i2c_com (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/i2c_com.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/power_on_delay.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/power_on_delay.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/power_on_delay.v(line number: 22)] Analyzing module power_on_delay (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/power_on_delay.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 22)] Analyzing module reg_config (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/SXT/rgb565_to_rgb888.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/SXT/rgb565_to_rgb888.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/SXT/rgb565_to_rgb888.v(line number: 1)] Analyzing module rgb565_to_rgb888 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/SXT/rgb565_to_rgb888.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m.v(line number: 2)] Analyzing module AXI_FULL_M (library work)
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m.v(line number: 54)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 1)] Analyzing module axi_m_arbitration (library work)
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 84)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 85)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 86)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 87)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 94)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 95)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 96)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 97)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 98)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 99)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 100)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 101)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 102)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/rw_fifo_ctrl.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/rw_fifo_ctrl.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/rw_fifo_ctrl.v(line number: 1)] Analyzing module rw_fifo_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/rw_fifo_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/eth_img_rec.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/eth_img_rec.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/eth_img_rec.v(line number: 1)] Analyzing module eth_img_rec (library work)
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/eth_img_rec.v(line number: 17)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/eth_img_rec.v(line number: 18)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/eth_img_rec.v(line number: 19)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/eth_img_rec.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/pcie_dma_ctrl.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/pcie_dma_ctrl.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/pcie_dma_ctrl.v(line number: 1)] Analyzing module pcie_dma_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/pcie_dma_ctrl.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_cross_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_cross_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_cross_v1_0.v(line number: 11)] Analyzing module ips2l_pcie_apb_cross_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_cross_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_mux_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_mux_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_mux_v1_0.v(line number: 11)] Analyzing module ips2l_pcie_apb_mux_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_mux_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb2dbi_v1_1.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb2dbi_v1_1.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb2dbi_v1_1.v(line number: 11)] Analyzing module ips2l_pcie_apb2dbi_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb2dbi_v1_1.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_cfg_init_v1_7.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_cfg_init_v1_7.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_cfg_init_v1_7.v(line number: 11)] Analyzing module ips2l_pcie_cfg_init_v1_7 (library work)
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_cfg_init_v1_7.v(line number: 125)] Convert attribute name from syn_romstyle to PAP_RAM_STYLE
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_cfg_init_v1_7.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v(line number: 11)] Analyzing module ips2l_pcie_hard_ctrl_v1_8 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_pll_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_pll_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_pll_v1_0.v(line number: 21)] Analyzing module ips2l_pcie_pll_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_pll_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 11)] Analyzing module ips2l_pcie_soft_phy_v1_3 (library work)
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 70)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 71)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 72)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 73)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 74)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 76)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 96)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 97)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_top_v1_8.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_top_v1_8.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_top_v1_8.v(line number: 11)] Analyzing module ips2l_pcie_top_v1_8 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_top_v1_8.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_seio_intf_v1_2.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_seio_intf_v1_2.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_seio_intf_v1_2.v(line number: 11)] Analyzing module ips2l_pcie_seio_intf_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_seio_intf_v1_2.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rcv_data_ram.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rcv_data_ram.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rcv_data_ram.v(line number: 18)] Analyzing module rcv_data_ram (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rcv_data_ram.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 20)] Analyzing module ipm2l_sdpram_v1_0_rcv_data_ram (library work)
I: Found Verilog include file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/rcv_data_ram_init_param.v
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 292)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 293)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 296)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 300)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 304)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 308)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 316)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 317)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 320)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 321)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 324)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 325)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 328)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 329)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 332)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 333)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 336)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 337)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 340)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 341)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 344)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 345)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 348)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 349)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 352)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 353)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 356)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 357)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 361)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 362)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 365)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 366)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 370)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 371)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 374)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 375)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 378)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 379)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 382)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 383)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 386)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 387)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 390)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 391)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 394)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 395)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 398)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 399)] Ignore 'system task' $finish
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rcv_header_ram.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rcv_header_ram.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rcv_header_ram.v(line number: 18)] Analyzing module rcv_header_ram (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rcv_header_ram.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 20)] Analyzing module ipm2l_sdpram_v1_0_rcv_header_ram (library work)
I: Found Verilog include file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/rcv_header_ram_init_param.v
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 292)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 293)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 296)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 300)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 304)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 308)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 316)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 317)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 320)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 321)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 324)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 325)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 328)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 329)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 332)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 333)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 336)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 337)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 340)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 341)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 344)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 345)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 348)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 349)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 352)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 353)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 356)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 357)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 361)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 362)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 365)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 366)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 370)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 371)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 374)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 375)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 378)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 379)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 382)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 383)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 386)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 387)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 390)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 391)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 394)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 395)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 398)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 399)] Ignore 'system task' $finish
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/retry_data_ram.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/retry_data_ram.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/retry_data_ram.v(line number: 18)] Analyzing module retry_data_ram (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/retry_data_ram.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 19)] Analyzing module ipm2l_spram_v1_0_retry_data_ram (library work)
I: Found Verilog include file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/retry_data_ram_init_param.v
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 124)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 128)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 136)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 137)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 140)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 141)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 144)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 145)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 148)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 149)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 152)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 153)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 156)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 157)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 160)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 161)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 164)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 165)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 168)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 169)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 172)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 173)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 176)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 177)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 181)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 182)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 185)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 186)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 190)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 191)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 194)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 195)] Ignore 'system task' $finish
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_cross_sync_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_cross_sync_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_cross_sync_v1_0.v(line number: 6)] Analyzing module hsst_rst_cross_sync_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_cross_sync_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_debounce_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_debounce_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_debounce_v1_0.v(line number: 6)] Analyzing module hsst_rst_debounce_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_debounce_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Analyzing module hsst_rst_sync_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_wtchdg_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_wtchdg_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_wtchdg_v1_0.v(line number: 6)] Analyzing module hsst_rst_wtchdg_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_wtchdg_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_phy_mac_rdata_proc.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_phy_mac_rdata_proc.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_phy_mac_rdata_proc.v(line number: 6)] Analyzing module hsstl_phy_mac_rdata_proc (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_phy_mac_rdata_proc.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v(line number: 6)] Analyzing module hsstl_rst4mcrsw_rx_init_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_fsm_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_fsm_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_fsm_v1_0.v(line number: 6)] Analyzing module hsstl_rst4mcrsw_rx_rst_fsm_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_fsm_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v(line number: 6)] Analyzing module hsstl_rst4mcrsw_rx_rst_initfsm_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v(line number: 6)] Analyzing module hsstl_rst4mcrsw_rx_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_rst_fsm_v1_1.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_rst_fsm_v1_1.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_rst_fsm_v1_1.v(line number: 6)] Analyzing module hsstl_rst4mcrsw_tx_rst_fsm_v1_1 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_rst_fsm_v1_1.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v(line number: 6)] Analyzing module hsstl_rst4mcrsw_tx_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v(line number: 6)] Analyzing module hsstl_rst4mcrsw_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/ips_hsst_rst_sync_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/ips_hsst_rst_sync_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/ips_hsst_rst_sync_v1_0.v(line number: 6)] Analyzing module ips_hsst_rst_sync_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/ips_hsst_rst_sync_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x1_top.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x1_top.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x1_top.v(line number: 19)] Analyzing module ipm2l_pcie_hsstlp_x1_top (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x1_top.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v(line number: 19)] Analyzing module ipm2l_pcie_hsstlp_x2_top (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x4_top.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x4_top.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x4_top.v(line number: 19)] Analyzing module ipm2l_pcie_hsstlp_x4_top (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x4_top.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_apb_bridge_v1_2.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_apb_bridge_v1_2.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_apb_bridge_v1_2.v(line number: 17)] Analyzing module ipm2l_hsstlp_apb_bridge_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_apb_bridge_v1_2.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v(line number: 17)] Analyzing module ipm2l_hsstlp_wrapper_v1_6 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_fifo_clr_v1_3.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_fifo_clr_v1_3.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_fifo_clr_v1_3.v(line number: 16)] Analyzing module ipm2l_hsstlp_fifo_clr_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_fifo_clr_v1_3.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_pll_rst_fsm_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_pll_rst_fsm_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_pll_rst_fsm_v1_0.v(line number: 16)] Analyzing module ipm2l_hsstlp_pll_rst_fsm_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_pll_rst_fsm_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_debounce_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_debounce_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_debounce_v1_0.v(line number: 16)] Analyzing module ipm2l_hsstlp_rst_debounce_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_debounce_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_pll_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_pll_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_pll_v1_0.v(line number: 16)] Analyzing module ipm2l_hsstlp_rst_pll_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_pll_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_rx_v1_6.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_rx_v1_6.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_rx_v1_6.v(line number: 16)] Analyzing module ipm2l_hsstlp_rst_rx_v1_6 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_rx_v1_6.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_sync_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_sync_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_sync_v1_0.v(line number: 16)] Analyzing module ipm2l_hsstlp_rst_sync_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_sync_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_tx_v1_6.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_tx_v1_6.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_tx_v1_6.v(line number: 16)] Analyzing module ipm2l_hsstlp_rst_tx_v1_6 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_tx_v1_6.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_v1_6.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_v1_6.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_v1_6.v(line number: 16)] Analyzing module ipm2l_hsstlp_rst_v1_6 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_v1_6.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_wtchdg_v1_0.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_wtchdg_v1_0.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_wtchdg_v1_0.v(line number: 16)] Analyzing module ipm2l_hsstlp_rst_wtchdg_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_wtchdg_v1_0.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rxlane_rst_fsm_v1_6.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rxlane_rst_fsm_v1_6.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rxlane_rst_fsm_v1_6.v(line number: 16)] Analyzing module ipm2l_hsstlp_rxlane_rst_fsm_v1_6 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rxlane_rst_fsm_v1_6.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_txlane_rst_fsm_v1_6.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_txlane_rst_fsm_v1_6.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_txlane_rst_fsm_v1_6.v(line number: 16)] Analyzing module ipm2l_hsstlp_txlane_rst_fsm_v1_6 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_txlane_rst_fsm_v1_6.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/pcie_test.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/pcie_test.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/pcie_test.v(line number: 16)] Analyzing module pcie_test (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/pcie_test.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/PLL/PLL.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/PLL/PLL.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/PLL/PLL.v(line number: 18)] Analyzing module PLL (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/PLL/PLL.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Analyzing module ips2l_rst_sync_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp(line number: 183)] Analyzing module ips2l_ddrphy_wrlvl_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 495)] Analyzing module ips2l_ddrphy_wrcal_v1_7 (library work)
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 514)] Convert attribute name from syn_preserve to PAP_PRESERVE
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 515)] Convert attribute name from syn_preserve to PAP_PRESERVE
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp(line number: 232)] Analyzing module ips2l_ddrphy_wdata_path_adj_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp(line number: 151)] Analyzing module ips2l_ddrphy_upcal_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp(line number: 83)] Analyzing module ips2l_ddrphy_training_ctrl_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp(line number: 108)] Analyzing module ips2l_ddrphy_slice_rddata_align_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 268)] Analyzing module ips2l_ddrphy_reset_ctrl_v1_3 (library work)
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 298)] Convert attribute name from syn_preserve to PAP_PRESERVE
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp(line number: 750)] Analyzing module ips2l_ddrphy_rdcal_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp(line number: 196)] Analyzing module ips2l_ddrphy_main_ctrl_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp(line number: 577)] Analyzing module ips2l_ddrphy_init_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp(line number: 174)] Analyzing module ips2l_ddrphy_info_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp(line number: 243)] Analyzing module ips2l_ddrphy_gatecal_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp(line number: 100)] Analyzing module ips2l_ddrphy_gate_update_ctrl_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp(line number: 228)] Analyzing module ips2l_ddrphy_eyecal_v1_5 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp(line number: 112)] Analyzing module ips2l_ddrphy_drift_ctrl_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp(line number: 395)] Analyzing module ips2l_ddrphy_dqsi_rdel_cal_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp(line number: 527)] Analyzing module ips2l_ddrphy_dqs_rddata_align_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp(line number: 173)] Analyzing module ips2l_ddrphy_dqs_gate_coarse_cal_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp(line number: 124)] Analyzing module ips2l_ddrphy_dll_update_ctrl_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp(line number: 320)] Analyzing module ips2l_ddrphy_dfi_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp(line number: 69)] Analyzing module ips2l_ddrphy_gpll_phase_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp(line number: 292)] Analyzing module ips2l_ddrphy_data_slice_wrlvl_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 278)] Analyzing module ips2l_ddrphy_data_slice_wrcal_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 583)] Analyzing module ips2l_ddrphy_data_slice_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp(line number: 111)] Analyzing module ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp(line number: 182)] Analyzing module ips2l_ddrphy_cpd_ctrl_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp(line number: 71)] Analyzing module ips2l_ddrphy_cpd_lock_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp(line number: 134)] Analyzing module ips2l_ddrphy_control_path_adj_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 392)] Analyzing module ips2l_ddrphy_calib_top_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp(line number: 199)] Analyzing module ips2l_ddrphy_calib_mux_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp(line number: 84)] Analyzing module ips2l_ddrphy_rst_debounce_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp(line number: 104)] Analyzing module ips2l_ddrphy_rst_clk_phase_adj_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 127)] Analyzing module ips2l_ddrphy_gpll_v1_3 (library work)
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 154)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 155)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 156)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 157)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 158)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 242)] Analyzing module ips2l_ddrphy_ppll_v1_0 (library work)
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 261)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 262)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 263)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 264)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 265)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp(line number: 145)] Analyzing module ips2l_mcdq_apb_cross_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp(line number: 101)] Analyzing module ips2l_mcdq_calib_delay_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp(line number: 559)] Analyzing module ips2l_mcdq_cfg_apb_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp(line number: 243)] Analyzing module ips2l_mcdq_dcd_bm_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp(line number: 76)] Analyzing module ips2l_mcdq_dcd_rowaddr_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp(line number: 209)] Analyzing module ips2l_mcdq_dcd_sm_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp(line number: 174)] Analyzing module ips2l_mcdq_dcd_top_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 643)] Analyzing module ips2l_mcdq_dcp_back_ctrl_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp(line number: 298)] Analyzing module ips2l_mcdq_dcp_buf_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp(line number: 210)] Analyzing module ips2l_mcdq_dcp_out_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp(line number: 329)] Analyzing module ips2l_mcdq_dcp_top_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp(line number: 432)] Analyzing module ips2l_mcdq_dfi_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp(line number: 315)] Analyzing module ips2l_mcdq_lp_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp(line number: 321)] Analyzing module ips2l_mcdq_mrs_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp(line number: 95)] Analyzing module ips2l_mcdq_prefetch_fifo_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp(line number: 83)] Analyzing module ips2l_mcdq_rdatapath_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp(line number: 78)] Analyzing module ips2l_mcdq_reg_fifo2_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp(line number: 271)] Analyzing module ips2l_mcdq_ui_axi_v1_2a (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp(line number: 171)] Analyzing module ips2l_mcdq_wdatapath_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp(line number: 140)] Analyzing module ips2l_mcdq_wdp_align_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp(line number: 133)] Analyzing module ips2l_mcdq_wdp_dcp_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 619)] Analyzing module ips2l_mcdq_wrapper_v1_2b (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Analyzing module ips2l_mcdq_com_timing_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp(line number: 128)] Analyzing module ips2l_mcdq_tfaw_timing_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp(line number: 68)] Analyzing module ips2l_mcdq_tfaw_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp(line number: 115)] Analyzing module ips2l_mcdq_timing_act2wr_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp(line number: 92)] Analyzing module ips2l_mcdq_timing_act_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Analyzing module ips2l_mcdq_timing_pre_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp(line number: 128)] Analyzing module ips2l_mcdq_timing_rd_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp(line number: 90)] Analyzing module ips2l_mcdq_timing_ref_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp(line number: 127)] Analyzing module ips2l_mcdq_timing_wr_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Analyzing module ips2l_mcdq_trc_timing_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 130)] Analyzing module ips2l_distributed_fifo_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp(line number: 269)] Analyzing module ips2l_distributed_fifo_ctr_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 130)] Analyzing module ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 120)] Analyzing module ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0 (library work)
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 129)] Convert attribute name from syn_ramstyle to PAP_RAM_STYLE
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3.v(line number: 12)] Analyzing module ddr3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 12)] Analyzing module ddr3_ddrphy_top (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 12)] Analyzing module ddr3_slice_top_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v(line number: 18)] Analyzing module ipm2l_fifo_ctrl_v1_1_SXT1_FIFO (library work)
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v(line number: 46)] Convert attribute name from syn_preserve to PAP_PRESERVE
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v(line number: 48)] Convert attribute name from syn_preserve to PAP_PRESERVE
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v(line number: 59)] Convert attribute name from syn_preserve to PAP_PRESERVE
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v(line number: 61)] Convert attribute name from syn_preserve to PAP_PRESERVE
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 18)] Analyzing module ipm2l_sdpram_v1_10_SXT1_FIFO (library work)
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 349)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 350)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 353)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 357)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 361)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 365)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 373)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 374)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 377)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 378)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 381)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 382)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 385)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 386)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 389)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 390)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 393)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 394)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 397)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 398)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 401)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 402)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 405)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 406)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 409)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 410)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 413)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 414)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 417)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 418)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 421)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 422)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 425)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 426)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 429)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 430)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 433)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 434)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 437)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 438)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 442)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 443)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 446)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 447)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 451)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 452)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 457)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 458)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 461)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 462)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 465)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 466)] Ignore 'system task' $finish
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 471)] Ignore 'system task' $display
W: Verilog-2008: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 472)] Ignore 'system task' $finish
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_v1_10_SXT1_FIFO.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_v1_10_SXT1_FIFO.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_v1_10_SXT1_FIFO.v(line number: 19)] Analyzing module ipm2l_fifo_v1_10_SXT1_FIFO (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_v1_10_SXT1_FIFO.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/SXT1_FIFO.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/SXT1_FIFO.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/SXT1_FIFO.v(line number: 16)] Analyzing module SXT1_FIFO (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/SXT1_FIFO.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_ctrl_v1_3.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_ctrl_v1_3.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_ctrl_v1_3.v(line number: 21)] Analyzing module ipml_fifo_ctrl_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_ctrl_v1_3.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 20)] Analyzing module ipml_sdpram_v1_6_read_ddr_fifo (library work)
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 309)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 310)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 313)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 317)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 321)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 325)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 329)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 330)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 333)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 334)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 337)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 338)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 341)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 342)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 345)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 346)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 349)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 350)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 353)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 354)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 357)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 358)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 361)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 362)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 365)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 366)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 369)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 370)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 374)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 375)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 378)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 379)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 383)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 384)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 387)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 388)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 391)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 392)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 395)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 396)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 399)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 400)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 405)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 406)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 409)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 410)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 415)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 416)] Ignore 'system task' $finish
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_v1_6_read_ddr_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_v1_6_read_ddr_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_v1_6_read_ddr_fifo.v(line number: 25)] Analyzing module ipml_fifo_v1_6_read_ddr_fifo (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_v1_6_read_ddr_fifo.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/read_ddr_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/read_ddr_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/read_ddr_fifo.v(line number: 18)] Analyzing module read_ddr_fifo (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/read_ddr_fifo.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/hdmi_pcie_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/hdmi_pcie_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/hdmi_pcie_fifo.v(line number: 18)] Analyzing module hdmi_pcie_fifo (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/hdmi_pcie_fifo.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 20)] Analyzing module ipml_sdpram_v1_6_write_ddr_fifo (library work)
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 309)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 310)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 313)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 317)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 321)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 325)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 329)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 330)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 333)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 334)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 337)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 338)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 341)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 342)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 345)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 346)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 349)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 350)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 353)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 354)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 357)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 358)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 361)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 362)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 365)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 366)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 369)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 370)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 374)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 375)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 378)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 379)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 383)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 384)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 387)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 388)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 391)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 392)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 395)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 396)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 399)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 400)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 405)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 406)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 409)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 410)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 415)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 416)] Ignore 'system task' $finish
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_fifo_v1_6_write_ddr_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_fifo_v1_6_write_ddr_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_fifo_v1_6_write_ddr_fifo.v(line number: 25)] Analyzing module ipml_fifo_v1_6_write_ddr_fifo (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_fifo_v1_6_write_ddr_fifo.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/write_ddr_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/write_ddr_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/write_ddr_fifo.v(line number: 18)] Analyzing module write_ddr_fifo (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/write_ddr_fifo.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_fifo_v1_6_hdmi_pcie_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_fifo_v1_6_hdmi_pcie_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_fifo_v1_6_hdmi_pcie_fifo.v(line number: 25)] Analyzing module ipml_fifo_v1_6_hdmi_pcie_fifo (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_fifo_v1_6_hdmi_pcie_fifo.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 20)] Analyzing module ipml_sdpram_v1_6_eth_pkt_fifo (library work)
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 308)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 309)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 312)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 316)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 320)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 324)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 328)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 329)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 332)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 333)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 336)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 337)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 340)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 341)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 344)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 345)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 348)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 349)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 352)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 353)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 356)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 357)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 360)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 361)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 364)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 365)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 368)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 369)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 373)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 374)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 377)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 378)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 382)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 383)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 386)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 387)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 390)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 391)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 394)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 395)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 398)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 399)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 404)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 405)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 408)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 409)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 414)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v(line number: 415)] Ignore 'system task' $finish
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_sdpram_v1_6_eth_pkt_fifo.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_fifo_v1_6_eth_pkt_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_fifo_v1_6_eth_pkt_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_fifo_v1_6_eth_pkt_fifo.v(line number: 25)] Analyzing module ipml_fifo_v1_6_eth_pkt_fifo (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/rtl/ipml_fifo_v1_6_eth_pkt_fifo.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/eth_pkt_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/eth_pkt_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/eth_pkt_fifo.v(line number: 18)] Analyzing module eth_pkt_fifo (library work)
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/eth_pkt_fifo/eth_pkt_fifo.v successfully.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v
I: Verilog-0001: Analyzing file E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v
I: Verilog-0002: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 20)] Analyzing module ipml_sdpram_v1_6_hdmi_pcie_fifo (library work)
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 308)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 309)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 312)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 316)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 320)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 324)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 328)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 329)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 332)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 333)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 336)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 337)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 340)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 341)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 344)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 345)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 348)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 349)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 352)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 353)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 356)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 357)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 360)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 361)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 364)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 365)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 368)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 369)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 373)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 374)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 377)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 378)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 382)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 383)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 386)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 387)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 390)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 391)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 394)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 395)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 398)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 399)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 404)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 405)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 408)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 409)] Ignore 'system task' $finish
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 414)] Ignore 'system task' $display
W: Verilog-2008: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v(line number: 415)] Ignore 'system task' $finish
Parsing done.
Executing : .rtl_analyze -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test} E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/hdmi_pcie_fifo/rtl/ipml_sdpram_v1_6_hdmi_pcie_fifo.v successfully.
I: Module "pcie_dma_test" is set as top module.
Executing : rtl-analyze successfully. Time elapsed: 2.796s wall, 0.391s user + 0.078s system = 0.469s CPU (16.8%)

Start rtl-elaborate.
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 9)] Elaborating module pcie_dma_test
I: Module instance {pcie_dma_test} parameter value:
    VIDEO_LENGTH = 32'b00000000000000000000011110000000
    VIDEO_HIGTH = 32'b00000000000000000000010000111000
    ZOOM_VIDEO_LENGTH = 32'b00000000000000000000001111000000
    ZOOM_VIDEO_HIGTH = 32'b00000000000000000000001000011100
    PIXEL_WIDTH = 32'b00000000000000000000000000100000
    MEM_ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    MEM_BADDR_WIDTH = 32'b00000000000000000000000000000011
    M_AXI_BRUST_LEN = 32'b00000000000000000000000000001000
    RW_ADDR_MIN = 20'b00000000000000000000
    RW_ADDR_MAX = 32'b00000000000011111101001000000000
    BOARD_MAC = 48'b000000000001000100100010001100110100010001010101
    BOARD_IP = 32'b11000000101010000000000100001010
    DES_MAC = 48'b010110000001000100100010100100010011100000110001
    TH_1S = 27'b001111101111000101001000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 196)] Elaborating instance my_PLL
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/PLL/PLL.v(line number: 18)] Elaborating module PLL
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/PLL/PLL.v(line number: 302)] Elaborating instance u_gpll
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 208)] Elaborating instance power_on_delay_inst
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/power_on_delay.v(line number: 22)] Elaborating module power_on_delay
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 218)] Elaborating instance coms1_reg_config
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 22)] Elaborating module reg_config
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 40)] Elaborating instance u1
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/i2c_com.v(line number: 21)] Elaborating module i2c_com
W: Verilog-2048: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/i2c_com.v(line number: 51)] Zero-extending on all bits z values may cause simulation mismatch.
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 230)] Elaborating instance coms2_reg_config
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 22)] Elaborating module reg_config
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 250)] Elaborating instance cmos1_8_16bit
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/cmos_8_16bit.v(line number: 12)] Elaborating module cmos_8_16bit
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 269)] Elaborating instance cmos2_8_16bit
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/cmos_8_16bit.v(line number: 12)] Elaborating module cmos_8_16bit
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 356)] Elaborating instance u_rgb565_to_rgb888
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/SXT/rgb565_to_rgb888.v(line number: 1)] Elaborating module rgb565_to_rgb888
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Elaborating instance user_axi_m_arbitration
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 1)] Elaborating module axi_m_arbitration
I: Module instance {pcie_dma_test/user_axi_m_arbitration} parameter value:
    VIDEO_LENGTH = 32'b00000000000000000000011110000000
    VIDEO_HIGTH = 32'b00000000000000000000010000111000
    ZOOM_VIDEO_LENGTH = 32'b00000000000000000000001111000000
    ZOOM_VIDEO_HIGTH = 32'b00000000000000000000001000011100
    PIXEL_WIDTH = 32'b00000000000000000000000000100000
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    DQ_WIDTH = 32'b00000000000000000000000000010000
    M_AXI_BRUST_LEN = 32'b00000000000000000000000000001000
    VIDEO0_BASE_ADDR = 2'b00
    VIDEO1_BASE_ADDR = 2'b01
    VIDEO2_BASE_ADDR = 2'b10
    VIDEO3_BASE_ADDR = 2'b11
    M0_WRITE = 2'b00
    M1_WRITE = 2'b01
    M2_WRITE = 2'b10
    M3_WRITE = 2'b11
    READ_ARBITRATION = 3'b000
    M0_READ = 3'b001
    M1_READ = 3'b010
    M2_READ = 3'b011
    M3_READ = 3'b100
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 450)] Elaborating instance u_axi_full_m0
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m.v(line number: 2)] Elaborating module AXI_FULL_M
I: Module instance {pcie_dma_test/user_axi_m_arbitration/u_axi_full_m0} parameter value:
    VIDEO_LENGTH = 32'b00000000000000000000001111000000
    VIDEO_HIGTH = 32'b00000000000000000000001000011100
    PIXEL_WIDTH = 32'b00000000000000000000000000100000
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    DQ_WIDTH = 32'b00000000000000000000000000010000
    M_AXI_BRUST_LEN = 32'b00000000000000000000000000001000
    VIDEO_BASE_ADDR = 32'b00000000000000000000000000000000
    IDLE = 32'b00000000000000000000000000000000
    WRITE_START = 32'b00000000000000000000000000000001
    WRITE_ADDR = 32'b00000000000000000000000000000010
    WRITE_DATA = 32'b00000000000000000000000000000011
    READ_START = 32'b00000000000000000000000000000001
    READ_ADDR = 32'b00000000000000000000000000000010
    READ_DATA = 32'b00000000000000000000000000000011
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 499)] Elaborating instance u_axi_full_m1
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m.v(line number: 2)] Elaborating module AXI_FULL_M
I: Module instance {pcie_dma_test/user_axi_m_arbitration/u_axi_full_m1} parameter value:
    VIDEO_LENGTH = 32'b00000000000000000000001111000000
    VIDEO_HIGTH = 32'b00000000000000000000001000011100
    PIXEL_WIDTH = 32'b00000000000000000000000000100000
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    DQ_WIDTH = 32'b00000000000000000000000000010000
    M_AXI_BRUST_LEN = 32'b00000000000000000000000000001000
    VIDEO_BASE_ADDR = 32'b00000000000000000000000000000001
    IDLE = 32'b00000000000000000000000000000000
    WRITE_START = 32'b00000000000000000000000000000001
    WRITE_ADDR = 32'b00000000000000000000000000000010
    WRITE_DATA = 32'b00000000000000000000000000000011
    READ_START = 32'b00000000000000000000000000000001
    READ_ADDR = 32'b00000000000000000000000000000010
    READ_DATA = 32'b00000000000000000000000000000011
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 547)] Elaborating instance u_axi_full_m2
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m.v(line number: 2)] Elaborating module AXI_FULL_M
I: Module instance {pcie_dma_test/user_axi_m_arbitration/u_axi_full_m2} parameter value:
    VIDEO_LENGTH = 32'b00000000000000000000001111000000
    VIDEO_HIGTH = 32'b00000000000000000000001000011100
    PIXEL_WIDTH = 32'b00000000000000000000000000100000
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    DQ_WIDTH = 32'b00000000000000000000000000010000
    M_AXI_BRUST_LEN = 32'b00000000000000000000000000001000
    VIDEO_BASE_ADDR = 32'b00000000000000000000000000000010
    IDLE = 32'b00000000000000000000000000000000
    WRITE_START = 32'b00000000000000000000000000000001
    WRITE_ADDR = 32'b00000000000000000000000000000010
    WRITE_DATA = 32'b00000000000000000000000000000011
    READ_START = 32'b00000000000000000000000000000001
    READ_ADDR = 32'b00000000000000000000000000000010
    READ_DATA = 32'b00000000000000000000000000000011
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 595)] Elaborating instance u_axi_full_m3
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m.v(line number: 2)] Elaborating module AXI_FULL_M
I: Module instance {pcie_dma_test/user_axi_m_arbitration/u_axi_full_m3} parameter value:
    VIDEO_LENGTH = 32'b00000000000000000000001111000000
    VIDEO_HIGTH = 32'b00000000000000000000001000011100
    PIXEL_WIDTH = 32'b00000000000000000000000000100000
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    DQ_WIDTH = 32'b00000000000000000000000000010000
    M_AXI_BRUST_LEN = 32'b00000000000000000000000000001000
    VIDEO_BASE_ADDR = 32'b00000000000000000000000000000011
    IDLE = 32'b00000000000000000000000000000000
    WRITE_START = 32'b00000000000000000000000000000001
    WRITE_ADDR = 32'b00000000000000000000000000000010
    WRITE_DATA = 32'b00000000000000000000000000000011
    READ_START = 32'b00000000000000000000000000000001
    READ_ADDR = 32'b00000000000000000000000000000010
    READ_DATA = 32'b00000000000000000000000000000011
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 636)] Elaborating instance user_rw_fifo_ctrl0
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/rw_fifo_ctrl.v(line number: 1)] Elaborating module rw_fifo_ctrl
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/rw_fifo_ctrl.v(line number: 93)] Elaborating instance user_write_ddr_fifo
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/write_ddr_fifo.v(line number: 18)] Elaborating module write_ddr_fifo
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/write_ddr_fifo.v(line number: 164)] Elaborating instance U_ipml_fifo_write_ddr_fifo
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_fifo_v1_6_write_ddr_fifo.v(line number: 25)] Elaborating module ipml_fifo_v1_6_write_ddr_fifo
I: Module instance {pcie_dma_test/user_axi_m_arbitration/user_rw_fifo_ctrl0/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo} parameter value:
    c_SIM_DEVICE = LOGOS
    c_WR_DEPTH_WIDTH = 32'b00000000000000000000000000001011
    c_WR_DATA_WIDTH = 32'b00000000000000000000000000100000
    c_RD_DEPTH_WIDTH = 32'b00000000000000000000000000001000
    c_RD_DATA_WIDTH = 32'b00000000000000000000000100000000
    c_OUTPUT_REG = 32'b00000000000000000000000000000000
    c_RD_OCE_EN = 32'b00000000000000000000000000000000
    c_RESET_TYPE = ASYNC_RESET
    c_POWER_OPT = 32'b00000000000000000000000000000000
    c_RD_CLK_OR_POL_INV = 32'b00000000000000000000000000000000
    c_WR_BYTE_EN = 32'b00000000000000000000000000000000
    c_BE_WIDTH = 32'b00000000000000000000000000000001
    c_FIFO_TYPE = ASYN
    c_ALMOST_FULL_NUM = 32'b00000000000000000000011111111100
    c_ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_fifo_v1_6_write_ddr_fifo.v(line number: 93)] Elaborating instance U_ipml_sdpram
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 20)] Elaborating module ipml_sdpram_v1_6_write_ddr_fifo
I: Module instance {pcie_dma_test/user_axi_m_arbitration/user_rw_fifo_ctrl0/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram} parameter value:
    c_SIM_DEVICE = LOGOS
    c_WR_ADDR_WIDTH = 32'b00000000000000000000000000001011
    c_WR_DATA_WIDTH = 32'b00000000000000000000000000100000
    c_RD_ADDR_WIDTH = 32'b00000000000000000000000000001000
    c_RD_DATA_WIDTH = 32'b00000000000000000000000100000000
    c_OUTPUT_REG = 32'b00000000000000000000000000000000
    c_RD_OCE_EN = 32'b00000000000000000000000000000000
    c_WR_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_RD_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_WR_CLK_EN = 32'b00000000000000000000000000000001
    c_RD_CLK_EN = 32'b00000000000000000000000000000001
    c_RD_CLK_OR_POL_INV = 32'b00000000000000000000000000000000
    c_RESET_TYPE = ASYNC_RESET
    c_POWER_OPT = 32'b00000000000000000000000000000000
    c_INIT_FILE = NONE
    c_INIT_FORMAT = BIN
    c_WR_BYTE_EN = 32'b00000000000000000000000000000000
    c_BE_WIDTH = 32'b00000000000000000000000000000001
W: Verilog-2039: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 474)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2039: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 476)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2039: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 622)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 682)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 683)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 684)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 685)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 685)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 686)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 686)] Case condition never applies
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[4] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[5] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[6] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[7] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[8] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[9] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[10] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[11] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[12] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[13] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[14] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[15] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[16] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[17] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[22] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[23] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[24] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[25] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[26] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[27] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[28] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[29] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[30] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[31] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[32] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[33] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[34] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[35] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[40] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[41] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[42] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[43] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[44] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[45] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[46] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[47] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[48] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[49] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[50] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[51] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[52] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[53] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[58] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[59] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[60] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[61] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[62] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[63] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[64] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[65] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[66] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[67] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[68] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[69] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[70] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[71] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[76] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[77] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[78] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[79] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[80] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[81] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[82] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[83] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[84] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[85] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[86] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[87] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[88] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[89] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[94] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[95] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[96] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[97] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[98] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[99] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[100] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[101] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[102] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[103] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[104] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[105] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[106] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[107] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[112] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[113] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[114] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[115] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[116] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[117] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[118] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[119] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[120] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[121] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[122] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[123] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[124] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[125] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[130] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[131] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[132] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[133] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[134] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[135] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[136] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[137] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[138] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[139] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[140] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[141] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[142] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 773)] Net DA_bus[143] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[8] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[17] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[26] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[35] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[44] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[53] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[62] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[71] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[80] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[89] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[98] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[107] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[116] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[125] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[134] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 774)] Net DB_bus[143] in ipml_sdpram_v1_6_write_ddr_fifo(original module ipml_sdpram_v1_6_write_ddr_fifo) does not have a driver, tie it to 0
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_fifo_v1_6_write_ddr_fifo.v(line number: 121)] Elaborating instance U_ipml_fifo_ctrl
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_ctrl_v1_3.v(line number: 21)] Elaborating module ipml_fifo_ctrl_v1_3
I: Module instance {pcie_dma_test/user_axi_m_arbitration/user_rw_fifo_ctrl0/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_fifo_ctrl} parameter value:
    c_WR_DEPTH_WIDTH = 32'b00000000000000000000000000001011
    c_RD_DEPTH_WIDTH = 32'b00000000000000000000000000001000
    c_FIFO_TYPE = ASYN
    c_ALMOST_FULL_NUM = 32'b00000000000000000000011111111100
    c_ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/rw_fifo_ctrl.v(line number: 110)] Elaborating instance user_read_ddr_fifo
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/read_ddr_fifo.v(line number: 18)] Elaborating module read_ddr_fifo
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/read_ddr_fifo.v(line number: 164)] Elaborating instance U_ipml_fifo_read_ddr_fifo
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_v1_6_read_ddr_fifo.v(line number: 25)] Elaborating module ipml_fifo_v1_6_read_ddr_fifo
I: Module instance {pcie_dma_test/user_axi_m_arbitration/user_rw_fifo_ctrl0/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo} parameter value:
    c_SIM_DEVICE = LOGOS
    c_WR_DEPTH_WIDTH = 32'b00000000000000000000000000001000
    c_WR_DATA_WIDTH = 32'b00000000000000000000000100000000
    c_RD_DEPTH_WIDTH = 32'b00000000000000000000000000001011
    c_RD_DATA_WIDTH = 32'b00000000000000000000000000100000
    c_OUTPUT_REG = 32'b00000000000000000000000000000000
    c_RD_OCE_EN = 32'b00000000000000000000000000000000
    c_RESET_TYPE = ASYNC_RESET
    c_POWER_OPT = 32'b00000000000000000000000000000000
    c_RD_CLK_OR_POL_INV = 32'b00000000000000000000000000000000
    c_WR_BYTE_EN = 32'b00000000000000000000000000000000
    c_BE_WIDTH = 32'b00000000000000000000000000000001
    c_FIFO_TYPE = ASYN
    c_ALMOST_FULL_NUM = 32'b00000000000000000000000001111100
    c_ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_v1_6_read_ddr_fifo.v(line number: 93)] Elaborating instance U_ipml_sdpram
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 20)] Elaborating module ipml_sdpram_v1_6_read_ddr_fifo
I: Module instance {pcie_dma_test/user_axi_m_arbitration/user_rw_fifo_ctrl0/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram} parameter value:
    c_SIM_DEVICE = LOGOS
    c_WR_ADDR_WIDTH = 32'b00000000000000000000000000001000
    c_WR_DATA_WIDTH = 32'b00000000000000000000000100000000
    c_RD_ADDR_WIDTH = 32'b00000000000000000000000000001011
    c_RD_DATA_WIDTH = 32'b00000000000000000000000000100000
    c_OUTPUT_REG = 32'b00000000000000000000000000000000
    c_RD_OCE_EN = 32'b00000000000000000000000000000000
    c_WR_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_RD_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_WR_CLK_EN = 32'b00000000000000000000000000000001
    c_RD_CLK_EN = 32'b00000000000000000000000000000001
    c_RD_CLK_OR_POL_INV = 32'b00000000000000000000000000000000
    c_RESET_TYPE = ASYNC_RESET
    c_POWER_OPT = 32'b00000000000000000000000000000000
    c_INIT_FILE = NONE
    c_INIT_FORMAT = BIN
    c_WR_BYTE_EN = 32'b00000000000000000000000000000000
    c_BE_WIDTH = 32'b00000000000000000000000000000001
W: Verilog-2039: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 474)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2039: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 476)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 488)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 488)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 488)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 488)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 488)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 488)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 488)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 486)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 487)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 488)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 489)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 490)] Case condition never applies
W: Verilog-2039: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 622)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 682)] Case condition never applies
W: Verilog-2038: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 683)] Case condition never applies
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 852)] Elaborating instance U_GTP_DRM9K
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[8] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[17] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[26] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[35] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[44] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[53] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[62] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[71] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[80] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[89] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[98] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[107] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[116] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[125] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[134] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 773)] Net DA_bus[143] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[8] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[17] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[26] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[35] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[44] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[53] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[62] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[71] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[80] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[89] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[98] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[107] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[116] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[125] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[134] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 774)] Net DB_bus[143] in ipml_sdpram_v1_6_read_ddr_fifo(original module ipml_sdpram_v1_6_read_ddr_fifo) does not have a driver, tie it to 0
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_v1_6_read_ddr_fifo.v(line number: 121)] Elaborating instance U_ipml_fifo_ctrl
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_fifo_ctrl_v1_3.v(line number: 21)] Elaborating module ipml_fifo_ctrl_v1_3
I: Module instance {pcie_dma_test/user_axi_m_arbitration/user_rw_fifo_ctrl0/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_fifo_ctrl} parameter value:
    c_WR_DEPTH_WIDTH = 32'b00000000000000000000000000001000
    c_RD_DEPTH_WIDTH = 32'b00000000000000000000000000001011
    c_FIFO_TYPE = ASYN
    c_ALMOST_FULL_NUM = 32'b00000000000000000000000001111100
    c_ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 658)] Elaborating instance user_rw_fifo_ctrl1
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/rw_fifo_ctrl.v(line number: 1)] Elaborating module rw_fifo_ctrl
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 680)] Elaborating instance user_rw_fifo_ctrl2
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/rw_fifo_ctrl.v(line number: 1)] Elaborating module rw_fifo_ctrl
I: Verilog-0004: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/axi_m_arbitration.v(line number: 702)] Elaborating instance user_rw_fifo_ctrl3
I: Verilog-0003: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/source/rw_fifo_ctrl.v(line number: 1)] Elaborating module rw_fifo_ctrl
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 392)] Width mismatch between port video0_data_in and signal bound to it for instantiated module axi_m_arbitration
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 392)] Width mismatch between port video0_data_out and signal bound to it for instantiated module axi_m_arbitration
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 392)] Width mismatch between port video1_data_in and signal bound to it for instantiated module axi_m_arbitration
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 392)] Width mismatch between port video1_data_out and signal bound to it for instantiated module axi_m_arbitration
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 392)] Width mismatch between port video2_data_out and signal bound to it for instantiated module axi_m_arbitration
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 392)] Width mismatch between port video3_data_out and signal bound to it for instantiated module axi_m_arbitration
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 392)] Width mismatch between port wr_addr_max and signal bound to it for instantiated module axi_m_arbitration
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 392)] Width mismatch between port y_act and signal bound to it for instantiated module axi_m_arbitration
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 392)] Width mismatch between port x_act and signal bound to it for instantiated module axi_m_arbitration
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 660)] Elaborating instance u_SXT1_FIFO_to_DDR
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/SXT1_FIFO.v(line number: 16)] Elaborating module SXT1_FIFO
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/SXT1_FIFO.v(line number: 168)] Elaborating instance U_ipm2l_fifo_SXT1_FIFO
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_v1_10_SXT1_FIFO.v(line number: 19)] Elaborating module ipm2l_fifo_v1_10_SXT1_FIFO
I: Module instance {pcie_dma_test/u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO} parameter value:
    c_CAS_MODE = 36K
    c_WR_DEPTH_WIDTH = 32'b00000000000000000000000000001010
    c_WR_DATA_WIDTH = 32'b00000000000000000000000010000000
    c_RD_DEPTH_WIDTH = 32'b00000000000000000000000000001010
    c_RD_DATA_WIDTH = 32'b00000000000000000000000010000000
    c_OUTPUT_REG = 32'b00000000000000000000000000000000
    c_RD_OCE_EN = 32'b00000000000000000000000000000000
    c_FAB_REG = 32'b00000000000000000000000000000000
    c_RESET_TYPE = ASYNC
    c_POWER_OPT = 32'b00000000000000000000000000000000
    c_RD_CLK_OR_POL_INV = 32'b00000000000000000000000000000000
    c_WR_BYTE_EN = 32'b00000000000000000000000000000000
    c_BE_WIDTH = 32'b00000000000000000000000000000001
    c_FIFO_TYPE = ASYN
    c_ALMOST_FULL_NUM = 32'b00000000000000000000001111111100
    c_ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_v1_10_SXT1_FIFO.v(line number: 84)] Elaborating instance U_ipm2l_sdpram
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 18)] Elaborating module ipm2l_sdpram_v1_10_SXT1_FIFO
I: Module instance {pcie_dma_test/u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram} parameter value:
    c_CAS_MODE = 36K
    c_WR_ADDR_WIDTH = 32'b00000000000000000000000000001010
    c_WR_DATA_WIDTH = 32'b00000000000000000000000010000000
    c_RD_ADDR_WIDTH = 32'b00000000000000000000000000001010
    c_RD_DATA_WIDTH = 32'b00000000000000000000000010000000
    c_WR_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_WR_CLK_EN = 32'b00000000000000000000000000000001
    c_OUTPUT_REG = 32'b00000000000000000000000000000000
    c_RD_OCE_EN = 32'b00000000000000000000000000000000
    c_FAB_REG = 32'b00000000000000000000000000000000
    c_RD_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_RD_CLK_EN = 32'b00000000000000000000000000000001
    c_RESET_TYPE = ASYNC
    c_RD_CLK_OR_POL_INV = 32'b00000000000000000000000000000000
    c_POWER_OPT = 32'b00000000000000000000000000000000
    c_INIT_FILE = NONE
    c_INIT_FORMAT = BIN
    c_WR_BYTE_EN = 32'b00000000000000000000000000000000
    c_BE_WIDTH = 32'b00000000000000000000000000000001
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 516)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 517)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 538)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 539)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 540)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 541)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 541)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 542)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 542)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 538)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 539)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 540)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 541)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 541)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 542)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 542)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 538)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 539)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 540)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 541)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 541)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 542)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 542)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 538)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 539)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 540)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 541)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 541)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 542)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 542)] Case condition never applies
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 670)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 687)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 688)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 689)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 690)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 690)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 691)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 691)] Case condition never applies
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Elaborating instance U_GTP_DRM36K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Elaborating instance U_GTP_DRM36K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Elaborating instance U_GTP_DRM36K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Elaborating instance U_GTP_DRM36K_E1
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Give initial value 0 for the no drive pin INJECT_SBITERR in module instance pcie_dma_test/u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram.ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Give initial value 0 for the no drive pin INJECT_DBITERR in module instance pcie_dma_test/u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram.ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Give initial value 0 for the no drive pin INJECT_SBITERR in module instance pcie_dma_test/u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram.ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM36K_E1
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Give initial value 0 for the no drive pin INJECT_DBITERR in module instance pcie_dma_test/u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram.ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM36K_E1
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Give initial value 0 for the no drive pin INJECT_SBITERR in module instance pcie_dma_test/u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram.ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM36K_E1
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Give initial value 0 for the no drive pin INJECT_DBITERR in module instance pcie_dma_test/u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram.ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM36K_E1
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Give initial value 0 for the no drive pin INJECT_SBITERR in module instance pcie_dma_test/u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram.ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM36K_E1
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 869)] Give initial value 0 for the no drive pin INJECT_DBITERR in module instance pcie_dma_test/u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram.ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM36K_E1
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[8] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[17] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[26] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[35] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[44] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[53] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[62] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[71] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[80] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[89] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[98] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[107] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[116] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[125] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[134] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 779)] Net DA_bus[143] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[8] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[17] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[26] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[35] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[44] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[53] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[62] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[71] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[80] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[89] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[98] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[107] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[116] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[125] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[134] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v(line number: 780)] Net DB_bus[143] in ipm2l_sdpram_v1_10_SXT1_FIFO(original module ipm2l_sdpram_v1_10_SXT1_FIFO) does not have a driver, tie it to 0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_v1_10_SXT1_FIFO.v(line number: 109)] Elaborating instance U_ipm2l_fifo_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v(line number: 18)] Elaborating module ipm2l_fifo_ctrl_v1_1_SXT1_FIFO
I: Module instance {pcie_dma_test/u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl} parameter value:
    c_WR_DEPTH_WIDTH = 32'b00000000000000000000000000001010
    c_RD_DEPTH_WIDTH = 32'b00000000000000000000000000001010
    c_FIFO_TYPE = ASYN
    c_ALMOST_FULL_NUM = 32'b00000000000000000000001111111100
    c_ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v(line number: 195)] Repeat multiplier in concatenation evaluates to 0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 705)] Elaborating instance GTP_GRS_INST
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 716)] Elaborating instance u_ddr3
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3.v(line number: 12)] Elaborating module ddr3
I: Module instance {pcie_dma_test/u_ddr3} parameter value:
    MEM_ROW_WIDTH = 32'b00000000000000000000000000001111
    MEM_COLUMN_WIDTH = 32'b00000000000000000000000000001010
    MEM_BANK_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DM_WIDTH = 32'b00000000000000000000000000000010
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3.v(line number: 288)] Elaborating instance u_ddrc_rstn_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrc_rstn_sync} parameter value:
    DATA_WIDTH = 1'b1
    DFT_VALUE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3.v(line number: 323)] Elaborating instance u_ips_ddrc_top
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 619)] Elaborating module ips2l_mcdq_wrapper_v1_2b
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top} parameter value:
    DDR_TYPE = 2'b00
    MEM_ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    MEM_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ADDR_MAPPING_SEL = 32'b00000000000000000000000000000001
    TOTAL_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MR0_DDR3 = 16'b0001010100100000
    MR1_DDR3 = 16'b0000000000010100
    MR2_DDR3 = 16'b0000000000000000
    MR3_DDR3 = 16'b0000000000000000
    MR_DDR2 = 16'b0000000000000000
    EMR1_DDR2 = 16'b0000000000000000
    EMR2_DDR2 = 16'b0000000000000000
    EMR3_DDR2 = 16'b0000000000000000
    MR_LPDDR = 16'b0000000000000000
    EMR_LPDDR = 16'b0000000000000000
    TXSDLL = 32'b00000000000000000000001000000000
    TCCD = 32'b00000000000000000000000000000100
    TXP = 32'b00000000000000000000000000000011
    TFAW = 32'b00000000000000000000000000010010
    TRAS = 32'b00000000000000000000000000001110
    TRCD = 32'b00000000000000000000000000000110
    TREFI = 32'b00000000000000000000110000110000
    TRFC = 32'b00000000000000000000000001101000
    TRC = 32'b00000000000000000000000000010100
    TRP = 32'b00000000000000000000000000000110
    TRRD = 32'b00000000000000000000000000000100
    TRTP = 32'b00000000000000000000000000000100
    TWR = 32'b00000000000000000000000000000110
    TWTR = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 867)] Elaborating instance mcdq_ui_axi
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp(line number: 271)] Elaborating module ips2l_mcdq_ui_axi_v1_2a
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_ui_axi} parameter value:
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    MEM_ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    ADDR_MAPPING_SEL = 32'b00000000000000000000000000000001
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp(line number: 427)] Elaborating instance mcdq_reg_fifo2
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp(line number: 78)] Elaborating module ips2l_mcdq_reg_fifo2_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2} parameter value:
    W = 32'b00000000000000000000000000100110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp(line number: 543)] Elaborating instance u_user_cmd_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp(line number: 78)] Elaborating module ips2l_mcdq_reg_fifo2_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo} parameter value:
    W = 32'b00000000000000000000000000110111
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 902)] Elaborating instance mcdq_wdatapath
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp(line number: 171)] Elaborating module ips2l_mcdq_wdatapath_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_wdatapath} parameter value:
    DDR_TYPE = 2'b00
    DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp(line number: 239)] Elaborating instance ips_distributed_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000000010
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 192)] Elaborating instance u_ips2l_distributed_fifo_distributed_fifo_v1_0
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000000010
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 173)] Elaborating instance ips2l_distributed_sdpram_distributed_fifo_v1_0
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 120)] Elaborating module ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000000010
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    INIT_FILE = NONE
    FILE_FORMAT = BIN
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 193)] Elaborating instance u_ips2l_distributed_fifo_ctr
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp(line number: 269)] Elaborating module ips2l_distributed_fifo_ctr_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr} parameter value:
    DEPTH = 32'b00000000000000000000000000000100
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp(line number: 278)] Elaborating instance mc3q_wdp_dcp
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp(line number: 133)] Elaborating module ips2l_mcdq_wdp_dcp_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp(line number: 313)] Elaborating instance mcdq_wdp_align
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp(line number: 140)] Elaborating module ips2l_mcdq_wdp_align_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align} parameter value:
    DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 929)] Elaborating instance mcdq_rdatapath
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp(line number: 83)] Elaborating module ips2l_mcdq_rdatapath_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_rdatapath} parameter value:
    DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp(line number: 114)] Elaborating instance mcdq_prefetch_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp(line number: 95)] Elaborating module ips2l_mcdq_prefetch_fifo_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo} parameter value:
    D = 32'b00000000000000000000000000100000
    W = 32'b00000000000000000000000000000101
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp(line number: 165)] Elaborating instance ips2l_distributed_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000101
    DATA_WIDTH = 32'b00000000000000000000000000000101
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 192)] Elaborating instance u_ips2l_distributed_fifo_distributed_fifo_v1_0
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000101
    DATA_WIDTH = 32'b00000000000000000000000000000101
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 173)] Elaborating instance ips2l_distributed_sdpram_distributed_fifo_v1_0
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 120)] Elaborating module ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000101
    DATA_WIDTH = 32'b00000000000000000000000000000101
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    INIT_FILE = NONE
    FILE_FORMAT = BIN
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 193)] Elaborating instance u_ips2l_distributed_fifo_ctr
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp(line number: 269)] Elaborating module ips2l_distributed_fifo_ctr_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr} parameter value:
    DEPTH = 32'b00000000000000000000000000000101
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 957)] Elaborating instance mcdq_dcd_top
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp(line number: 174)] Elaborating module ips2l_mcdq_dcd_top_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcd_top} parameter value:
    SINGLE_RANK = true
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    RADDR_WIDTH = 32'b00000000000000000000000000000001
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    BURST_LENGTH = 32'b00000000000000000000000000001000
    TREFI = 32'b00000000000000000000001100001100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp(line number: 238)] Elaborating instance mcdq_dcd_bm
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp(line number: 243)] Elaborating module ips2l_mcdq_dcd_bm_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm} parameter value:
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    TOTAL_BANK_WIDTH = 32'b00000000000000000000000000000011
    TREFI = 32'b00000000000000000000001100001100
    REF_NUM = 32'b00000000000000000000000000001000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp(line number: 374)] Elaborating instance mcdq_dcd_rowaddr
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp(line number: 76)] Elaborating module ips2l_mcdq_dcd_rowaddr_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr} parameter value:
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    TOTAL_BANK_WIDTH = 32'b00000000000000000000000000000011
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp(line number: 282)] Elaborating instance mcdq_dcd_sm
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp(line number: 209)] Elaborating module ips2l_mcdq_dcd_sm_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm} parameter value:
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    BURST_LENGTH = 32'b00000000000000000000000000001000
    REF_NUM = 32'b00000000000000000000000000001000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1006)] Elaborating instance mcdq_dcp_top
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp(line number: 329)] Elaborating module ips2l_mcdq_dcp_top_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top} parameter value:
    SINGLE_RANK = true
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    RADDR_WIDTH = 32'b00000000000000000000000000000001
    TZQCS = 32'b00000000000000000000000001001011
    TRP = 32'b00000000000000000000000000000110
    TFAW = 32'b00000000000000000000000000010010
    TRAS = 32'b00000000000000000000000000001110
    TRCD = 32'b00000000000000000000000000000110
    TRFC = 32'b00000000000000000000000001101000
    TRRD = 32'b00000000000000000000000000000100
    TRC = 32'b00000000000000000000000000010100
    TCCD = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp(line number: 434)] Elaborating instance mcdq_dcp_buf
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp(line number: 298)] Elaborating module ips2l_mcdq_dcp_buf_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf} parameter value:
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    FIFO_DATA_WIDTH = 32'b00000000000000000000000000101011
    TRFC = 32'b00000000000000000000000001101000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp(line number: 408)] Elaborating instance A_ips2l_distributed_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ips2l_distributed_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000101011
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000001100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 192)] Elaborating instance u_ips2l_distributed_fifo_distributed_fifo_v1_0
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000101011
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000001100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 173)] Elaborating instance ips2l_distributed_sdpram_distributed_fifo_v1_0
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 120)] Elaborating module ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000101011
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    INIT_FILE = NONE
    FILE_FORMAT = BIN
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 193)] Elaborating instance u_ips2l_distributed_fifo_ctr
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp(line number: 269)] Elaborating module ips2l_distributed_fifo_ctr_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr} parameter value:
    DEPTH = 32'b00000000000000000000000000000100
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000001100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp(line number: 459)] Elaborating instance B_ips2l_distributed_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000101011
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000001100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp(line number: 498)] Elaborating instance mcdq_dcp_back_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 643)] Elaborating module ips2l_mcdq_dcp_back_ctrl_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl} parameter value:
    SINGLE_RANK = true
    FIFO_DATA_WIDTH = 32'b00000000000000000000000000101011
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    RADDR_WIDTH = 32'b00000000000000000000000000000001
    TZQCS = 32'b00000000000000000000000001001011
    TRP = 32'b00000000000000000000000000000110
    TFAW = 32'b00000000000000000000000000010010
    TRAS = 32'b00000000000000000000000000001110
    TRCD = 32'b00000000000000000000000000000110
    TRFC = 32'b00000000000000000000000001101000
    TRRD = 32'b00000000000000000000000000000100
    TRC = 32'b00000000000000000000000000010100
    TCCD = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1038)] Elaborating instance timing_act2wr_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp(line number: 115)] Elaborating module ips2l_mcdq_timing_act2wr_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act2wr_pass} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1052)] Elaborating instance mcdq_timing_rd_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp(line number: 128)] Elaborating module ips2l_mcdq_timing_rd_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000011
    CNT1_WIDTH = 32'b00000000000000000000000000000111
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1048)] Width mismatch between port cnt_init0 and signal bound to it for instantiated module ips2l_mcdq_timing_rd_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1071)] Elaborating instance timing_wr_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp(line number: 127)] Elaborating module ips2l_mcdq_timing_wr_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000011
    CNT1_WIDTH = 32'b00000000000000000000000000000110
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1067)] Width mismatch between port cnt_init0 and signal bound to it for instantiated module ips2l_mcdq_timing_wr_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1158)] Elaborating instance timing_prea_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1153)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1178)] Elaborating instance timing_ref_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp(line number: 90)] Elaborating module ips2l_mcdq_timing_ref_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1175)] Width mismatch between port cnt_init0 and signal bound to it for instantiated module ips2l_mcdq_timing_ref_pass_v1_2
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1175)] Width mismatch between port cnt_init1 and signal bound to it for instantiated module ips2l_mcdq_timing_ref_pass_v1_2
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1175)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_ref_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000010100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000010100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000010100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000010100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000010100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000010100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000010100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000010100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1245)] Elaborating instance tfaw_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp(line number: 128)] Elaborating module ips2l_mcdq_tfaw_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TFAW = 32'b00000000000000000000000000010010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp(line number: 168)] Elaborating instance mcdq_tfaw
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp(line number: 68)] Elaborating module ips2l_mcdq_tfaw_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw} parameter value:
    TFAW = 32'b00000000000000000000000000010010
    CNT_WIDTH = 32'b00000000000000000000000000000101
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp(line number: 168)] Elaborating instance mcdq_tfaw
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp(line number: 68)] Elaborating module ips2l_mcdq_tfaw_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw} parameter value:
    TFAW = 32'b00000000000000000000000000010010
    CNT_WIDTH = 32'b00000000000000000000000000000101
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp(line number: 168)] Elaborating instance mcdq_tfaw
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp(line number: 68)] Elaborating module ips2l_mcdq_tfaw_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw} parameter value:
    TFAW = 32'b00000000000000000000000000010010
    CNT_WIDTH = 32'b00000000000000000000000000000101
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1330)] Elaborating instance timing_act_pass
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp(line number: 92)] Elaborating module ips2l_mcdq_timing_act_pass_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1327)] Width mismatch between port cnt_init0 and signal bound to it for instantiated module ips2l_mcdq_timing_act_pass_v1_2
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1327)] Width mismatch between port cnt_init1 and signal bound to it for instantiated module ips2l_mcdq_timing_act_pass_v1_2
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1327)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_act_pass_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp(line number: 535)] Elaborating instance mcdq_dcp_out
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp(line number: 210)] Elaborating module ips2l_mcdq_dcp_out_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out} parameter value:
    SINGLE_RANK = true
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    BADDR_WIDTH = 32'b00000000000000000000000000000011
    RADDR_WIDTH = 32'b00000000000000000000000000000001
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1057)] Elaborating instance mcdq_calib_delay
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp(line number: 101)] Elaborating module ips2l_mcdq_calib_delay_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_calib_delay} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000001111
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1085)] Elaborating instance mcdq_dfi
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp(line number: 432)] Elaborating module ips2l_mcdq_dfi_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_dfi} parameter value:
    BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    TOTAL_ADDR_WIDTH = 32'b00000000000000000000000000001111
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp(line number: 553)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp(line number: 617)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp(line number: 729)] Repeat multiplier in concatenation evaluates to 0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1123)] Elaborating instance mcdq_apb_cross_v1_2
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp(line number: 145)] Elaborating module ips2l_mcdq_apb_cross_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1158)] Elaborating instance mcdq_cfg_apb
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp(line number: 559)] Elaborating module ips2l_mcdq_cfg_apb_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb} parameter value:
    DDR_TYPE = 2'b00
    MR0_DDR3 = 16'b0001010100100000
    MR1_DDR3 = 16'b0000000000010100
    MR2_DDR3 = 16'b0000000000000000
    MR3_DDR3 = 16'b0000000000000000
    MR_DDR2 = 16'b0000000000000000
    EMR1_DDR2 = 16'b0000000000000000
    EMR2_DDR2 = 16'b0000000000000000
    EMR3_DDR2 = 16'b0000000000000000
    MR_LPDDR = 16'b0000000000000000
    EMR_LPDDR = 16'b0000000000000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1207)] Elaborating instance mcdq_mrs
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp(line number: 321)] Elaborating module ips2l_mcdq_mrs_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_mrs} parameter value:
    DDR_TYPE = 2'b00
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    TRFC = 32'b00000000000000000000000001101000
    TRP = 32'b00000000000000000000000000000110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1233)] Elaborating instance mcdq_lp
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp(line number: 315)] Elaborating module ips2l_mcdq_lp_v1_2
I: Module instance {pcie_dma_test/u_ddr3/u_ips_ddrc_top/mcdq_lp} parameter value:
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    TRFC = 32'b00000000000000000000000001101000
    TREFI = 32'b00000000000000000000001100001100
    TRP = 32'b00000000000000000000000000000110
    TXSDLL = 32'b00000000000000000000000010000000
    TXP = 32'b00000000000000000000000000000011
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3.v(line number: 397)] Elaborating instance u_ddrphy_top
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 12)] Elaborating module ddr3_ddrphy_top
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top} parameter value:
    MEM_TYPE = DDR3
    TMRD = 8'b00000001
    TMOD = 8'b00000011
    TXPR = 8'b00011011
    TRP = 8'b00000010
    TRFC = 8'b00011010
    TRCD = 8'b00000010
    MEM_ROW_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANK_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DM_WIDTH = 32'b00000000000000000000000000000010
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 422)] Elaborating instance u_clkbufm
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 432)] Elaborating instance u_ips2l_ddrphy_rst_clk_phase_adj
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp(line number: 104)] Elaborating module ips2l_ddrphy_rst_clk_phase_adj_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj} parameter value:
    PHASE_ADJ_DIR = 32'b00000000000000000000000000000000
    PHASE_ADJ_STEP = 32'b00000000000000000000000000001000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 455)] Elaborating instance rst_clk_gpll
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 127)] Elaborating module ips2l_ddrphy_gpll_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/rst_clk_gpll} parameter value:
    CLKIN_FREQ = 25.000000
    BANDWIDTH = OPTIMIZED
    IDIV = 32'b00000000000000000000000000000001
    FDIV = 32.000000
    DUTYF = 32'b00000000000000000000000000100000
    ODIV0 = 32.000000
    ODIV1 = 32'b00000000000000000000000001000000
    DUTY0 = 32'b00000000000000000000000000100000
    STATIC_PHASE0 = 32'b00000000000000000000000000000000
    INTERNAL_FB = CLKOUTF
    ODIV2 = 32'b00000000000000000000000000000100
    ODIV3 = 32'b00000000000000000000000000001000
    ODIV4 = 32'b00000000000000000000000000010000
    ODIV5 = 32'b00000000000000000000000000100000
    ODIV6 = 32'b00000000000000000000000001000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 221)] Elaborating instance u_gpll
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 470)] Elaborating instance u_rst_clk_bufg
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 479)] Elaborating instance u_ddrphy_rst_seq_rstn_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 497)] Elaborating instance ddrphy_gpll
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 127)] Elaborating module ips2l_ddrphy_gpll_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_gpll} parameter value:
    CLKIN_FREQ = 25.000000
    BANDWIDTH = OPTIMIZED
    IDIV = 32'b00000000000000000000000000000001
    FDIV = 32.000000
    DUTYF = 32'b00000000000000000000000000100000
    ODIV0 = 8.000000
    ODIV1 = 32'b00000000000000000000000000010000
    DUTY0 = 32'b00000000000000000000000000001000
    STATIC_PHASE0 = 32'b00000000000000000000000000000000
    INTERNAL_FB = CLKOUTF
    ODIV2 = 32'b00000000000000000000000000000100
    ODIV3 = 32'b00000000000000000000000000001000
    ODIV4 = 32'b00000000000000000000000000010000
    ODIV5 = 32'b00000000000000000000000000100000
    ODIV6 = 32'b00000000000000000000000001000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 221)] Elaborating instance u_gpll
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 512)] Elaborating instance u_ddrphy_gpll_phase
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp(line number: 69)] Elaborating module ips2l_ddrphy_gpll_phase_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 521)] Elaborating instance u_sysclk_bufg
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 528)] Elaborating instance u_ddrphy_cpd
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 541)] Elaborating instance u_ddrphy_cpd_rstn_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/u_ddrphy_cpd_rstn_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 548)] Elaborating instance u_ips2l_ddrphy_cpd_lock
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp(line number: 71)] Elaborating module ips2l_ddrphy_cpd_lock_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 556)] Elaborating instance ddrphy_cpd_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp(line number: 182)] Elaborating module ips2l_ddrphy_cpd_ctrl_v1_3
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 576)] Elaborating instance ddrphy_reset_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 268)] Elaborating module ips2l_ddrphy_reset_ctrl_v1_3
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 412)] Elaborating instance ddrphy_pll_lock_debounce
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp(line number: 84)] Elaborating module ips2l_ddrphy_rst_debounce_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce} parameter value:
    RISE_CNTR_WIDTH = 32'b00000000000000000000000000010011
    RISE_CNTR_VALUE = 19'b1000000000000000000
    ACTIVE_HIGH = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 620)] Elaborating instance u_ddrphy_rstn_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 630)] Elaborating instance u_dll_rst_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 609)] Elaborating instance ddrphy_dll_update_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp(line number: 124)] Elaborating module ips2l_ddrphy_dll_update_ctrl_v1_3
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 626)] Elaborating instance u_dll_update_n_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/u_dll_update_n_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 636)] Elaborating instance u_dll_freeze_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/u_dll_freeze_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 646)] Elaborating instance ddrphy_gate_update_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp(line number: 100)] Elaborating module ips2l_ddrphy_gate_update_ctrl_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_gate_update_ctrl} parameter value:
    UPDATE_EN = 1'b0
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp(line number: 182)] Elaborating instance ddrphy_drift_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp(line number: 112)] Elaborating module ips2l_ddrphy_drift_ctrl_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp(line number: 182)] Elaborating instance ddrphy_drift_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp(line number: 112)] Elaborating module ips2l_ddrphy_drift_ctrl_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 681)] Elaborating instance ddrphy_calib_top
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 392)] Elaborating module ips2l_ddrphy_calib_top_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_calib_top} parameter value:
    DDR_TYPE = 2'b00
    WRCAL_EN = 1'b0
    EYECAL_EN = 32'b00000000000000000000000000000001
    T200US = 20'b00000101001000001000
    T500US = 20'b00001100011100111000
    T400NS = 8'b00101001
    TMRD = 8'b00000001
    TMOD = 8'b00000011
    TXPR = 8'b00011011
    TRP = 8'b00000010
    TZQINIT = 10'b0010000000
    TRFC = 8'b00011010
    TRCD = 8'b00000010
    REF_CNT = 4'b1001
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DM_WIDTH = 32'b00000000000000000000000000000010
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 597)] Elaborating instance ddrphy_main_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp(line number: 196)] Elaborating module ips2l_ddrphy_main_ctrl_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl} parameter value:
    DDR_TYPE = 2'b00
    EYECAL_EN = 32'b00000000000000000000000000000001
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 641)] Elaborating instance ddrphy_init
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp(line number: 577)] Elaborating module ips2l_ddrphy_init_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init} parameter value:
    DDR_TYPE = 2'b00
    T200US = 20'b00000101001000001000
    T500US = 20'b00001100011100111000
    T400NS = 8'b00101001
    TMRD = 8'b00000001
    TMOD = 8'b00000011
    TXPR = 8'b00011011
    TRP = 8'b00000010
    TRFC = 8'b00011010
    TZQINIT = 10'b0010000000
    REF_CNT = 4'b1001
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 669)] Elaborating instance ddrphy_wrlvl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp(line number: 183)] Elaborating module ips2l_ddrphy_wrlvl_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl} parameter value:
    TMOD = 8'b00000011
    TRFC = 8'b00011010
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 698)] Elaborating instance ddrphy_rdcal
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp(line number: 750)] Elaborating module ips2l_ddrphy_rdcal_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal} parameter value:
    DDR_TYPE = 2'b00
    TRFC = 8'b00011010
    TRCD = 8'b00000010
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 756)] Elaborating instance ddrphy_wrcal
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 495)] Elaborating module ips2l_ddrphy_wrcal_v1_7
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal} parameter value:
    WRCAL_EN = 1'b0
    TRFC = 8'b00011010
    TRCD = 8'b00000010
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 787)] Elaborating instance ddrphy_eyecal
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp(line number: 228)] Elaborating module ips2l_ddrphy_eyecal_v1_5
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal} parameter value:
    TRFC = 8'b00011010
    TRCD = 8'b00000010
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 815)] Elaborating instance ddrphy_calib_mux
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp(line number: 199)] Elaborating module ips2l_ddrphy_calib_mux_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_calib_mux} parameter value:
    DDR_TYPE = 2'b00
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 883)] Elaborating instance ddrphy_upcal
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp(line number: 151)] Elaborating module ips2l_ddrphy_upcal_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal} parameter value:
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 753)] Elaborating instance ddrphy_training_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp(line number: 83)] Elaborating module ips2l_ddrphy_training_ctrl_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_training_ctrl} parameter value:
    SRB_DQS_RST_TRAINING_HIGH_CLK = 32'b00000000000000000000000000000011
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 765)] Elaborating instance u_force_read_clk_ctrl_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/u_force_read_clk_ctrl_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 775)] Elaborating instance u_force_samp_position_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/u_force_samp_position_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 785)] Elaborating instance u_samp_position_dyn_adj_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/u_samp_position_dyn_adj_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 795)] Elaborating instance u_wrcal_position_dyn_adj_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/u_wrcal_position_dyn_adj_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 821)] Elaborating instance ddrphy_slice_top
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 12)] Elaborating module ddr3_slice_top_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top} parameter value:
    CLKIN_FREQ = 25.000000
    PPLL_BANDWIDTH = LOW
    DDR_TYPE = 2'b00
    GATE_MODE = 1'b1
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
    SC_LDO_CTRL = 2'b00
    SC_DLY_2X = 1'b1
    PPLL_IDIV = 32'b00000000000000000000000000000001
    PPLL_FDIV = 32'b00000000000000000000000001000000
    PPLL_ODIVPHY = 32'b00000000000000000000000000000010
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
    MEM_DM_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 580)] Elaborating instance u_clkbufr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 597)] Elaborating instance ddrphy_ppll
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 242)] Elaborating module ips2l_ddrphy_ppll_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll} parameter value:
    CLKIN_FREQ = 25.000000
    BANDWIDTH = LOW
    CLKOUT4_SYN_EN = TRUE
    INTERNAL_FB = CLKOUT4
    IDIV = 32'b00000000000000000000000000000001
    FDIV = 32'b00000000000000000000000001000000
    ODIVPHY = 32'b00000000000000000000000000000010
    ODIV0 = 32'b00000000000000000000000000010000
    ODIV1 = 32'b00000000000000000000000000000010
    ODIV2 = 32'b00000000000000000000000000000100
    ODIV3 = 32'b00000000000000000000000000001000
    ODIV4 = 32'b00000000000000000000000001000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 310)] Elaborating instance u_ppll
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 612)] Elaborating instance u_ddrphy_ioclkdiv
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 580)] Elaborating instance u_clkbufr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 597)] Elaborating instance ddrphy_ppll
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 242)] Elaborating module ips2l_ddrphy_ppll_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll} parameter value:
    CLKIN_FREQ = 25.000000
    BANDWIDTH = LOW
    CLKOUT4_SYN_EN = TRUE
    INTERNAL_FB = CLKOUT4
    IDIV = 32'b00000000000000000000000000000001
    FDIV = 32'b00000000000000000000000001000000
    ODIVPHY = 32'b00000000000000000000000000000010
    ODIV0 = 32'b00000000000000000000000000010000
    ODIV1 = 32'b00000000000000000000000000000010
    ODIV2 = 32'b00000000000000000000000000000100
    ODIV3 = 32'b00000000000000000000000000001000
    ODIV4 = 32'b00000000000000000000000001000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 612)] Elaborating instance u_ddrphy_ioclkdiv
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 635)] Elaborating instance ddrphy_data_slice
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 583)] Elaborating module ips2l_ddrphy_data_slice_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice} parameter value:
    DDR_TYPE = 2'b00
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
    GATE_MODE = 1'b1
    SC_LDO_CTRL = 2'b00
    SC_DLY_2X = 1'b1
    WL_MAX_STEP = 8'b11001001
    WL_MAX_CHECK = 5'b11111
    MIN_DQSI_WIN = 9'b000001010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 810)] Elaborating instance ddrphy_data_slice_wrlvl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp(line number: 292)] Elaborating module ips2l_ddrphy_data_slice_wrlvl_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl} parameter value:
    WL_MAX_STEP = 8'b11001001
    CK_MAX_STEP = 8'b10000000
    WL_MAX_CHECK = 5'b11111
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 841)] Elaborating instance ddrphy_data_slice_wrcal
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 278)] Elaborating module ips2l_ddrphy_data_slice_wrcal_v1_10
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 868)] Elaborating instance ddrphy_data_slice_dqs_gate_cal
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp(line number: 111)] Elaborating module ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal} parameter value:
    GATE_MODE = 1'b1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp(line number: 148)] Elaborating instance ddrphy_dqs_gate_coarse_cal
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp(line number: 173)] Elaborating module ips2l_ddrphy_dqs_gate_coarse_cal_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp(line number: 164)] Elaborating instance ddrphy_gatecal
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp(line number: 243)] Elaborating module ips2l_ddrphy_gatecal_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal} parameter value:
    GATE_MODE = 1'b1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 905)] Elaborating instance ddrphy_dqsi_rdel_cal
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp(line number: 395)] Elaborating module ips2l_ddrphy_dqsi_rdel_cal_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal} parameter value:
    MIN_DQSI_WIN = 9'b000001010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 947)] Elaborating instance ddrphy_dqs_rddata_align
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp(line number: 527)] Elaborating module ips2l_ddrphy_dqs_rddata_align_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align} parameter value:
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 983)] Elaborating instance ddrphy_wdata_path_adj
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp(line number: 232)] Elaborating module ips2l_ddrphy_wdata_path_adj_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj} parameter value:
    DQ_WIDTH = 32'b00000000000000000000000000001000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1012)] Elaborating instance u_ddc_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1052)] Elaborating instance u_dll_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1084)] Elaborating instance u_tserdes0_dqs
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1126)] Elaborating instance u_tserdes1_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1168)] Elaborating instance u_oserdes_dqs
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1200)] Elaborating instance u_iobufco_dqs
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1336)] Elaborating instance u_oserdes_dm
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1357)] Elaborating instance u_outbuft_dm
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[0].u_iodelay_dq
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[1].u_iodelay_dq
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[2].u_iodelay_dq
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[3].u_iodelay_dq
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[4].u_iodelay_dq
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[5].u_iodelay_dq
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[6].u_iodelay_dq
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[7].u_iodelay_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 635)] Elaborating instance ddrphy_data_slice
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 583)] Elaborating module ips2l_ddrphy_data_slice_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice} parameter value:
    DDR_TYPE = 2'b00
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
    GATE_MODE = 1'b1
    SC_LDO_CTRL = 2'b00
    SC_DLY_2X = 1'b1
    WL_MAX_STEP = 8'b11001001
    WL_MAX_CHECK = 5'b11111
    MIN_DQSI_WIN = 9'b000001010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 746)] Elaborating instance ddrphy_slice_rddata_align
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp(line number: 108)] Elaborating module ips2l_ddrphy_slice_rddata_align_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_slice_rddata_align} parameter value:
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 763)] Elaborating instance ddrphy_control_path_adj
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp(line number: 134)] Elaborating module ips2l_ddrphy_control_path_adj_v1_10
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj} parameter value:
    DDR_TYPE = 2'b00
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    SLIP_BIT_NUM = 2'b01
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 801)] Elaborating instance u_ddc_ca
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 853)] Elaborating instance u_tserdes_ca0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 895)] Elaborating instance u_tserdes_ca1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 801)] Elaborating instance u_ddc_ca
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 853)] Elaborating instance u_tserdes_ca0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 895)] Elaborating instance u_tserdes_ca1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 801)] Elaborating instance u_ddc_ca
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 853)] Elaborating instance u_tserdes_ca0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 895)] Elaborating instance u_tserdes_ca1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 940)] Elaborating instance u_oserdes_ck
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 975)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 982)] Elaborating instance u_outbuftco_ck
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1012)] Elaborating instance u_oserdes_odt
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1036)] Elaborating instance u_odelay_odt
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1043)] Elaborating instance u_outbuft_odt
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1071)] Elaborating instance u_oserdes_csn
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1095)] Elaborating instance u_odelay_csn
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1102)] Elaborating instance u_outbuft_csn
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1130)] Elaborating instance u_oserdes_rasn
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1154)] Elaborating instance u_odelay_rasn
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1161)] Elaborating instance u_outbuft_rasn
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1190)] Elaborating instance u_oserdes_casn
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1214)] Elaborating instance u_odelay_casn
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1221)] Elaborating instance u_outbuft_casn
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1249)] Elaborating instance u_oserdes_wen
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1273)] Elaborating instance u_odelay_wen
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1280)] Elaborating instance u_outbuft_wen
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1309)] Elaborating instance u_oserdes_cke
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1333)] Elaborating instance u_odelay_cke
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1340)] Elaborating instance u_outbuft_cke
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1440)] Elaborating instance u_oserdes_ba
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Elaborating instance u_odelay_ba
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1471)] Elaborating instance u_outbuft_ba
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1440)] Elaborating instance u_oserdes_ba
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Elaborating instance u_odelay_ba
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1471)] Elaborating instance u_outbuft_ba
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1440)] Elaborating instance u_oserdes_ba
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Elaborating instance u_odelay_ba
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1471)] Elaborating instance u_outbuft_ba
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 975)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.u_iodelay_dq
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1036)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.u_odelay_odt
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1095)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.u_odelay_csn
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1154)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.u_odelay_rasn
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1214)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.u_odelay_casn
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1273)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.u_odelay_wen
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1333)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.u_odelay_cke
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[0].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[1].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[2].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[3].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[4].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[5].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[6].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[7].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[8].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[9].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[10].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[11].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[12].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[13].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[14].u_odelay_addr
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.k_mem_ba[0].u_odelay_ba
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.k_mem_ba[1].u_odelay_ba
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Give initial value 0 for the no drive pin EN_N in module instance pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_slice_top.k_mem_ba[2].u_odelay_ba
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 947)] Elaborating instance ddrphy_dfi
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp(line number: 320)] Elaborating module ips2l_ddrphy_dfi_v1_3
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_dfi} parameter value:
    DDR_TYPE = 2'b00
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
    MEM_DM_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 1019)] Elaborating instance ddrphy_info
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp(line number: 174)] Elaborating module ips2l_ddrphy_info_v1_0
I: Module instance {pcie_dma_test/u_ddr3/u_ddrphy_top/ddrphy_info} parameter value:
    DDR_TYPE = 2'b00
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MR0_DDR3 = 16'b0001010100100000
    MR1_DDR3 = 16'b0000000000010100
    MR2_DDR3 = 16'b0000000000000000
    MR3_DDR3 = 16'b0000000000000000
    MR_DDR2 = 16'b0000101101000011
    EMR1_DDR2 = 16'b0000000000010100
    EMR2_DDR2 = 16'b0000000000000000
    EMR3_DDR2 = 16'b0000000000000000
    MR_LPDDR = 16'b0000000000100011
    EMR_LPDDR = 16'b0000000000000000
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/ddr3.v(line number: 323)] Give initial value 0 for the no drive pin ddr_zqcs_req in module instance pcie_dma_test/u_ddr3.u_ips_ddrc_top
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 708)] Width mismatch between port init_slip_step and signal bound to it for instantiated module ddr3
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 708)] Width mismatch between port init_read_clk_ctrl and signal bound to it for instantiated module ddr3
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1082)] Elaborating instance u_SXT1_FIFO_to_PCIe
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/SXT1_FIFO/SXT1_FIFO.v(line number: 16)] Elaborating module SXT1_FIFO
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1124)] Elaborating instance i2cSlave_u
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave.v(line number: 43)] Elaborating module i2cSlave
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave.v(line number: 164)] Elaborating instance u_registerInterface
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number: 43)] Elaborating module registerInterface
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/i2cSlave.v(line number: 180)] Elaborating instance u_serialInterface
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/serialInterface.v(line number: 53)] Elaborating module serialInterface
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1275)] Elaborating instance u_refclk_buttonrstn_debounce
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_cross_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_cross_sync_v1_0
I: Module instance {pcie_dma_test/u_refclk_buttonrstn_debounce} parameter value:
    RST_CNTR_WIDTH = 32'b00000000000000000000000000010000
    RST_CNTR_VALUE = 16'b1100000000000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1283)] Elaborating instance u_refclk_perstn_debounce
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_cross_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_cross_sync_v1_0
I: Module instance {pcie_dma_test/u_refclk_perstn_debounce} parameter value:
    RST_CNTR_WIDTH = 32'b00000000000000000000000000010000
    RST_CNTR_VALUE = 16'b1100000000000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1289)] Elaborating instance u_ref_core_rstn_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1296)] Elaborating instance u_pclk_core_rstn_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1331)] Elaborating instance u_uart2apb_top
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart2apb_top_32bit.v(line number: 6)] Elaborating module pgr_uart2apb_top_32bit
I: Module instance {pcie_dma_test/u_uart2apb_top} parameter value:
    CLK_DIV_P = 16'b0000000010010001
    FIFO_D = 32'b00000000000000000000000000010000
    WORD_LEN = 2'b11
    PARITY_EN = 1'b0
    PARITY_TYPE = 1'b0
    STOP_LEN = 1'b0
    MODE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart2apb_top_32bit.v(line number: 50)] Elaborating instance u_uart_top
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_top_32bit.v(line number: 6)] Elaborating module pgr_uart_top_32bit
I: Module instance {pcie_dma_test/u_uart2apb_top/u_uart_top} parameter value:
    CLK_DIV_P = 16'b0000000010010001
    FIFO_D = 32'b00000000000000000000000000010000
    WORD_LEN = 2'b11
    PARITY_EN = 1'b0
    PARITY_TYPE = 1'b0
    STOP_LEN = 1'b0
    MODE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_top_32bit.v(line number: 42)] Elaborating instance u_pgr_clk_gen
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_clk_gen_32bit.v(line number: 6)] Elaborating module pgr_clk_gen_32bit
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_top_32bit.v(line number: 54)] Elaborating instance u_tx_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_fifo_top_32bit.v(line number: 6)] Elaborating module pgr_fifo_top_32bit
I: Module instance {pcie_dma_test/u_uart2apb_top/u_uart_top/u_tx_fifo} parameter value:
    D = 32'b00000000000000000000000000010000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_fifo_top_32bit.v(line number: 34)] Elaborating instance u_prefetch_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgr_prefetch_fifo.v(line number: 8)] Elaborating module pgr_prefetch_fifo
I: Module instance {pcie_dma_test/u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo} parameter value:
    D = 32'b00000000000000000000000000010000
    W = 32'b00000000000000000000000000001000
    TYPE = Distributed
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgr_prefetch_fifo.v(line number: 82)] Elaborating instance pgm_distributed_fifo_v1_0
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_v1_1.v(line number: 18)] Elaborating module pgm_distributed_fifo_v1_1
I: Module instance {pcie_dma_test/u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000001000
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_v1_1.v(line number: 60)] Elaborating instance pgm_distributed_sdpram
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_sdpram_v1_1.v(line number: 22)] Elaborating module pgm_distributed_sdpram_v1_1
I: Module instance {pcie_dma_test/u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/pgm_distributed_sdpram} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000001000
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    INIT_FILE = NONE
    FILE_FORMAT = BIN
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_v1_1.v(line number: 80)] Elaborating instance u_pgm_distributed_fifo_ctr_v1_0
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_fifo_ctr_v1_0.v(line number: 18)] Elaborating module pgm_distributed_fifo_ctr_v1_0
I: Module instance {pcie_dma_test/u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0} parameter value:
    DEPTH = 32'b00000000000000000000000000000100
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_top_32bit.v(line number: 71)] Elaborating instance u_rx_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_fifo_top_32bit.v(line number: 6)] Elaborating module pgr_fifo_top_32bit
I: Module instance {pcie_dma_test/u_uart2apb_top/u_uart_top/u_rx_fifo} parameter value:
    D = 32'b00000000000000000000000000010000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_top_32bit.v(line number: 84)] Elaborating instance u_pgr_uart_tx
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_tx_32bit.v(line number: 6)] Elaborating module pgr_uart_tx_32bit
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_top_32bit.v(line number: 102)] Elaborating instance u_pgr_uart_rx
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart_rx_32bit.v(line number: 6)] Elaborating module pgr_uart_rx_32bit
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_uart2apb_top_32bit.v(line number: 68)] Elaborating instance u_apb_ctr
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_ctr_32bit.v(line number: 6)] Elaborating module pgr_apb_ctr_32bit
I: Module instance {pcie_dma_test/u_uart2apb_top/u_apb_ctr} parameter value:
    CLK_DIV_P = 16'b0000000010010001
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_ctr_32bit.v(line number: 39)] Elaborating instance u_apb_mif
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_mif_32bit.v(line number: 6)] Elaborating module pgr_apb_mif_32bit
I: Module instance {pcie_dma_test/u_uart2apb_top/u_apb_ctr/u_apb_mif} parameter value:
    CLK_DIV_P = 16'b0000000010010001
    TX_INTERVAL = 32'b00000000000000000000001101100110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_ctr_32bit.v(line number: 64)] Elaborating instance u_cmd_parser
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_cmd_parser_32bit.v(line number: 6)] Elaborating module pgr_cmd_parser_32bit
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1347)] Elaborating instance u_ips2l_pcie_expd_apb_mux
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_expd_apb_mux.v(line number: 11)] Elaborating module ips2l_expd_apb_mux
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_expd_apb_mux.v(line number: 64)] Elaborating instance u_pcie_expd_apb_cross
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_cross_v1_0.v(line number: 11)] Elaborating module ips2l_pcie_apb_cross_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1390)] Elaborating instance u_ips2l_pcie_dma
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma.v(line number: 15)] Elaborating module ips2l_pcie_dma
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma} parameter value:
    DEVICE_TYPE = 3'b000
    AXIS_SLAVE_NUM = 32'b00000000000000000000000000000011
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma.v(line number: 184)] Elaborating instance u_ips2l_pcie_dma_rx_top
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_top.v(line number: 15)] Elaborating module ips2l_pcie_dma_rx_top
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top} parameter value:
    DEVICE_TYPE = 3'b000
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_top.v(line number: 124)] Elaborating instance u_ips2l_pcie_dma_tlp_rcv
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tlp_rcv.v(line number: 15)] Elaborating module ips2l_pcie_dma_tlp_rcv
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv} parameter value:
    DEVICE_TYPE = 3'b000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_top.v(line number: 188)] Elaborating instance u_cpld_wr_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_cpld_wr_ctrl.v(line number: 15)] Elaborating module ips2l_pcie_dma_rx_cpld_wr_ctrl
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl} parameter value:
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_cpld_wr_ctrl.v(line number: 128)] Elaborating instance u_ipm_distributed_sdpram_v1_2
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ipm_distributed_sdpram_v1_2.v(line number: 18)] Elaborating module ipm_distributed_sdpram_v1_2
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/u_ipm_distributed_sdpram_v1_2} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000110
    DATA_WIDTH = 32'b00000000000000000000000000001010
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000001
    INIT_FILE = NONE
    FILE_FORMAT = BIN
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_cpld_wr_ctrl.v(line number: 166)] Elaborating instance ips2l_pcie_dma_cpld_wr_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_wr_ctrl.v(line number: 15)] Elaborating module ips2l_pcie_dma_wr_ctrl
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/ips2l_pcie_dma_cpld_wr_ctrl} parameter value:
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_top.v(line number: 214)] Elaborating instance u_mwr_wr_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_mwr_wr_ctrl.v(line number: 15)] Elaborating module ips2l_pcie_dma_rx_mwr_wr_ctrl
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_mwr_wr_ctrl} parameter value:
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_mwr_wr_ctrl.v(line number: 42)] Elaborating instance ips2l_pcie_dma_mwr_wr_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_wr_ctrl.v(line number: 15)] Elaborating module ips2l_pcie_dma_wr_ctrl
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_mwr_wr_ctrl/ips2l_pcie_dma_mwr_wr_ctrl} parameter value:
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_top.v(line number: 278)] Elaborating instance ips2l_pcie_dma_bar0
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/ips2l_pcie_dma_ram.v(line number: 18)] Elaborating module ips2l_pcie_dma_ram
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/ips2l_pcie_dma_ram.v(line number: 163)] Elaborating instance U_ipm2l_sdpram_ips2l_pcie_dma_ram
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 20)] Elaborating module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/ips2l_pcie_dma_bar0/U_ipm2l_sdpram_ips2l_pcie_dma_ram} parameter value:
    c_CAS_MODE = 18K
    c_WR_ADDR_WIDTH = 32'b00000000000000000000000000001100
    c_WR_DATA_WIDTH = 32'b00000000000000000000000010000000
    c_RD_ADDR_WIDTH = 32'b00000000000000000000000000001100
    c_RD_DATA_WIDTH = 32'b00000000000000000000000010000000
    c_WR_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_WR_CLK_EN = 32'b00000000000000000000000000000000
    c_OUTPUT_REG = 32'b00000000000000000000000000000000
    c_RD_OCE_EN = 32'b00000000000000000000000000000000
    c_RD_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_RD_CLK_EN = 32'b00000000000000000000000000000001
    c_RESET_TYPE = ASYNC
    c_RD_CLK_OR_POL_INV = 32'b00000000000000000000000000000000
    c_POWER_OPT = 32'b00000000000000000000000000000000
    c_INIT_FILE = NONE
    c_INIT_FORMAT = HEX
    c_WR_BYTE_EN = 32'b00000000000000000000000000000001
    c_BE_WIDTH = 32'b00000000000000000000000000010000
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 455)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 456)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 464)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 465)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 466)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 464)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 465)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 466)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 464)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 465)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 466)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 464)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 465)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 466)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 464)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 465)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 466)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 464)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 465)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 466)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 464)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 465)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 466)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 464)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 465)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 466)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 467)] Case condition never applies
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 569)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 574)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 575)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 576)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 577)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 577)] Case condition never applies
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 806)] Elaborating instance U_GTP_DRM18K_E1
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[8] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[17] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[26] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[35] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[44] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[53] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[62] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[71] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[80] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[89] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[98] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[107] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[116] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[125] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[134] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 664)] Net DA_bus[143] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[8] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[17] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[26] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[35] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[44] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[53] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[62] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[71] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[80] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[89] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[98] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[107] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[116] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[125] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[134] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/rtl/ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram.v(line number: 665)] Net DB_bus[143] in ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram(original module ipm2l_sdpram_v1_1_ips2l_pcie_dma_ram) does not have a driver, tie it to 0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rx_top.v(line number: 303)] Elaborating instance ips2l_pcie_dma_bar2
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_ram/ips2l_pcie_dma_ram.v(line number: 18)] Elaborating module ips2l_pcie_dma_ram
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma.v(line number: 249)] Elaborating instance u_ips2l_pcie_dma_controller
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_controller.v(line number: 15)] Elaborating module ips2l_pcie_dma_controller
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller} parameter value:
    DEVICE_TYPE = 3'b000
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma.v(line number: 298)] Elaborating instance u_ips2l_pcie_dma_tx_top
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v(line number: 15)] Elaborating module ips2l_pcie_dma_tx_top
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top} parameter value:
    DEVICE_TYPE = 3'b000
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v(line number: 121)] Elaborating instance u_ips2l_pcie_dma_tx_cpld_rd_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_cpld_rd_ctrl.v(line number: 15)] Elaborating module ips2l_pcie_dma_tx_cpld_rd_ctrl
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl} parameter value:
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_cpld_rd_ctrl.v(line number: 40)] Elaborating instance u_ips2l_pcie_dma_cpld_rd_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rd_ctrl.v(line number: 15)] Elaborating module ips2l_pcie_dma_rd_ctrl
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl} parameter value:
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rd_ctrl.v(line number: 216)] Elaborating instance u_mwr_data_rd_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/pgs_pciex4_prefetch_fifo_v1_2.v(line number: 8)] Elaborating module pgs_pciex4_prefetch_fifo_v1_2
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/u_mwr_data_rd_fifo} parameter value:
    D = 8'b10000000
    W = 32'b00000000000000000000000010000000
    TYPE = Distributed
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/pgs_pciex4_prefetch_fifo_v1_2.v(line number: 84)] Elaborating instance pgs_pciex4_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_v1_2.v(line number: 8)] Elaborating module pgs_pciex4_fifo_v1_2
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/u_mwr_data_rd_fifo/genblk1.pgs_pciex4_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000111
    DATA_WIDTH = 32'b00000000000000000000000010000000
    OUT_REG = 32'b00000000000000000000000000000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_v1_2.v(line number: 42)] Elaborating instance ipm_distributed_sdpram_distributed_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/ipm_distributed_sdpram_v1_2_distributed_fifo.v(line number: 22)] Elaborating module ipm_distributed_sdpram_v1_2_distributed_fifo
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/u_mwr_data_rd_fifo/genblk1.pgs_pciex4_fifo/ipm_distributed_sdpram_distributed_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000111
    DATA_WIDTH = 32'b00000000000000000000000010000000
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    INIT_FILE = NONE
    FILE_FORMAT = BIN
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_v1_2.v(line number: 57)] Elaborating instance pgs_pciex4_fifo_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_ctrl.v(line number: 8)] Elaborating module pgs_pciex4_fifo_ctrl
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/u_mwr_data_rd_fifo/genblk1.pgs_pciex4_fifo/pgs_pciex4_fifo_ctrl} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v(line number: 144)] Elaborating instance u_ips2l_pcie_dma_tx_mwr_rd_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_mwr_rd_ctrl.v(line number: 15)] Elaborating module ips2l_pcie_dma_tx_mwr_rd_ctrl
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl} parameter value:
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_mwr_rd_ctrl.v(line number: 101)] Elaborating instance u_ips2l_pcie_dma_mwr_rd_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_rd_ctrl.v(line number: 15)] Elaborating module ips2l_pcie_dma_rd_ctrl
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl} parameter value:
    ADDR_WIDTH = 4'b1100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v(line number: 165)] Elaborating instance u_ips2l_pcie_dma_cpld_tx_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_cpld_tx_ctrl.v(line number: 15)] Elaborating module ips2l_pcie_dma_cpld_tx_ctrl
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_cpld_tx_ctrl.v(line number: 128)] Elaborating instance u_cpld_req_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/pgs_pciex4_prefetch_fifo_v1_2.v(line number: 8)] Elaborating module pgs_pciex4_prefetch_fifo_v1_2
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/u_cpld_req_fifo} parameter value:
    D = 7'b1000000
    W = 32'b00000000000000000000000001101000
    TYPE = Distributed
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/pgs_pciex4_prefetch_fifo_v1_2.v(line number: 84)] Elaborating instance pgs_pciex4_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_v1_2.v(line number: 8)] Elaborating module pgs_pciex4_fifo_v1_2
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/u_cpld_req_fifo/genblk1.pgs_pciex4_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000110
    DATA_WIDTH = 32'b00000000000000000000000001101000
    OUT_REG = 32'b00000000000000000000000000000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_v1_2.v(line number: 42)] Elaborating instance ipm_distributed_sdpram_distributed_fifo
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/ipm_distributed_sdpram_v1_2_distributed_fifo.v(line number: 22)] Elaborating module ipm_distributed_sdpram_v1_2_distributed_fifo
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/u_cpld_req_fifo/genblk1.pgs_pciex4_fifo/ipm_distributed_sdpram_distributed_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000110
    DATA_WIDTH = 32'b00000000000000000000000001101000
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    INIT_FILE = NONE
    FILE_FORMAT = BIN
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_v1_2.v(line number: 57)] Elaborating instance pgs_pciex4_fifo_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/pgs_pciex4_fifo_ctrl.v(line number: 8)] Elaborating module pgs_pciex4_fifo_ctrl
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/u_cpld_req_fifo/genblk1.pgs_pciex4_fifo/pgs_pciex4_fifo_ctrl} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v(line number: 202)] Elaborating instance u_ips2l_pcie_dma_mrd_tx_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mrd_tx_ctrl.v(line number: 15)] Elaborating module ips2l_pcie_dma_mrd_tx_ctrl
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_tx_top.v(line number: 235)] Elaborating instance u_ips2l_pcie_dma_mwr_tx_ctrl
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mwr_tx_ctrl.v(line number: 15)] Elaborating module ips2l_pcie_dma_mwr_tx_ctrl
I: Module instance {pcie_dma_test/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl} parameter value:
    DEVICE_TYPE = 3'b000
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1387)] Width mismatch between port bar0_rd_addr and signal bound to it for instantiated module ips2l_pcie_dma
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1769)] Elaborating instance u_ips2l_pcie_wrap
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/pcie_test.v(line number: 16)] Elaborating module pcie_test
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/pcie_test.v(line number: 531)] Elaborating instance U_IPS2L_PCIE_TOP
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_top_v1_8.v(line number: 11)] Elaborating module ips2l_pcie_top_v1_8
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP} parameter value:
    DEVICE_TYPE = 3'b000
    DIAG_CTRL_BUS_B2 = NORMAL
    BAR_RESIZABLE = 32'b00000000000000000000000000000000
    NUM_OF_RBARS = 32'b00000000000000000000000000000011
    BAR_INDEX_0 = 32'b00000000000000000000000000000000
    BAR_INDEX_1 = 32'b00000000000000000000000000000001
    BAR_INDEX_2 = 32'b00000000000000000000000000000010
    TPH_DISABLE = TRUE
    MSIX_CAP_DISABLE = TRUE
    MSI_CAP_DISABLE = TRUE
    MSI_PVM_DISABLE = TRUE
    BAR_MASK_WRITABLE = 32'b00000000000000000000000000111111
    APP_DEV_NUM = 32'b00000000000000000000000000000000
    APP_BUS_NUM = 32'b00000000000000000000000000000000
    ATOMIC_DISABLE = TRUE
    HSST_LANE_NUM = 32'b00000000000000000000000000000010
    MAX_LINK_WIDTH = 6'b000010
    MAX_LINK_SPEED = 4'b0010
    LINK_CAPABLE = 6'b000011
    SCRAMBLE_DISABLE = 1'b0
    AUTO_LANE_FLIP_CTRL_EN = 1'b0
    NUM_OF_LANES = 5'b00001
    MAX_PAYLOAD_SIZE = 3'b011
    INT_DISABLE = 1'b1
    PVM_SUPPORT = 1'b0
    MSI_64_BIT_ADDR_CAP = 1'b0
    MSI_MULTIPLE_MSG_CAP = 3'b000
    MSI_ENABLE = 1'b0
    MSI_CAP_NEXT_OFFSET = 8'b01110000
    CAP_POINTER = 8'b01110000
    PCIE_CAP_NEXT_PTR = 8'b00000000
    VENDOR_ID = 16'b0000011101010101
    DEVICE_ID = 16'b0000011101010101
    BASE_CLASS_CODE = 8'b00000101
    SUBCLASS_CODE = 8'b10000000
    PROGRAM_INTERFACE = 8'b00000000
    REVISION_ID = 8'b00000000
    SUBSYS_DEV_ID = 16'b0000000000000000
    SUBSYS_VENDOR_ID = 16'b0000000000000000
    BAR0_PREFETCH = 1'b0
    BAR0_TYPE = 2'b00
    BAR0_MEM_IO = 1'b0
    BAR0_ENABLED = 1'b1
    BAR0_MASK = 31'b0000000000000000111111111111111
    BAR1_PREFETCH = 1'b0
    BAR1_TYPE = 2'b00
    BAR1_MEM_IO = 1'b0
    BAR1_ENABLED = 1'b1
    BAR1_MASK = 31'b0000000000111111111111111111111
    BAR2_PREFETCH = 1'b0
    BAR2_TYPE = 2'b00
    BAR2_MEM_IO = 1'b0
    BAR2_ENABLED = 1'b0
    BAR2_MASK = 31'b0000000000000000000000000000000
    BAR3_PREFETCH = 1'b0
    BAR3_TYPE = 2'b00
    BAR3_MEM_IO = 1'b0
    BAR3_ENABLED = 1'b0
    BAR3_MASK = 31'b0000000000000000000000000000000
    BAR4_PREFETCH = 1'b0
    BAR4_TYPE = 2'b00
    BAR4_MEM_IO = 1'b0
    BAR4_ENABLED = 1'b0
    BAR4_MASK = 31'b0000000000000000000000000000000
    BAR5_PREFETCH = 1'b0
    BAR5_TYPE = 2'b00
    BAR5_MEM_IO = 1'b0
    BAR5_ENABLED = 1'b0
    BAR5_MASK = 31'b0000000000000000000000000000000
    ROM_BAR_ENABLE = 1'b0
    ROM_BAR_ENABLED = 1'b0
    ROM_MASK = 31'b0000000000000000000000000000000
    DO_DESKEW_FOR_SRIS = 1'b1
    PCIE_CAP_HW_AUTO_SPEED_DISABLE = 1'b0
    TARGET_LINK_SPEED = 4'b0010
    ECRC_CHECK_EN = 1'b1
    ECRC_GEN_EN = 1'b0
    EXT_TAG_EN = 1'b1
    EXT_TAG_SUPP = 1'b1
    PCIE_CAP_RCB = 1'b1
    PCIE_CAP_CRS = 1'b0
    PCIE_CAP_ATOMIC_EN = 1'b0
    PCI_MSIX_ENABLE = 1'b0
    PCI_FUNCTION_MASK = 1'b0
    PCI_MSIX_TABLE_SIZE = 11'b00000000001
    PCI_MSIX_CPA_NEXT_OFFSET = 8'b00000000
    PCI_MSIX_TABLE_OFFSET = 29'b00000000000000000000000000000
    PCI_MSIX_BIR = 3'b000
    PCI_MSIX_PBA_OFFSET = 29'b00000000000000000000000000000
    PCI_MSIX_PBA_BIR = 3'b000
    AER_CAP_NEXT_OFFSET = 12'b000000000000
    TPH_REQ_NEXT_PTR = 12'b000000000000
    RESBAR_BAR0_MAX_SUPP_SIZE = 20'b11111111111111111111
    RESBAR_BAR0_INIT_SIZE = 5'b00000
    RESBAR_BAR1_MAX_SUPP_SIZE = 20'b11111111111111111111
    RESBAR_BAR1_INIT_SIZE = 5'b00000
    RESBAR_BAR2_MAX_SUPP_SIZE = 20'b11111111111111111111
    RESBAR_BAR2_INIT_SIZE = 5'b00000
    CPLQ_MANAGEMENT_ENABLE = 1'b1
    UPCONFIGURE_SUPPORT = 1'b1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_top_v1_8.v(line number: 331)] Elaborating instance u_core_rstn_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_top_v1_8.v(line number: 342)] Elaborating instance u_pcie_apb_mux
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_mux_v1_0.v(line number: 11)] Elaborating module ips2l_pcie_apb_mux_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_mux_v1_0.v(line number: 81)] Elaborating instance u_pcie_apb_cross
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb_cross_v1_0.v(line number: 11)] Elaborating module ips2l_pcie_apb_cross_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_top_v1_8.v(line number: 486)] Elaborating instance U_IPS2L_PCIE_HARD_CTRL
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v(line number: 11)] Elaborating module ips2l_pcie_hard_ctrl_v1_8
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL} parameter value:
    DEVICE_TYPE = 3'b000
    DEBUG_INFO_DW = 32'b00000000000000000000000010000101
    TP = 32'b00000000000000000000000000000010
    GRS_EN = FALSE
    PIN_MUX_INT_FORCE_EN = FALSE
    PIN_MUX_INT_DISABLE = FALSE
    DIAG_CTRL_BUS_B2 = NORMAL
    DYN_DEBUG_SEL_EN = TRUE
    DEBUG_INFO_SEL = 32'b00000000000000000000000000000000
    BAR_RESIZABLE = 32'b00000000000000000000000000000000
    NUM_OF_RBARS = 32'b00000000000000000000000000000011
    BAR_INDEX_0 = 32'b00000000000000000000000000000000
    BAR_INDEX_1 = 32'b00000000000000000000000000000001
    BAR_INDEX_2 = 32'b00000000000000000000000000000010
    TPH_DISABLE = TRUE
    MSIX_CAP_DISABLE = TRUE
    MSI_CAP_DISABLE = TRUE
    MSI_PVM_DISABLE = TRUE
    BAR_MASK_WRITABLE = 32'b00000000000000000000000000111111
    APP_DEV_NUM = 32'b00000000000000000000000000000000
    APP_BUS_NUM = 32'b00000000000000000000000000000000
    RAM_MUX_EN = TRUE
    ATOMIC_DISABLE = TRUE
    MAX_LINK_WIDTH = 6'b000010
    MAX_LINK_SPEED = 4'b0010
    LINK_CAPABLE = 6'b000011
    SCRAMBLE_DISABLE = 1'b0
    AUTO_LANE_FLIP_CTRL_EN = 1'b0
    NUM_OF_LANES = 5'b00001
    MAX_PAYLOAD_SIZE = 3'b011
    INT_DISABLE = 1'b1
    PVM_SUPPORT = 1'b0
    MSI_64_BIT_ADDR_CAP = 1'b0
    MSI_MULTIPLE_MSG_CAP = 3'b000
    MSI_ENABLE = 1'b0
    MSI_CAP_NEXT_OFFSET = 8'b01110000
    CAP_POINTER = 8'b01110000
    PCIE_CAP_NEXT_PTR = 8'b00000000
    VENDOR_ID = 16'b0000011101010101
    DEVICE_ID = 16'b0000011101010101
    BASE_CLASS_CODE = 8'b00000101
    SUBCLASS_CODE = 8'b10000000
    PROGRAM_INTERFACE = 8'b00000000
    REVISION_ID = 8'b00000000
    SUBSYS_DEV_ID = 16'b0000000000000000
    SUBSYS_VENDOR_ID = 16'b0000000000000000
    BAR0_PREFETCH = 1'b0
    BAR0_TYPE = 2'b00
    BAR0_MEM_IO = 1'b0
    BAR0_ENABLED = 1'b1
    BAR0_MASK = 31'b0000000000000000111111111111111
    BAR1_PREFETCH = 1'b0
    BAR1_TYPE = 2'b00
    BAR1_MEM_IO = 1'b0
    BAR1_ENABLED = 1'b1
    BAR1_MASK = 31'b0000000000111111111111111111111
    BAR2_PREFETCH = 1'b0
    BAR2_TYPE = 2'b00
    BAR2_MEM_IO = 1'b0
    BAR2_ENABLED = 1'b0
    BAR2_MASK = 31'b0000000000000000000000000000000
    BAR3_PREFETCH = 1'b0
    BAR3_TYPE = 2'b00
    BAR3_MEM_IO = 1'b0
    BAR3_ENABLED = 1'b0
    BAR3_MASK = 31'b0000000000000000000000000000000
    BAR4_PREFETCH = 1'b0
    BAR4_TYPE = 2'b00
    BAR4_MEM_IO = 1'b0
    BAR4_ENABLED = 1'b0
    BAR4_MASK = 31'b0000000000000000000000000000000
    BAR5_PREFETCH = 1'b0
    BAR5_TYPE = 2'b00
    BAR5_MEM_IO = 1'b0
    BAR5_ENABLED = 1'b0
    BAR5_MASK = 31'b0000000000000000000000000000000
    ROM_BAR_ENABLE = 1'b0
    ROM_BAR_ENABLED = 1'b0
    ROM_MASK = 31'b0000000000000000000000000000000
    DO_DESKEW_FOR_SRIS = 1'b1
    PCIE_CAP_HW_AUTO_SPEED_DISABLE = 1'b0
    TARGET_LINK_SPEED = 4'b0010
    ECRC_CHECK_EN = 1'b1
    ECRC_GEN_EN = 1'b0
    EXT_TAG_EN = 1'b1
    EXT_TAG_SUPP = 1'b1
    PCIE_CAP_RCB = 1'b1
    PCIE_CAP_CRS = 1'b0
    PCIE_CAP_ATOMIC_EN = 1'b0
    PCI_MSIX_ENABLE = 1'b0
    PCI_FUNCTION_MASK = 1'b0
    PCI_MSIX_TABLE_SIZE = 11'b00000000001
    PCI_MSIX_CPA_NEXT_OFFSET = 8'b00000000
    PCI_MSIX_TABLE_OFFSET = 29'b00000000000000000000000000000
    PCI_MSIX_BIR = 3'b000
    PCI_MSIX_PBA_OFFSET = 29'b00000000000000000000000000000
    PCI_MSIX_PBA_BIR = 3'b000
    AER_CAP_NEXT_OFFSET = 12'b000000000000
    TPH_REQ_NEXT_PTR = 12'b000000000000
    RESBAR_BAR0_MAX_SUPP_SIZE = 20'b11111111111111111111
    RESBAR_BAR0_INIT_SIZE = 5'b00000
    RESBAR_BAR1_MAX_SUPP_SIZE = 20'b11111111111111111111
    RESBAR_BAR1_INIT_SIZE = 5'b00000
    RESBAR_BAR2_MAX_SUPP_SIZE = 20'b11111111111111111111
    RESBAR_BAR2_INIT_SIZE = 5'b00000
    CPLQ_MANAGEMENT_ENABLE = 1'b1
    UPCONFIGURE_SUPPORT = 1'b1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v(line number: 424)] Elaborating instance mem_button_rstn_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v(line number: 426)] Elaborating instance pcie2_iip_exrcvdata_rams
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rcv_data_ram.v(line number: 18)] Elaborating module rcv_data_ram
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rcv_data_ram.v(line number: 145)] Elaborating instance U_ipm2l_sdpram_rcv_data_ram
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 20)] Elaborating module ipm2l_sdpram_v1_0_rcv_data_ram
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram} parameter value:
    c_CAS_MODE = 18K
    c_WR_ADDR_WIDTH = 32'b00000000000000000000000000001010
    c_WR_DATA_WIDTH = 32'b00000000000000000000000001001000
    c_RD_ADDR_WIDTH = 32'b00000000000000000000000000001010
    c_RD_DATA_WIDTH = 32'b00000000000000000000000001001000
    c_WR_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_WR_CLK_EN = 32'b00000000000000000000000000000000
    c_OUTPUT_REG = 32'b00000000000000000000000000000001
    c_RD_OCE_EN = 32'b00000000000000000000000000000000
    c_RD_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_RD_CLK_EN = 32'b00000000000000000000000000000000
    c_RESET_TYPE = ASYNC
    c_RD_CLK_OR_POL_INV = 32'b00000000000000000000000000000000
    c_POWER_OPT = 32'b00000000000000000000000000000000
    c_INIT_FILE = NONE
    c_INIT_FORMAT = BIN
    c_WR_BYTE_EN = 32'b00000000000000000000000000000000
    c_BE_WIDTH = 32'b00000000000000000000000000000100
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 445)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 446)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 454)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 455)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 456)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 458)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 454)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 455)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 456)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 458)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 454)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 455)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 456)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 458)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 454)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 455)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 456)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 458)] Case condition never applies
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 559)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 564)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 565)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 566)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 567)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 567)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 568)] Case condition never applies
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 796)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 796)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 796)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v(line number: 796)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v(line number: 438)] Elaborating instance pcie2_iip_exrcvhdr_rams
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rcv_header_ram.v(line number: 18)] Elaborating module rcv_header_ram
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rcv_header_ram.v(line number: 145)] Elaborating instance U_ipm2l_sdpram_rcv_header_ram
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 20)] Elaborating module ipm2l_sdpram_v1_0_rcv_header_ram
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvhdr_rams/U_ipm2l_sdpram_rcv_header_ram} parameter value:
    c_CAS_MODE = 18K
    c_WR_ADDR_WIDTH = 32'b00000000000000000000000000001001
    c_WR_DATA_WIDTH = 32'b00000000000000000000000010010000
    c_RD_ADDR_WIDTH = 32'b00000000000000000000000000001001
    c_RD_DATA_WIDTH = 32'b00000000000000000000000010010000
    c_WR_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_WR_CLK_EN = 32'b00000000000000000000000000000000
    c_OUTPUT_REG = 32'b00000000000000000000000000000001
    c_RD_OCE_EN = 32'b00000000000000000000000000000000
    c_RD_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_RD_CLK_EN = 32'b00000000000000000000000000000000
    c_RESET_TYPE = ASYNC
    c_RD_CLK_OR_POL_INV = 32'b00000000000000000000000000000000
    c_POWER_OPT = 32'b00000000000000000000000000000000
    c_INIT_FILE = NONE
    c_INIT_FORMAT = BIN
    c_WR_BYTE_EN = 32'b00000000000000000000000000000000
    c_BE_WIDTH = 32'b00000000000000000000000000000100
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 445)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 446)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 454)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 455)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 456)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 458)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 458)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 459)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 454)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 455)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 456)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 458)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 458)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 459)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 454)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 455)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 456)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 458)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 458)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 459)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 454)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 455)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 456)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 457)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 458)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 458)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 459)] Case condition never applies
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 559)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 564)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 565)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 566)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 567)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 567)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 568)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 568)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 569)] Case condition never applies
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 796)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 796)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 796)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v(line number: 796)] Elaborating instance U_GTP_DRM18K_E1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v(line number: 450)] Elaborating instance pcie2_iip_exretry_rams
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/retry_data_ram.v(line number: 18)] Elaborating module retry_data_ram
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/retry_data_ram.v(line number: 119)] Elaborating instance U_ipml_spram_retry_data_ram
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 19)] Elaborating module ipm2l_spram_v1_0_retry_data_ram
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exretry_rams/U_ipml_spram_retry_data_ram} parameter value:
    c_CAS_MODE = 18K
    c_ADDR_WIDTH = 32'b00000000000000000000000000001011
    c_DATA_WIDTH = 32'b00000000000000000000000001001000
    c_OUTPUT_REG = 32'b00000000000000000000000000000001
    c_RD_OCE_EN = 32'b00000000000000000000000000000000
    c_CLK_EN = 32'b00000000000000000000000000000000
    c_ADDR_STROBE_EN = 32'b00000000000000000000000000000000
    c_RESET_TYPE = ASYNC
    c_POWER_OPT = 32'b00000000000000000000000000000000
    c_CLK_OR_POL_INV = 32'b00000000000000000000000000000000
    c_INIT_FILE = NONE
    c_INIT_FORMAT = BIN
    c_WR_BYTE_EN = 32'b00000000000000000000000000000000
    c_BE_WIDTH = 32'b00000000000000000000000000000100
    c_RAM_MODE = SINGLE_PORT
    c_WRITE_MODE = NORMAL_WRITE
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 231)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2039: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 233)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 243)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 247)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 251)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 255)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 243)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 247)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 251)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 255)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 243)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 247)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 251)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 255)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 243)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 247)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 251)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 255)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 243)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 247)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 251)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 255)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 243)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 247)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 251)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 255)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 243)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 247)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 251)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 255)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 243)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 247)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 251)] Case condition never applies
W: Verilog-2038: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 255)] Case condition never applies
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 563)] Elaborating instance U_GTP_DRM18K
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 563)] Elaborating instance U_GTP_DRM18K
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 563)] Elaborating instance U_GTP_DRM18K
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 563)] Elaborating instance U_GTP_DRM18K
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 563)] Elaborating instance U_GTP_DRM18K
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 563)] Elaborating instance U_GTP_DRM18K
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 563)] Elaborating instance U_GTP_DRM18K
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 563)] Elaborating instance U_GTP_DRM18K
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[9] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[10] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[11] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[12] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[13] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[14] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[15] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[16] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[17] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[27] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[28] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[29] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[30] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[31] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[32] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[33] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[34] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[35] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[45] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[46] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[47] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[48] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[49] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[50] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[51] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[52] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[53] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[63] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[64] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[65] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[66] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[67] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[68] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[69] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[70] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[71] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[81] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[82] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[83] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[84] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[85] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[86] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[87] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[88] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[89] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[99] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[100] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[101] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[102] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[103] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[104] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[105] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[106] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[107] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[117] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[118] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[119] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[120] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[121] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[122] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[123] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[124] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[125] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[135] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[136] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[137] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[138] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[139] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[140] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[141] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[142] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 381)] Net DA_bus[143] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[9] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[10] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[11] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[12] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[13] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[14] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[15] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[16] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[17] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[27] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[28] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[29] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[30] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[31] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[32] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[33] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[34] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[35] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[45] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[46] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[47] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[48] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[49] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[50] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[51] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[52] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[53] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[63] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[64] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[65] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[66] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[67] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[68] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[69] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[70] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[71] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[81] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[82] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[83] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[84] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[85] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[86] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[87] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[88] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[89] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[99] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[100] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[101] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[102] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[103] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[104] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[105] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[106] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[107] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[117] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[118] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[119] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[120] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[121] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[122] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[123] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[124] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[125] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[135] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[136] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[137] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[138] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[139] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[140] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[141] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[142] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v(line number: 382)] Net DB_bus[143] in ipm2l_spram_v1_0_retry_data_ram(original module ipm2l_spram_v1_0_retry_data_ram) does not have a driver, tie it to 0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v(line number: 461)] Elaborating instance u_pcie_seio
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_seio_intf_v1_2.v(line number: 11)] Elaborating module ips2l_pcie_seio_intf_v1_2
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v(line number: 473)] Elaborating instance tx_rst_done_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v(line number: 563)] Elaborating instance U_IPS2L_PCIE_CFG_SPACE_INIT
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_cfg_init_v1_7.v(line number: 11)] Elaborating module ips2l_pcie_cfg_init_v1_7
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT} parameter value:
    DEVICE_TYPE = 3'b000
    MAX_LINK_WIDTH = 6'b000010
    MAX_LINK_SPEED = 4'b0010
    LINK_CAPABLE = 6'b000011
    SCRAMBLE_DISABLE = 1'b0
    AUTO_LANE_FLIP_CTRL_EN = 1'b0
    NUM_OF_LANES = 5'b00001
    MAX_PAYLOAD_SIZE = 3'b011
    INT_DISABLE = 1'b1
    PVM_SUPPORT = 1'b0
    MSI_64_BIT_ADDR_CAP = 1'b0
    MSI_MULTIPLE_MSG_CAP = 3'b000
    MSI_ENABLE = 1'b0
    MSI_CAP_NEXT_OFFSET = 8'b01110000
    CAP_POINTER = 8'b01110000
    PCIE_CAP_NEXT_PTR = 8'b00000000
    VENDOR_ID = 16'b0000011101010101
    DEVICE_ID = 16'b0000011101010101
    BASE_CLASS_CODE = 8'b00000101
    SUBCLASS_CODE = 8'b10000000
    PROGRAM_INTERFACE = 8'b00000000
    REVISION_ID = 8'b00000000
    SUBSYS_DEV_ID = 16'b0000000000000000
    SUBSYS_VENDOR_ID = 16'b0000000000000000
    BAR0_PREFETCH = 1'b0
    BAR0_TYPE = 2'b00
    BAR0_MEM_IO = 1'b0
    BAR0_ENABLED = 1'b1
    BAR0_MASK = 31'b0000000000000000111111111111111
    BAR1_PREFETCH = 1'b0
    BAR1_TYPE = 2'b00
    BAR1_MEM_IO = 1'b0
    BAR1_ENABLED = 1'b1
    BAR1_MASK = 31'b0000000000111111111111111111111
    BAR2_PREFETCH = 1'b0
    BAR2_TYPE = 2'b00
    BAR2_MEM_IO = 1'b0
    BAR2_ENABLED = 1'b0
    BAR2_MASK = 31'b0000000000000000000000000000000
    BAR3_PREFETCH = 1'b0
    BAR3_TYPE = 2'b00
    BAR3_MEM_IO = 1'b0
    BAR3_ENABLED = 1'b0
    BAR3_MASK = 31'b0000000000000000000000000000000
    BAR4_PREFETCH = 1'b0
    BAR4_TYPE = 2'b00
    BAR4_MEM_IO = 1'b0
    BAR4_ENABLED = 1'b0
    BAR4_MASK = 31'b0000000000000000000000000000000
    BAR5_PREFETCH = 1'b0
    BAR5_TYPE = 2'b00
    BAR5_MEM_IO = 1'b0
    BAR5_ENABLED = 1'b0
    BAR5_MASK = 31'b0000000000000000000000000000000
    ROM_BAR_ENABLE = 1'b0
    ROM_BAR_ENABLED = 1'b0
    ROM_MASK = 31'b0000000000000000000000000000000
    DO_DESKEW_FOR_SRIS = 1'b1
    PCIE_CAP_HW_AUTO_SPEED_DISABLE = 1'b0
    TARGET_LINK_SPEED = 4'b0010
    ECRC_CHECK_EN = 1'b1
    ECRC_GEN_EN = 1'b0
    EXT_TAG_EN = 1'b1
    EXT_TAG_SUPP = 1'b1
    PCIE_CAP_RCB = 1'b1
    PCIE_CAP_CRS = 1'b0
    PCIE_CAP_ATOMIC_EN = 1'b0
    PCI_MSIX_ENABLE = 1'b0
    PCI_FUNCTION_MASK = 1'b0
    PCI_MSIX_TABLE_SIZE = 11'b00000000001
    PCI_MSIX_CPA_NEXT_OFFSET = 8'b00000000
    PCI_MSIX_TABLE_OFFSET = 29'b00000000000000000000000000000
    PCI_MSIX_BIR = 3'b000
    PCI_MSIX_PBA_OFFSET = 29'b00000000000000000000000000000
    PCI_MSIX_PBA_BIR = 3'b000
    AER_CAP_NEXT_OFFSET = 12'b000000000000
    TPH_REQ_NEXT_PTR = 12'b000000000000
    RESBAR_BAR0_MAX_SUPP_SIZE = 20'b11111111111111111111
    RESBAR_BAR0_INIT_SIZE = 5'b00000
    RESBAR_BAR1_MAX_SUPP_SIZE = 20'b11111111111111111111
    RESBAR_BAR1_INIT_SIZE = 5'b00000
    RESBAR_BAR2_MAX_SUPP_SIZE = 20'b11111111111111111111
    RESBAR_BAR2_INIT_SIZE = 5'b00000
    CPLQ_MANAGEMENT_ENABLE = 1'b1
    UPCONFIGURE_SUPPORT = 1'b1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v(line number: 583)] Elaborating instance U_APB2DBI
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_apb2dbi_v1_1.v(line number: 11)] Elaborating module ips2l_pcie_apb2dbi_v1_1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_hard_ctrl_v1_8.v(line number: 646)] Elaborating instance u_gtp_pcie
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_top_v1_8.v(line number: 652)] Elaborating instance U_IPS2L_HSSTLP_PCIE_SOFT_PHY
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 11)] Elaborating module ips2l_pcie_soft_phy_v1_3
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY} parameter value:
    HSST_LANE_NUM = 32'b00000000000000000000000000000010
    EN_CONTI_SKP_REPLACE = 1'b0
    PW = 32'b00000000000000000000000101011011
    PW_PMA_RX = 32'b00000000000000000000000110001111
    PW_PMA_TX = 32'b00000000000000000000000110000101
    PW_QUAD = 32'b00000000000000000000000100000011
    TX_DATA_WIDTH = 32'b00000000000000000000000000100000
    ENCODER_TYPE = normal
    COM = 8'b10111100
    SKP = 8'b00011100
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 537)] Elaborating instance rdata_proc_0
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_phy_mac_rdata_proc.v(line number: 6)] Elaborating module hsstl_phy_mac_rdata_proc
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/rdata_proc_0} parameter value:
    EN_CONTI_SKP_REPLACE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 554)] Elaborating instance rdata_proc_1
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_phy_mac_rdata_proc.v(line number: 6)] Elaborating module hsstl_phy_mac_rdata_proc
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/genblk5.rdata_proc_1} parameter value:
    EN_CONTI_SKP_REPLACE = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 781)] Elaborating instance u_clkbufg
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 789)] Elaborating instance phy_rstn_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 791)] Elaborating instance button_rstn_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 877)] Elaborating instance hsst_pciex4_sync_rate_done
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/ips_hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module ips_hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 888)] Elaborating instance hsst_pciex4_sync_hsst_ch_ready
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/ips_hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module ips_hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 888)] Elaborating instance hsst_pciex4_sync_hsst_ch_ready
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/ips_hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module ips_hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 1000)] Elaborating instance hsst_pciex4_rst
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v(line number: 6)] Elaborating module hsstl_rst4mcrsw_v1_0
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst} parameter value:
    LINK_X1_WIDTH = 32'b00000000000000000000000000000001
    FORCE_LANE_REV = 32'b00000000000000000000000000000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v(line number: 113)] Elaborating instance ext_rstn_debounce
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_cross_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_cross_sync_v1_0
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce} parameter value:
    RST_CNTR_WIDTH = 32'b00000000000000000000000000010000
    RST_CNTR_VALUE = 16'b1100000000000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v(line number: 115)] Elaborating instance mac_clk_req_n_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v(line number: 121)] Elaborating instance rate_multi_sw_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v(line number: 122)] Elaborating instance st_recvr_multi_sw_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v(line number: 124)] Elaborating instance hsst_tx_rst_mcrsw
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v(line number: 6)] Elaborating module hsstl_rst4mcrsw_tx_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v(line number: 66)] Elaborating instance pll_lock_multi_sw_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v(line number: 69)] Elaborating instance pll_lock_multi_sw_deb
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_debounce_v1_0.v(line number: 6)] Elaborating module hsst_rst_debounce_v1_0
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/pll_lock_multi_sw_deb} parameter value:
    RISE_CNTR_WIDTH = 32'b00000000000000000000000000001100
    RISE_CNTR_VALUE = 32'b00000000000000000000100000000000
    ACTIVE_HIGH = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v(line number: 72)] Elaborating instance pll_lock_multi_sw_wtchdg
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_wtchdg_v1_0.v(line number: 6)] Elaborating module hsst_rst_wtchdg_v1_0
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/pll_lock_multi_sw_wtchdg} parameter value:
    ACTIVE_HIGH = 32'b00000000000000000000000000000000
    WTCHDG_CNTR1_WIDTH = 32'b00000000000000000000000000001010
    WTCHDG_CNTR2_WIDTH = 32'b00000000000000000000000000001010
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v(line number: 74)] Elaborating instance tx_rst_fsm_multi_sw_lane
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_tx_rst_fsm_v1_1.v(line number: 6)] Elaborating module hsstl_rst4mcrsw_tx_rst_fsm_v1_1
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v(line number: 170)] Elaborating instance hsst_rx_rst_mcrsw
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v(line number: 6)] Elaborating module hsstl_rst4mcrsw_rx_v1_0
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw} parameter value:
    LINK_X1_WIDTH = 32'b00000000000000000000000000000001
    FORCE_LANE_REV = 32'b00000000000000000000000000000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v(line number: 92)] Elaborating instance link_num_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v(line number: 118)] Elaborating instance hsst_rst4mcrsw_rx_init
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v(line number: 6)] Elaborating module hsstl_rst4mcrsw_rx_init_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v(line number: 45)] Elaborating instance loss_signal_multi_sw_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v(line number: 46)] Elaborating instance cdr_align_multi_sw_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v(line number: 47)] Elaborating instance word_align_multi_sw_sync
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_sync_v1_0.v(line number: 6)] Elaborating module hsst_rst_sync_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v(line number: 51)] Elaborating instance loss_signal_multi_sw_deb
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_debounce_v1_0.v(line number: 6)] Elaborating module hsst_rst_debounce_v1_0
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb} parameter value:
    RISE_CNTR_WIDTH = 32'b00000000000000000000000000001100
    RISE_CNTR_VALUE = 32'b00000000000000000000000000000100
    ACTIVE_HIGH = 32'b00000000000000000000000000000001
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v(line number: 54)] Elaborating instance cdr_align_multi_sw_deb
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsst_rst_debounce_v1_0.v(line number: 6)] Elaborating module hsst_rst_debounce_v1_0
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb} parameter value:
    RISE_CNTR_WIDTH = 32'b00000000000000000000000000001100
    RISE_CNTR_VALUE = 32'b00000000000000000000100000000000
    ACTIVE_HIGH = 1'b0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v(line number: 57)] Elaborating instance rx_rst_initfsm_multi_sw_lane
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v(line number: 6)] Elaborating module hsstl_rst4mcrsw_rx_rst_initfsm_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v(line number: 118)] Elaborating instance hsst_rst4mcrsw_rx_init
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v(line number: 6)] Elaborating module hsstl_rst4mcrsw_rx_init_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v(line number: 118)] Elaborating instance hsst_rst4mcrsw_rx_init
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v(line number: 6)] Elaborating module hsstl_rst4mcrsw_rx_init_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v(line number: 118)] Elaborating instance hsst_rst4mcrsw_rx_init
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v(line number: 6)] Elaborating module hsstl_rst4mcrsw_rx_init_v1_0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v(line number: 161)] Elaborating instance rx_rst_fsm_multi_sw_lane
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_fsm_v1_0.v(line number: 6)] Elaborating module hsstl_rst4mcrsw_rx_rst_fsm_v1_0
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane} parameter value:
    FORCE_LANE_REV = 32'b00000000000000000000000000000000
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v(line number: 70)] Net P_LX_RX_CKDIV_DYNSEL[1] in hsstl_rst4mcrsw_rx_v1_0(original module hsstl_rst4mcrsw_rx_v1_0) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v(line number: 70)] Net P_LX_RX_CKDIV_DYNSEL[2] in hsstl_rst4mcrsw_rx_v1_0(original module hsstl_rst4mcrsw_rx_v1_0) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v(line number: 70)] Net P_LX_RX_CKDIV_DYNSEL[3] in hsstl_rst4mcrsw_rx_v1_0(original module hsstl_rst4mcrsw_rx_v1_0) does not have a driver, tie it to 0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 1485)] Elaborating instance GTP_HSST_2LANE_TOP
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v(line number: 19)] Elaborating module ipm2l_pcie_hsstlp_x2_top
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v(line number: 1699)] Elaborating instance U_IPM2L_HSSTLP_RST
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_v1_6.v(line number: 16)] Elaborating module ipm2l_hsstlp_rst_v1_6
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_IPM2L_HSSTLP_RST} parameter value:
    INNER_RST_EN = FALSE
    FREE_CLOCK_FREQ = 10.000000
    CH0_TX_ENABLE = TRUE
    CH1_TX_ENABLE = TRUE
    CH2_TX_ENABLE = FALSE
    CH3_TX_ENABLE = FALSE
    CH0_RX_ENABLE = TRUE
    CH1_RX_ENABLE = TRUE
    CH2_RX_ENABLE = FALSE
    CH3_RX_ENABLE = FALSE
    CH0_MULT_LANE_MODE = 32'b00000000000000000000000000000010
    CH1_MULT_LANE_MODE = 32'b00000000000000000000000000000010
    CH2_MULT_LANE_MODE = 32'b00000000000000000000000000000001
    CH3_MULT_LANE_MODE = 32'b00000000000000000000000000000001
    CH0_RXPCS_ALIGN_TIMER = 32'b00000000000000000111111111111111
    CH1_RXPCS_ALIGN_TIMER = 32'b00000000000000000111111111111111
    CH2_RXPCS_ALIGN_TIMER = 32'b00000000000000000111111111111111
    CH3_RXPCS_ALIGN_TIMER = 32'b00000000000000000111111111111111
    PCS_CH0_BYPASS_WORD_ALIGN = FALSE
    PCS_CH1_BYPASS_WORD_ALIGN = FALSE
    PCS_CH2_BYPASS_WORD_ALIGN = TRUE
    PCS_CH3_BYPASS_WORD_ALIGN = TRUE
    PCS_CH0_BYPASS_BONDING = TRUE
    PCS_CH1_BYPASS_BONDING = TRUE
    PCS_CH2_BYPASS_BONDING = TRUE
    PCS_CH3_BYPASS_BONDING = TRUE
    PCS_CH0_BYPASS_CTC = FALSE
    PCS_CH1_BYPASS_CTC = FALSE
    PCS_CH2_BYPASS_CTC = TRUE
    PCS_CH3_BYPASS_CTC = TRUE
    P_LX_TX_CKDIV_0 = 32'b00000000000000000000000000000010
    P_LX_TX_CKDIV_1 = 32'b00000000000000000000000000000010
    P_LX_TX_CKDIV_2 = 32'b00000000000000000000000000000000
    P_LX_TX_CKDIV_3 = 32'b00000000000000000000000000000000
    LX_RX_CKDIV_0 = 32'b00000000000000000000000000000010
    LX_RX_CKDIV_1 = 32'b00000000000000000000000000000010
    LX_RX_CKDIV_2 = 32'b00000000000000000000000000000000
    LX_RX_CKDIV_3 = 32'b00000000000000000000000000000000
    CH0_TX_PLL_SEL = 32'b00000000000000000000000000000000
    CH1_TX_PLL_SEL = 32'b00000000000000000000000000000000
    CH2_TX_PLL_SEL = 32'b00000000000000000000000000000000
    CH3_TX_PLL_SEL = 32'b00000000000000000000000000000000
    CH0_RX_PLL_SEL = 32'b00000000000000000000000000000000
    CH1_RX_PLL_SEL = 32'b00000000000000000000000000000000
    CH2_RX_PLL_SEL = 32'b00000000000000000000000000000000
    CH3_RX_PLL_SEL = 32'b00000000000000000000000000000000
    PLL_NUBER = 32'b00000000000000000000000000000001
    PCS_TX_CLK_EXPLL_USE_CH0 = FALSE
    PCS_TX_CLK_EXPLL_USE_CH1 = FALSE
    PCS_TX_CLK_EXPLL_USE_CH2 = FALSE
    PCS_TX_CLK_EXPLL_USE_CH3 = FALSE
    PCS_RX_CLK_EXPLL_USE_CH0 = TRUE
    PCS_RX_CLK_EXPLL_USE_CH1 = TRUE
    PCS_RX_CLK_EXPLL_USE_CH2 = FALSE
    PCS_RX_CLK_EXPLL_USE_CH3 = FALSE
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v(line number: 2321)] Elaborating instance U_GTP_HSSTLP_WRAPPER
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v(line number: 17)] Elaborating module ipm2l_hsstlp_wrapper_v1_6
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER} parameter value:
    PLL0_EN = TRUE
    PLL1_EN = FALSE
    CH0_EN = Fullduplex
    CH1_EN = Fullduplex
    CH2_EN = DISABLE
    CH3_EN = DISABLE
    CHANNEL0_EN = TRUE
    CHANNEL1_EN = TRUE
    CHANNEL2_EN = FALSE
    CHANNEL3_EN = FALSE
    TX_CHANNEL0_PLL = 32'b00000000000000000000000000000000
    TX_CHANNEL1_PLL = 32'b00000000000000000000000000000000
    TX_CHANNEL2_PLL = 32'b00000000000000000000000000000000
    TX_CHANNEL3_PLL = 32'b00000000000000000000000000000000
    RX_CHANNEL0_PLL = 32'b00000000000000000000000000000000
    RX_CHANNEL1_PLL = 32'b00000000000000000000000000000000
    RX_CHANNEL2_PLL = 32'b00000000000000000000000000000000
    RX_CHANNEL3_PLL = 32'b00000000000000000000000000000000
    CH0_MULT_LANE_MODE = 32'b00000000000000000000000000000010
    CH1_MULT_LANE_MODE = 32'b00000000000000000000000000000010
    CH2_MULT_LANE_MODE = 32'b00000000000000000000000000000001
    CH3_MULT_LANE_MODE = 32'b00000000000000000000000000000001
    PLL0_TXPCLK_PLL_SEL = 32'b00000000000000000000000000000000
    PLL1_TXPCLK_PLL_SEL = 32'b00000000000000000000000000000000
    PMA_PLL0_TX_SYNCK_PD = 32'b00000000000000000000000000000000
    PMA_PLL0_REG_REFCLK_TERM_IMP_CTRL = TRUE
    PMA_PLL0_REG_BG_TRIM = 32'b00000000000000000000000000000010
    PMA_PLL0_REG_IBUP_A1 = 32'b00000000000000111111111111111111
    PMA_PLL0_REG_IBUP_A2 = 32'b00000000000000000000110000000000
    PMA_PLL0_REG_IBUP_PD = 32'b00000000000000000000000000000000
    PMA_PLL0_REG_V2I_BIAS_SEL = FALSE
    PMA_PLL0_REG_V2I_EN = TRUE
    PMA_PLL0_REG_V2I_TB_SEL = 32'b00000000000000000000000000000000
    PMA_PLL0_REG_V2I_RCALTEST_PD = FALSE
    PMA_PLL0_REG_RES_CAL_TEST = 32'b00000000000000000000000000000000
    PMA_PLL0_RES_CAL_DIV = 32'b00000000000000000000000000000000
    PMA_PLL0_RES_CAL_CLK_SEL = FALSE
    PMA_PLL0_REG_PLL_PFDDELAY_EN = TRUE
    PMA_PLL0_REG_PFDDELAYSEL = 32'b00000000000000000000000000000001
    PMA_PLL0_REG_PLL_VCTRL_SET = 32'b00000000000000000000000000000000
    PMA_PLL0_REG_READY_OR_LOCK = FALSE
    PMA_PLL0_REG_PLL_CP = 32'b00000000000000000000000000011111
    PMA_PLL0_REG_PLL_REFDIV = 32'b00000000000000000000000000010000
    PMA_PLL0_REG_PLL_LOCKDET_EN = FALSE
    PMA_PLL0_REG_PLL_READY = FALSE
    PMA_PLL0_REG_PLL_READY_OW = FALSE
    PMA_PLL0_REG_PLL_FBDIV = 32'b00000000000000000000000000100111
    PMA_PLL0_REG_LPF_RES = 32'b00000000000000000000000000000001
    PMA_PLL0_REG_JTAG_OE = FALSE
    PMA_PLL0_REG_JTAG_VHYSTSEL = 32'b00000000000000000000000000000000
    PMA_PLL0_REG_PLL_LOCKDET_EN_OW = FALSE
    PMA_PLL0_REG_PLL_LOCKDET_FBCT = 32'b00000000000000000000000000000011
    PMA_PLL0_REG_PLL_LOCKDET_ITER = 32'b00000000000000000000000000000000
    PMA_PLL0_REG_PLL_LOCKDET_MODE = FALSE
    PMA_PLL0_REG_PLL_LOCKDET_LOCKCT = 32'b00000000000000000000000000000100
    PMA_PLL0_REG_PLL_LOCKDET_REFCT = 32'b00000000000000000000000000000011
    PMA_PLL0_REG_PLL_LOCKDET_RESET_N = TRUE
    PMA_PLL0_REG_PLL_LOCKDET_RESET_N_OW = FALSE
    PMA_PLL0_REG_PLL_LOCKED = FALSE
    PMA_PLL0_REG_PLL_LOCKED_OW = FALSE
    PMA_PLL0_REG_PLL_LOCKED_STICKY_CLEAR = FALSE
    PMA_PLL0_REG_PLL_UNLOCKED = FALSE
    PMA_PLL0_REG_PLL_UNLOCKDET_ITER = 32'b00000000000000000000000000000010
    PMA_PLL0_REG_PLL_UNLOCKED_OW = FALSE
    PMA_PLL0_REG_PLL_UNLOCKED_STICKY_CLEAR = FALSE
    PMA_PLL0_REG_I_CTRL_MAX = 32'b00000000000000000000000000111111
    PMA_PLL0_REG_REFCLK_TEST_EN = FALSE
    PMA_PLL0_REG_RESCAL_EN = FALSE
    PMA_PLL0_REG_I_CTRL_MIN = 32'b00000000000000000000000000000000
    PMA_PLL0_REG_RESCAL_DONE_OW = FALSE
    PMA_PLL0_REG_RESCAL_DONE_VAL = FALSE
    PMA_PLL0_REG_RESCAL_I_CODE = 32'b00000000000000000000000000101110
    PMA_PLL0_REG_RESCAL_I_CODE_OW = FALSE
    PMA_PLL0_REG_RESCAL_I_CODE_PMA = FALSE
    PMA_PLL0_REG_RESCAL_I_CODE_VAL = 32'b00000000000000000000000000101110
    PMA_PLL0_REG_RESCAL_INT_R_SMALL_OW = FALSE
    PMA_PLL0_REG_RESCAL_INT_R_SMALL_VAL = FALSE
    PMA_PLL0_REG_RESCAL_ITER_VALID_SEL = 32'b00000000000000000000000000000000
    PMA_PLL0_REG_RESCAL_RESET_N_OW = FALSE
    PMA_PLL0_REG_RESCAL_RST_N_VAL = FALSE
    PMA_PLL0_REG_RESCAL_WAIT_SEL = TRUE
    PMA_PLL0_REFCLK2LANE_PD_L = FALSE
    PMA_PLL0_REFCLK2LANE_PD_R = FALSE
    PMA_PLL0_REG_LOCKDET_REPEAT = FALSE
    PMA_PLL0_REG_NOFBCLK_STICKY_CLEAR = FALSE
    PMA_PLL0_REG_NOREFCLK_STICKY_CLEAR = FALSE
    PMA_PLL0_REG_TEST_SEL = 32'b00000000000000000000000000001111
    PMA_PLL0_REG_TEST_V_EN = FALSE
    PMA_PLL0_REG_TEST_SIG_HALF_EN = FALSE
    PMA_PLL0_REG_REFCLK_PAD_SEL = FALSE
    PMA_PLL0_PARM_PLL_POWERUP = ON
    PMA_PLL1_TX_SYNCK_PD = 32'b00000000000000000000000000000000
    PMA_PLL1_REG_REFCLK_TERM_IMP_CTRL = TRUE
    PMA_PLL1_REG_BG_TRIM = 32'b00000000000000000000000000000010
    PMA_PLL1_REG_IBUP_A1 = 32'b00000000000000111111111111111111
    PMA_PLL1_REG_IBUP_A2 = 32'b00000000000000000000110000000000
    PMA_PLL1_REG_IBUP_PD = 32'b00000000000000000000000000000000
    PMA_PLL1_REG_V2I_BIAS_SEL = FALSE
    PMA_PLL1_REG_V2I_EN = TRUE
    PMA_PLL1_REG_V2I_TB_SEL = 32'b00000000000000000000000000000000
    PMA_PLL1_REG_V2I_RCALTEST_PD = FALSE
    PMA_PLL1_REG_RES_CAL_TEST = 32'b00000000000000000000000000000000
    PMA_PLL1_RES_CAL_DIV = 32'b00000000000000000000000000000000
    PMA_PLL1_RES_CAL_CLK_SEL = FALSE
    PMA_PLL1_REG_PLL_PFDDELAY_EN = TRUE
    PMA_PLL1_REG_PFDDELAYSEL = 32'b00000000000000000000000000000001
    PMA_PLL1_REG_PLL_VCTRL_SET = 32'b00000000000000000000000000000000
    PMA_PLL1_REG_READY_OR_LOCK = FALSE
    PMA_PLL1_REG_PLL_CP = 32'b00000000000000000000000000011111
    PMA_PLL1_REG_PLL_REFDIV = 32'b00000000000000000000000000010000
    PMA_PLL1_REG_PLL_LOCKDET_EN = FALSE
    PMA_PLL1_REG_PLL_READY = FALSE
    PMA_PLL1_REG_PLL_READY_OW = FALSE
    PMA_PLL1_REG_PLL_FBDIV = 32'b00000000000000000000000000100100
    PMA_PLL1_REG_LPF_RES = 32'b00000000000000000000000000000001
    PMA_PLL1_REG_JTAG_OE = FALSE
    PMA_PLL1_REG_JTAG_VHYSTSEL = 32'b00000000000000000000000000000000
    PMA_PLL1_REG_PLL_LOCKDET_EN_OW = FALSE
    PMA_PLL1_REG_PLL_LOCKDET_FBCT = 32'b00000000000000000000000000000011
    PMA_PLL1_REG_PLL_LOCKDET_ITER = 32'b00000000000000000000000000000000
    PMA_PLL1_REG_PLL_LOCKDET_MODE = FALSE
    PMA_PLL1_REG_PLL_LOCKDET_LOCKCT = 32'b00000000000000000000000000000100
    PMA_PLL1_REG_PLL_LOCKDET_REFCT = 32'b00000000000000000000000000000011
    PMA_PLL1_REG_PLL_LOCKDET_RESET_N = TRUE
    PMA_PLL1_REG_PLL_LOCKDET_RESET_N_OW = FALSE
    PMA_PLL1_REG_PLL_LOCKED = FALSE
    PMA_PLL1_REG_PLL_LOCKED_OW = FALSE
    PMA_PLL1_REG_PLL_LOCKED_STICKY_CLEAR = FALSE
    PMA_PLL1_REG_PLL_UNLOCKED = FALSE
    PMA_PLL1_REG_PLL_UNLOCKDET_ITER = 32'b00000000000000000000000000000010
    PMA_PLL1_REG_PLL_UNLOCKED_OW = FALSE
    PMA_PLL1_REG_PLL_UNLOCKED_STICKY_CLEAR = FALSE
    PMA_PLL1_REG_I_CTRL_MAX = 32'b00000000000000000000000000111111
    PMA_PLL1_REG_REFCLK_TEST_EN = FALSE
    PMA_PLL1_REG_RESCAL_EN = FALSE
    PMA_PLL1_REG_I_CTRL_MIN = 32'b00000000000000000000000000000000
    PMA_PLL1_REG_RESCAL_DONE_OW = FALSE
    PMA_PLL1_REG_RESCAL_DONE_VAL = FALSE
    PMA_PLL1_REG_RESCAL_I_CODE = 32'b00000000000000000000000000101110
    PMA_PLL1_REG_RESCAL_I_CODE_OW = FALSE
    PMA_PLL1_REG_RESCAL_I_CODE_PMA = FALSE
    PMA_PLL1_REG_RESCAL_I_CODE_VAL = 32'b00000000000000000000000000101110
    PMA_PLL1_REG_RESCAL_INT_R_SMALL_OW = FALSE
    PMA_PLL1_REG_RESCAL_INT_R_SMALL_VAL = FALSE
    PMA_PLL1_REG_RESCAL_ITER_VALID_SEL = 32'b00000000000000000000000000000000
    PMA_PLL1_REG_RESCAL_RESET_N_OW = FALSE
    PMA_PLL1_REG_RESCAL_RST_N_VAL = FALSE
    PMA_PLL1_REG_RESCAL_WAIT_SEL = TRUE
    PMA_PLL1_REFCLK2LANE_PD_L = FALSE
    PMA_PLL1_REFCLK2LANE_PD_R = FALSE
    PMA_PLL1_REG_LOCKDET_REPEAT = FALSE
    PMA_PLL1_REG_NOFBCLK_STICKY_CLEAR = FALSE
    PMA_PLL1_REG_NOREFCLK_STICKY_CLEAR = FALSE
    PMA_PLL1_REG_TEST_SEL = 32'b00000000000000000000000000001111
    PMA_PLL1_REG_TEST_V_EN = FALSE
    PMA_PLL1_REG_TEST_SIG_HALF_EN = FALSE
    PMA_PLL1_REG_REFCLK_PAD_SEL = FALSE
    PMA_PLL1_PARM_PLL_POWERUP = OFF
    CH0_MUX_BIAS = 32'b00000000000000000000000000000010
    CH0_PD_CLK = 32'b00000000000000000000000000000000
    CH0_REG_SYNC = 32'b00000000000000000000000000000000
    CH0_REG_SYNC_OW = 32'b00000000000000000000000000000000
    CH0_PLL_LOCK_OW = 32'b00000000000000000000000000000000
    CH0_PLL_LOCK_OW_EN = 32'b00000000000000000000000000000000
    PCS_CH0_SLAVE = 32'b00000000000000000000000000000000
    PCS_CH0_BYPASS_WORD_ALIGN = FALSE
    PCS_CH0_BYPASS_DENC = FALSE
    PCS_CH0_BYPASS_BONDING = TRUE
    PCS_CH0_BYPASS_CTC = FALSE
    PCS_CH0_BYPASS_GEAR = FALSE
    PCS_CH0_BYPASS_BRIDGE = TRUE
    PCS_CH0_BYPASS_BRIDGE_FIFO = FALSE
    PCS_CH0_DATA_MODE = X20
    PCS_CH0_RX_POLARITY_INV = DELAY
    PCS_CH0_ALIGN_MODE = 10GB
    PCS_CH0_SAMP_16B = X20
    PCS_CH0_FARLP_PWR_REDUCTION = FALSE
    PCS_CH0_COMMA_REG0 = 32'b00000000000000000000000101111100
    PCS_CH0_COMMA_MASK = 32'b00000000000000000000000000000000
    PCS_CH0_CEB_MODE = 10GB
    PCS_CH0_CTC_MODE = 4SKIP
    PCS_CH0_A_REG = 32'b00000000000000000000000001111100
    PCS_CH0_GE_AUTO_EN = FALSE
    PCS_CH0_SKIP_REG0 = 32'b00000000000000000000000110111100
    PCS_CH0_SKIP_REG1 = 32'b00000000000000000000000100011100
    PCS_CH0_SKIP_REG2 = 32'b00000000000000000000000100011100
    PCS_CH0_SKIP_REG3 = 32'b00000000000000000000000100011100
    PCS_CH0_DEC_DUAL = TRUE
    PCS_CH0_SPLIT = FALSE
    PCS_CH0_FIFOFLAG_CTC = FALSE
    PCS_CH0_COMMA_DET_MODE = COMMA_PATTERN
    PCS_CH0_ERRDETECT_SILENCE = TRUE
    PCS_CH0_PMA_RCLK_POLINV = PMA_RCLK
    PCS_CH0_PCS_RCLK_SEL = PMA_RCLK
    PCS_CH0_CB_RCLK_SEL = PMA_RCLK
    PCS_CH0_AFTER_CTC_RCLK_SEL = RCLK2
    PCS_CH0_RCLK_POLINV = RCLK
    PCS_CH0_BRIDGE_RCLK_SEL = PMA_RCLK
    PCS_CH0_PCS_RCLK_EN = FALSE
    PCS_CH0_CB_RCLK_EN = FALSE
    PCS_CH0_AFTER_CTC_RCLK_EN = FALSE
    PCS_CH0_AFTER_CTC_RCLK_EN_GB = TRUE
    PCS_CH0_PCS_RX_RSTN = TRUE
    PCS_CH0_PCIE_SLAVE = MASTER
    PCS_CH0_RX_64B66B_67B = NORMAL
    PCS_CH0_RX_BRIDGE_CLK_POLINV = RX_BRIDGE_CLK
    PCS_CH0_PCS_CB_RSTN = TRUE
    PCS_CH0_TX_BRIDGE_GEAR_SEL = FALSE
    PCS_CH0_TX_BYPASS_BRIDGE_UINT = FALSE
    PCS_CH0_TX_BYPASS_BRIDGE_FIFO = FALSE
    PCS_CH0_TX_BYPASS_GEAR = FALSE
    PCS_CH0_TX_BYPASS_ENC = FALSE
    PCS_CH0_TX_BYPASS_BIT_SLIP = TRUE
    PCS_CH0_TX_GEAR_SPLIT = TRUE
    PCS_CH0_TX_DRIVE_REG_MODE = NO_CHANGE
    PCS_CH0_TX_BIT_SLIP_CYCLES = 32'b00000000000000000000000000000000
    PCS_CH0_INT_TX_MASK_0 = FALSE
    PCS_CH0_INT_TX_MASK_1 = FALSE
    PCS_CH0_INT_TX_MASK_2 = FALSE
    PCS_CH0_INT_TX_CLR_0 = FALSE
    PCS_CH0_INT_TX_CLR_1 = FALSE
    PCS_CH0_INT_TX_CLR_2 = FALSE
    PCS_CH0_TX_PMA_TCLK_POLINV = PMA_TCLK
    PCS_CH0_TX_PCS_CLK_EN_SEL = TRUE
    PCS_CH0_TX_BRIDGE_TCLK_SEL = TCLK
    PCS_CH0_TX_TCLK_POLINV = TCLK
    PCS_CH0_PCS_TCLK_SEL = PMA_TCLK
    PCS_CH0_TX_PCS_TX_RSTN = TRUE
    PCS_CH0_TX_SLAVE = MASTER
    PCS_CH0_TX_GEAR_CLK_EN_SEL = FALSE
    PCS_CH0_DATA_WIDTH_MODE = X20
    PCS_CH0_TX_64B66B_67B = NORMAL
    PCS_CH0_GEAR_TCLK_SEL = PMA_TCLK
    PCS_CH0_TX_TCLK2FABRIC_SEL = TRUE
    PCS_CH0_TX_OUTZZ = FALSE
    PCS_CH0_ENC_DUAL = TRUE
    PCS_CH0_TX_BITSLIP_DATA_MODE = X10
    PCS_CH0_TX_BRIDGE_CLK_POLINV = TX_BRIDGE_CLK
    PCS_CH0_COMMA_REG1 = 32'b00000000000000000000001010000011
    PCS_CH0_RAPID_IMAX = 32'b00000000000000000000000000000101
    PCS_CH0_RAPID_VMIN_1 = 32'b00000000000000000000000011111010
    PCS_CH0_RAPID_VMIN_2 = 32'b00000000000000000000000000000001
    PCS_CH0_RX_PRBS_MODE = DISABLE
    PCS_CH0_RX_ERRCNT_CLR = FALSE
    PCS_CH0_PRBS_ERR_LPBK = FALSE
    PCS_CH0_TX_PRBS_MODE = DISABLE
    PCS_CH0_TX_INSERT_ER = FALSE
    PCS_CH0_ENABLE_PRBS_GEN = FALSE
    PCS_CH0_DEFAULT_RADDR = 32'b00000000000000000000000000000110
    PCS_CH0_MASTER_CHECK_OFFSET = 32'b00000000000000000000000000000100
    PCS_CH0_DELAY_SET = 32'b00000000000000000000000000000011
    PCS_CH0_SEACH_OFFSET = 80BIT
    PCS_CH0_CEB_RAPIDLS_MMAX = 32'b00000000000000000000000000000101
    PCS_CH0_CTC_AFULL = 32'b00000000000000000000000000010100
    PCS_CH0_CTC_AEMPTY = 32'b00000000000000000000000000001100
    PCS_CH0_CTC_CONTI_SKP_SET = 32'b00000000000000000000000000000000
    PCS_CH0_FAR_LOOP = FALSE
    PCS_CH0_NEAR_LOOP = FALSE
    PCS_CH0_PMA_TX2RX_PLOOP_EN = TRUE
    PCS_CH0_PMA_TX2RX_SLOOP_EN = TRUE
    PCS_CH0_PMA_RX2TX_PLOOP_EN = TRUE
    PCS_CH0_INT_RX_MASK_0 = FALSE
    PCS_CH0_INT_RX_MASK_1 = FALSE
    PCS_CH0_INT_RX_MASK_2 = FALSE
    PCS_CH0_INT_RX_MASK_3 = FALSE
    PCS_CH0_INT_RX_MASK_4 = FALSE
    PCS_CH0_INT_RX_MASK_5 = FALSE
    PCS_CH0_INT_RX_MASK_6 = FALSE
    PCS_CH0_INT_RX_MASK_7 = FALSE
    PCS_CH0_INT_RX_CLR_0 = FALSE
    PCS_CH0_INT_RX_CLR_1 = FALSE
    PCS_CH0_INT_RX_CLR_2 = FALSE
    PCS_CH0_INT_RX_CLR_3 = FALSE
    PCS_CH0_INT_RX_CLR_4 = FALSE
    PCS_CH0_INT_RX_CLR_5 = FALSE
    PCS_CH0_INT_RX_CLR_6 = FALSE
    PCS_CH0_INT_RX_CLR_7 = FALSE
    PCS_CH0_CA_RSTN_RX = FALSE
    PCS_CH0_CA_DYN_DLY_EN_RX = FALSE
    PCS_CH0_CA_DYN_DLY_SEL_RX = FALSE
    PCS_CH0_CA_RX = 32'b00000000000000000000000000000000
    PCS_CH0_CA_RSTN_TX = FALSE
    PCS_CH0_CA_DYN_DLY_EN_TX = FALSE
    PCS_CH0_CA_DYN_DLY_SEL_TX = FALSE
    PCS_CH0_CA_TX = 32'b00000000000000000000000000000000
    PCS_CH0_RXPRBS_PWR_REDUCTION = NORMAL
    PCS_CH0_WDALIGN_PWR_REDUCTION = NORMAL
    PCS_CH0_RXDEC_PWR_REDUCTION = NORMAL
    PCS_CH0_RXCB_PWR_REDUCTION = NORMAL
    PCS_CH0_RXCTC_PWR_REDUCTION = NORMAL
    PCS_CH0_RXGEAR_PWR_REDUCTION = NORMAL
    PCS_CH0_RXBRG_PWR_REDUCTION = NORMAL
    PCS_CH0_RXTEST_PWR_REDUCTION = NORMAL
    PCS_CH0_TXBRG_PWR_REDUCTION = NORMAL
    PCS_CH0_TXGEAR_PWR_REDUCTION = NORMAL
    PCS_CH0_TXENC_PWR_REDUCTION = NORMAL
    PCS_CH0_TXBSLP_PWR_REDUCTION = NORMAL
    PCS_CH0_TXPRBS_PWR_REDUCTION = NORMAL
    PMA_CH0_REG_RX_PD = ON
    PMA_CH0_REG_RX_PD_EN = FALSE
    PMA_CH0_REG_RX_RESERVED_2 = FALSE
    PMA_CH0_REG_RX_RESERVED_3 = FALSE
    PMA_CH0_REG_RX_DATAPATH_PD = ON
    PMA_CH0_REG_RX_DATAPATH_PD_EN = TRUE
    PMA_CH0_REG_RX_SIGDET_PD = ON
    PMA_CH0_REG_RX_SIGDET_PD_EN = FALSE
    PMA_CH0_REG_RX_DCC_RST_N = TRUE
    PMA_CH0_REG_RX_DCC_RST_N_EN = FALSE
    PMA_CH0_REG_RX_CDR_RST_N = TRUE
    PMA_CH0_REG_RX_CDR_RST_N_EN = FALSE
    PMA_CH0_REG_RX_SIGDET_RST_N = TRUE
    PMA_CH0_REG_RX_SIGDET_RST_N_EN = FALSE
    PMA_CH0_REG_RXPCLK_SLIP = FALSE
    PMA_CH0_REG_RXPCLK_SLIP_OW = FALSE
    PMA_CH0_REG_RX_PCLKSWITCH_RST_N = TRUE
    PMA_CH0_REG_RX_PCLKSWITCH_RST_N_EN = FALSE
    PMA_CH0_REG_RX_PCLKSWITCH = FALSE
    PMA_CH0_REG_RX_PCLKSWITCH_EN = FALSE
    PMA_CH0_REG_RX_HIGHZ = FALSE
    PMA_CH0_REG_RX_HIGHZ_EN = FALSE
    PMA_CH0_REG_RX_SIGDET_CLK_WINDOW = FALSE
    PMA_CH0_REG_RX_SIGDET_CLK_WINDOW_OW = FALSE
    PMA_CH0_REG_RX_PD_BIAS_RX = FALSE
    PMA_CH0_REG_RX_PD_BIAS_RX_OW = FALSE
    PMA_CH0_REG_RX_RESET_N = FALSE
    PMA_CH0_REG_RX_RESET_N_OW = FALSE
    PMA_CH0_REG_RX_RESERVED_29_28 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_BUSWIDTH = 20BIT
    PMA_CH0_REG_RX_BUSWIDTH_EN = TRUE
    PMA_CH0_REG_RX_RATE = DIV1
    PMA_CH0_REG_RX_RESERVED_36 = FALSE
    PMA_CH0_REG_RX_RATE_EN = FALSE
    PMA_CH0_REG_RX_RES_TRIM = 32'b00000000000000000000000000101110
    PMA_CH0_REG_RX_RESERVED_44 = FALSE
    PMA_CH0_REG_RX_RESERVED_45 = FALSE
    PMA_CH0_REG_RX_SIGDET_STATUS_EN = FALSE
    PMA_CH0_REG_RX_RESERVED_48_47 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_ICTRL_SIGDET = 32'b00000000000000000000000000000101
    PMA_CH0_REG_CDR_READY_THD = 32'b00000000000000000000101010101110
    PMA_CH0_REG_RX_RESERVED_65 = FALSE
    PMA_CH0_REG_RX_PCLK_EDGE_SEL = POS_EDGE
    PMA_CH0_REG_RX_PIBUF_IC = 32'b00000000000000000000000000000001
    PMA_CH0_REG_RX_RESERVED_69 = FALSE
    PMA_CH0_REG_RX_DCC_IC_RX = 32'b00000000000000000000000000000001
    PMA_CH0_REG_CDR_READY_CHECK_CTRL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_ICTRL_TRX = 100PCT
    PMA_CH0_REG_RX_RESERVED_77_76 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_RESERVED_79_78 = 32'b00000000000000000000000000000001
    PMA_CH0_REG_RX_RESERVED_81_80 = 32'b00000000000000000000000000000001
    PMA_CH0_REG_RX_ICTRL_PIBUF = 100PCT
    PMA_CH0_REG_RX_ICTRL_PI = 100PCT
    PMA_CH0_REG_RX_ICTRL_DCC = 100PCT
    PMA_CH0_REG_RX_RESERVED_89_88 = 32'b00000000000000000000000000000001
    PMA_CH0_REG_TX_RATE = DIV1
    PMA_CH0_REG_RX_RESERVED_92 = FALSE
    PMA_CH0_REG_TX_RATE_EN = FALSE
    PMA_CH0_REG_RX_TX2RX_PLPBK_RST_N = TRUE
    PMA_CH0_REG_RX_TX2RX_PLPBK_RST_N_EN = FALSE
    PMA_CH0_REG_RX_TX2RX_PLPBK_EN = FALSE
    PMA_CH0_REG_TXCLK_SEL = PLL
    PMA_CH0_REG_RX_DATA_POLARITY = NORMAL
    PMA_CH0_REG_RX_ERR_INSERT = FALSE
    PMA_CH0_REG_UDP_CHK_EN = FALSE
    PMA_CH0_REG_PRBS_SEL = PRBS7
    PMA_CH0_REG_PRBS_CHK_EN = FALSE
    PMA_CH0_REG_PRBS_CHK_WIDTH_SEL = 20BIT
    PMA_CH0_REG_BIST_CHK_PAT_SEL = PRBS
    PMA_CH0_REG_LOAD_ERR_CNT = FALSE
    PMA_CH0_REG_CHK_COUNTER_EN = FALSE
    PMA_CH0_REG_CDR_PROP_GAIN = 32'b00000000000000000000000000000111
    PMA_CH0_REG_CDR_PROP_TURBO_GAIN = 32'b00000000000000000000000000000101
    PMA_CH0_REG_CDR_INT_GAIN = 32'b00000000000000000000000000000100
    PMA_CH0_REG_CDR_INT_TURBO_GAIN = 32'b00000000000000000000000000000101
    PMA_CH0_REG_CDR_INT_SAT_MAX = 32'b00000000000000000000001100000000
    PMA_CH0_REG_CDR_INT_SAT_MIN = 32'b00000000000000000000000011111111
    PMA_CH0_REG_CDR_INT_RST = FALSE
    PMA_CH0_REG_CDR_INT_RST_OW = FALSE
    PMA_CH0_REG_CDR_PROP_RST = FALSE
    PMA_CH0_REG_CDR_PROP_RST_OW = FALSE
    PMA_CH0_REG_CDR_LOCK_RST = FALSE
    PMA_CH0_REG_CDR_LOCK_RST_OW = FALSE
    PMA_CH0_REG_CDR_RX_PI_FORCE_SEL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_CDR_RX_PI_FORCE_D = 32'b00000000000000000000000000000000
    PMA_CH0_REG_CDR_LOCK_TIMER = 1_2U
    PMA_CH0_REG_CDR_TURBO_MODE_TIMER = 32'b00000000000000000000000000000001
    PMA_CH0_REG_CDR_LOCK_VAL = FALSE
    PMA_CH0_REG_CDR_LOCK_OW = FALSE
    PMA_CH0_REG_CDR_INT_SAT_DET_EN = TRUE
    PMA_CH0_REG_CDR_SAT_AUTO_DIS = TRUE
    PMA_CH0_REG_CDR_GAIN_AUTO = FALSE
    PMA_CH0_REG_CDR_TURBO_GAIN_AUTO = FALSE
    PMA_CH0_REG_RX_RESERVED_171_167 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_RESERVED_175_172 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_CDR_SAT_DET_STATUS_EN = FALSE
    PMA_CH0_REG_CDR_SAT_DET_STATUS_RESET_EN = FALSE
    PMA_CH0_REG_CDR_PI_CTRL_RST = FALSE
    PMA_CH0_REG_CDR_PI_CTRL_RST_OW = FALSE
    PMA_CH0_REG_CDR_SAT_DET_RST = FALSE
    PMA_CH0_REG_CDR_SAT_DET_RST_OW = FALSE
    PMA_CH0_REG_CDR_SAT_DET_STICKY_RST = FALSE
    PMA_CH0_REG_CDR_SAT_DET_STICKY_RST_OW = FALSE
    PMA_CH0_REG_CDR_SIGDET_STATUS_DIS = FALSE
    PMA_CH0_REG_CDR_SAT_DET_TIMER = 32'b00000000000000000000000000000010
    PMA_CH0_REG_CDR_SAT_DET_STATUS_VAL = FALSE
    PMA_CH0_REG_CDR_SAT_DET_STATUS_OW = FALSE
    PMA_CH0_REG_CDR_TURBO_MODE_EN = TRUE
    PMA_CH0_REG_RX_RESERVED_190 = FALSE
    PMA_CH0_REG_RX_RESERVED_193_191 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_CDR_STATUS_FIFO_EN = TRUE
    PMA_CH0_REG_PMA_TEST_SEL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_OOB_COMWAKE_GAP_MIN = 32'b00000000000000000000000000000011
    PMA_CH0_REG_OOB_COMWAKE_GAP_MAX = 32'b00000000000000000000000000001011
    PMA_CH0_REG_OOB_COMINIT_GAP_MIN = 32'b00000000000000000000000000001111
    PMA_CH0_REG_OOB_COMINIT_GAP_MAX = 32'b00000000000000000000000000100011
    PMA_CH0_REG_RX_RESERVED_227_226 = 32'b00000000000000000000000000000001
    PMA_CH0_REG_COMWAKE_STATUS_CLEAR = 32'b00000000000000000000000000000000
    PMA_CH0_REG_COMINIT_STATUS_CLEAR = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_SYNC_RST_N_EN = FALSE
    PMA_CH0_REG_RX_SYNC_RST_N = TRUE
    PMA_CH0_REG_RX_RESERVED_233_232 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_RESERVED_235_234 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_SATA_COMINIT_OW = FALSE
    PMA_CH0_REG_RX_SATA_COMINIT = FALSE
    PMA_CH0_REG_RX_SATA_COMWAKE_OW = FALSE
    PMA_CH0_REG_RX_SATA_COMWAKE = FALSE
    PMA_CH0_REG_RX_RESERVED_241_240 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_DCC_DISABLE = FALSE
    PMA_CH0_REG_RX_RESERVED_243 = FALSE
    PMA_CH0_REG_RX_SLIP_SEL_EN = FALSE
    PMA_CH0_REG_RX_SLIP_SEL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_SLIP_EN = FALSE
    PMA_CH0_REG_RX_SIGDET_STATUS_SEL = 32'b00000000000000000000000000000101
    PMA_CH0_REG_RX_SIGDET_FSM_RST_N = TRUE
    PMA_CH0_REG_RX_RESERVED_254 = FALSE
    PMA_CH0_REG_RX_SIGDET_STATUS = FALSE
    PMA_CH0_REG_RX_SIGDET_VTH = 72MV
    PMA_CH0_REG_RX_SIGDET_GRM = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_SIGDET_PULSE_EXT = FALSE
    PMA_CH0_REG_RX_SIGDET_CH2_SEL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_SIGDET_CH2_CHK_WINDOW = 32'b00000000000000000000000000000011
    PMA_CH0_REG_RX_SIGDET_CHK_WINDOW_EN = TRUE
    PMA_CH0_REG_RX_SIGDET_NOSIG_COUNT_SETTING = 32'b00000000000000000000000000000100
    PMA_CH0_REG_SLIP_FIFO_INV_EN = FALSE
    PMA_CH0_REG_SLIP_FIFO_INV = POS_EDGE
    PMA_CH0_REG_RX_SIGDET_OOB_DET_COUNT_VAL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_SIGDET_4OOB_DET_SEL = 32'b00000000000000000000000000000111
    PMA_CH0_REG_RX_RESERVED_285_283 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_RESERVED_286 = FALSE
    PMA_CH0_REG_RX_SIGDET_IC_I = 32'b00000000000000000000000000001010
    PMA_CH0_REG_RX_OOB_DETECTOR_RESET_N_OW = FALSE
    PMA_CH0_REG_RX_OOB_DETECTOR_RESET_N = FALSE
    PMA_CH0_REG_RX_OOB_DETECTOR_PD_OW = FALSE
    PMA_CH0_REG_RX_OOB_DETECTOR_PD = ON
    PMA_CH0_REG_RX_LS_MODE_EN = FALSE
    PMA_CH0_REG_ANA_RX_EQ1_R_SET_FB_O_SEL = TRUE
    PMA_CH0_REG_ANA_RX_EQ2_R_SET_FB_O_SEL = TRUE
    PMA_CH0_REG_RX_EQ1_R_SET_TOP = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_EQ1_R_SET_FB = 32'b00000000000000000000000000001111
    PMA_CH0_REG_RX_EQ1_C_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_EQ1_OFF = FALSE
    PMA_CH0_REG_RX_EQ2_R_SET_TOP = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_EQ2_R_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_EQ2_C_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_EQ2_OFF = FALSE
    PMA_CH0_REG_EQ_DAC = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_ICTRL_EQ = 32'b00000000000000000000000000000010
    PMA_CH0_REG_EQ_DC_CALIB_EN = TRUE
    PMA_CH0_REG_EQ_DC_CALIB_SEL = FALSE
    PMA_CH0_REG_RX_RESERVED_337_330 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_RESERVED_345_338 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_RESERVED_353_346 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RX_RESERVED_361_354 = 32'b00000000000000000000000000000000
    PMA_CH0_CTLE_CTRL_REG_I = 32'b00000000000000000000000000000000
    PMA_CH0_CTLE_REG_FORCE_SEL_I = FALSE
    PMA_CH0_CTLE_REG_HOLD_I = FALSE
    PMA_CH0_CTLE_REG_INIT_DAC_I = 32'b00000000000000000000000000000000
    PMA_CH0_CTLE_REG_POLARITY_I = FALSE
    PMA_CH0_CTLE_REG_SHIFTER_GAIN_I = 32'b00000000000000000000000000000001
    PMA_CH0_CTLE_REG_THRESHOLD_I = 32'b00000000000000000000110000000000
    PMA_CH0_REG_RX_RES_TRIM_EN = TRUE
    PMA_CH0_REG_RX_RESERVED_393_389 = 32'b00000000000000000000000000000000
    PMA_CH0_CFG_RX_LANE_POWERUP = ON
    PMA_CH0_CFG_RX_PMA_RSTN = TRUE
    PMA_CH0_INT_PMA_RX_MASK_0 = FALSE
    PMA_CH0_INT_PMA_RX_CLR_0 = FALSE
    PMA_CH0_CFG_CTLE_ADP_RSTN = TRUE
    PMA_CH0_REG_TX_PD = ON
    PMA_CH0_REG_TX_PD_OW = FALSE
    PMA_CH0_REG_TX_MAIN_PRE_Z = FALSE
    PMA_CH0_REG_TX_MAIN_PRE_Z_OW = FALSE
    PMA_CH0_REG_TX_BEACON_TIMER_SEL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RXDET_REQ_OW = FALSE
    PMA_CH0_REG_TX_RXDET_REQ = FALSE
    PMA_CH0_REG_TX_BEACON_EN_OW = FALSE
    PMA_CH0_REG_TX_BEACON_EN = FALSE
    PMA_CH0_REG_TX_EI_EN_OW = FALSE
    PMA_CH0_REG_TX_EI_EN = FALSE
    PMA_CH0_REG_TX_BIT_CONV = FALSE
    PMA_CH0_REG_TX_RES_CAL = 32'b00000000000000000000000000110000
    PMA_CH0_REG_TX_RESERVED_19 = FALSE
    PMA_CH0_REG_TX_RESERVED_25_20 = 32'b00000000000000000000000000100000
    PMA_CH0_REG_TX_RESERVED_33_26 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_41_34 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_49_42 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_57_50 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_SYNC_OW = FALSE
    PMA_CH0_REG_TX_SYNC = FALSE
    PMA_CH0_REG_TX_PD_POST = ON
    PMA_CH0_REG_TX_PD_POST_OW = TRUE
    PMA_CH0_REG_TX_RESET_N_OW = FALSE
    PMA_CH0_REG_TX_RESET_N = TRUE
    PMA_CH0_REG_TX_RESERVED_64 = FALSE
    PMA_CH0_REG_TX_RESERVED_65 = TRUE
    PMA_CH0_REG_TX_BUSWIDTH_OW = TRUE
    PMA_CH0_REG_TX_BUSWIDTH = 20BIT
    PMA_CH0_REG_PLL_READY_OW = FALSE
    PMA_CH0_REG_PLL_READY = TRUE
    PMA_CH0_REG_TX_RESERVED_72 = FALSE
    PMA_CH0_REG_TX_RESERVED_73 = FALSE
    PMA_CH0_REG_TX_RESERVED_74 = FALSE
    PMA_CH0_REG_EI_PCLK_DELAY_SEL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_77 = FALSE
    PMA_CH0_REG_TX_RESERVED_83_78 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_89_84 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_95_90 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_101_96 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_107_102 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_113_108 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_AMP_DAC0 = 32'b00000000000000000000000000011001
    PMA_CH0_REG_TX_AMP_DAC1 = 32'b00000000000000000000000000010011
    PMA_CH0_REG_TX_AMP_DAC2 = 32'b00000000000000000000000000001110
    PMA_CH0_REG_TX_AMP_DAC3 = 32'b00000000000000000000000000001001
    PMA_CH0_REG_TX_RESERVED_143_138 = 32'b00000000000000000000000000000101
    PMA_CH0_REG_TX_MARGIN = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_MARGIN_OW = FALSE
    PMA_CH0_REG_TX_RESERVED_149_148 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_150 = FALSE
    PMA_CH0_REG_TX_SWING = FALSE
    PMA_CH0_REG_TX_SWING_OW = FALSE
    PMA_CH0_REG_TX_RESERVED_153 = FALSE
    PMA_CH0_REG_TX_RXDET_THRESHOLD = 84MV
    PMA_CH0_REG_TX_RESERVED_157_156 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_BEACON_OSC_CTRL = FALSE
    PMA_CH0_REG_TX_RESERVED_160_159 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_162_161 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_TX2RX_SLPBACK_EN = FALSE
    PMA_CH0_REG_TX_PCLK_EDGE_SEL = FALSE
    PMA_CH0_REG_TX_RXDET_STATUS_OW = FALSE
    PMA_CH0_REG_TX_RXDET_STATUS = TRUE
    PMA_CH0_REG_TX_PRBS_GEN_EN = FALSE
    PMA_CH0_REG_TX_PRBS_GEN_WIDTH_SEL = 20BIT
    PMA_CH0_REG_TX_PRBS_SEL = PRBS7
    PMA_CH0_REG_TX_UDP_DATA_7_TO_0 = 32'b00000000000000000000000000000101
    PMA_CH0_REG_TX_UDP_DATA_15_TO_8 = 32'b00000000000000000000000011101011
    PMA_CH0_REG_TX_UDP_DATA_19_TO_16 = 32'b00000000000000000000000000000011
    PMA_CH0_REG_TX_RESERVED_192 = FALSE
    PMA_CH0_REG_TX_FIFO_WP_CTRL = 32'b00000000000000000000000000000100
    PMA_CH0_REG_TX_FIFO_EN = FALSE
    PMA_CH0_REG_TX_DATA_MUX_SEL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_ERR_INSERT = FALSE
    PMA_CH0_REG_TX_RESERVED_203_200 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_204 = FALSE
    PMA_CH0_REG_TX_SATA_EN = FALSE
    PMA_CH0_REG_TX_RESERVED_207_206 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_RATE_CHANGE_TXPCLK_ON_OW = FALSE
    PMA_CH0_REG_RATE_CHANGE_TXPCLK_ON = TRUE
    PMA_CH0_REG_TX_CFG_POST1 = 32'b00000000000000000000000000010011
    PMA_CH0_REG_TX_CFG_POST2 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_DEEMP = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_DEEMP_OW = FALSE
    PMA_CH0_REG_TX_RESERVED_224_223 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RESERVED_225 = FALSE
    PMA_CH0_REG_TX_RESERVED_229_226 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_OOB_DELAY_SEL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_POLARITY = NORMAL
    PMA_CH0_REG_ANA_TX_JTAG_DATA_O_SEL = FALSE
    PMA_CH0_REG_TX_RESERVED_236 = FALSE
    PMA_CH0_REG_TX_LS_MODE_EN = FALSE
    PMA_CH0_REG_TX_JTAG_MODE_EN_OW = FALSE
    PMA_CH0_REG_TX_JTAG_MODE_EN = FALSE
    PMA_CH0_REG_RX_JTAG_MODE_EN_OW = FALSE
    PMA_CH0_REG_RX_JTAG_MODE_EN = FALSE
    PMA_CH0_REG_RX_JTAG_OE = TRUE
    PMA_CH0_REG_RX_ACJTAG_VHYSTSEL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_RES_CAL_EN = FALSE
    PMA_CH0_REG_RX_TERM_MODE_CTRL = 32'b00000000000000000000000000000101
    PMA_CH0_REG_TX_RESERVED_251_250 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_PLPBK_TXPCLK_EN = FALSE
    PMA_CH0_REG_TX_RESERVED_253 = FALSE
    PMA_CH0_REG_TX_RESERVED_254 = FALSE
    PMA_CH0_REG_TX_RESERVED_255 = FALSE
    PMA_CH0_REG_TX_RESERVED_256 = FALSE
    PMA_CH0_REG_TX_RESERVED_257 = FALSE
    PMA_CH0_REG_TX_PH_SEL = 32'b00000000000000000000000000000001
    PMA_CH0_REG_TX_CFG_PRE = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_CFG_MAIN = 32'b00000000000000000000000000000000
    PMA_CH0_REG_CFG_POST = 32'b00000000000000000000000000001100
    PMA_CH0_REG_PD_MAIN = TRUE
    PMA_CH0_REG_PD_PRE = TRUE
    PMA_CH0_REG_TX_LS_DATA = FALSE
    PMA_CH0_REG_TX_DCC_BUF_SZ_SEL = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_DCC_CAL_CUR_TUNE = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_DCC_CAL_EN = FALSE
    PMA_CH0_REG_TX_DCC_CUR_SS = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_DCC_FA_CTRL = FALSE
    PMA_CH0_REG_TX_DCC_RI_CTRL = FALSE
    PMA_CH0_REG_ATB_SEL_2_TO_0 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_ATB_SEL_9_TO_3 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_CFG_7_TO_0 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_CFG_15_TO_8 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_CFG_23_TO_16 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_CFG_31_TO_24 = 32'b00000000000000000000000010000000
    PMA_CH0_REG_TX_OOB_EI_EN = FALSE
    PMA_CH0_REG_TX_OOB_EI_EN_OW = FALSE
    PMA_CH0_REG_TX_BEACON_EN_DELAYED = FALSE
    PMA_CH0_REG_TX_BEACON_EN_DELAYED_OW = FALSE
    PMA_CH0_REG_TX_JTAG_DATA = FALSE
    PMA_CH0_REG_TX_RXDET_TIMER_SEL = 32'b00000000000000000000000001010111
    PMA_CH0_REG_TX_CFG1_7_0 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_CFG1_15_8 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_CFG1_23_16 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_TX_CFG1_31_24 = 32'b00000000000000000000000000000000
    PMA_CH0_REG_CFG_LANE_POWERUP = ON
    PMA_CH0_REG_CFG_TX_LANE_POWERUP_CLKPATH = TRUE
    PMA_CH0_REG_CFG_TX_LANE_POWERUP_PISO = TRUE
    PMA_CH0_REG_CFG_TX_LANE_POWERUP_DRIVER = TRUE
    CH1_MUX_BIAS = 32'b00000000000000000000000000000010
    CH1_PD_CLK = 32'b00000000000000000000000000000000
    CH1_REG_SYNC = 32'b00000000000000000000000000000000
    CH1_REG_SYNC_OW = 32'b00000000000000000000000000000000
    CH1_PLL_LOCK_OW = 32'b00000000000000000000000000000000
    CH1_PLL_LOCK_OW_EN = 32'b00000000000000000000000000000000
    PCS_CH1_SLAVE = 32'b00000000000000000000000000000000
    PCS_CH1_BYPASS_WORD_ALIGN = FALSE
    PCS_CH1_BYPASS_DENC = FALSE
    PCS_CH1_BYPASS_BONDING = TRUE
    PCS_CH1_BYPASS_CTC = FALSE
    PCS_CH1_BYPASS_GEAR = FALSE
    PCS_CH1_BYPASS_BRIDGE = TRUE
    PCS_CH1_BYPASS_BRIDGE_FIFO = FALSE
    PCS_CH1_DATA_MODE = X20
    PCS_CH1_RX_POLARITY_INV = DELAY
    PCS_CH1_ALIGN_MODE = 10GB
    PCS_CH1_SAMP_16B = X20
    PCS_CH1_FARLP_PWR_REDUCTION = FALSE
    PCS_CH1_COMMA_REG0 = 32'b00000000000000000000000101111100
    PCS_CH1_COMMA_MASK = 32'b00000000000000000000000000000000
    PCS_CH1_CEB_MODE = 10GB
    PCS_CH1_CTC_MODE = 4SKIP
    PCS_CH1_A_REG = 32'b00000000000000000000000001111100
    PCS_CH1_GE_AUTO_EN = FALSE
    PCS_CH1_SKIP_REG0 = 32'b00000000000000000000000110111100
    PCS_CH1_SKIP_REG1 = 32'b00000000000000000000000100011100
    PCS_CH1_SKIP_REG2 = 32'b00000000000000000000000100011100
    PCS_CH1_SKIP_REG3 = 32'b00000000000000000000000100011100
    PCS_CH1_DEC_DUAL = TRUE
    PCS_CH1_SPLIT = FALSE
    PCS_CH1_FIFOFLAG_CTC = FALSE
    PCS_CH1_COMMA_DET_MODE = COMMA_PATTERN
    PCS_CH1_ERRDETECT_SILENCE = TRUE
    PCS_CH1_PMA_RCLK_POLINV = PMA_RCLK
    PCS_CH1_PCS_RCLK_SEL = PMA_RCLK
    PCS_CH1_CB_RCLK_SEL = PMA_RCLK
    PCS_CH1_AFTER_CTC_RCLK_SEL = RCLK2
    PCS_CH1_RCLK_POLINV = RCLK
    PCS_CH1_BRIDGE_RCLK_SEL = PMA_RCLK
    PCS_CH1_PCS_RCLK_EN = FALSE
    PCS_CH1_CB_RCLK_EN = FALSE
    PCS_CH1_AFTER_CTC_RCLK_EN = FALSE
    PCS_CH1_AFTER_CTC_RCLK_EN_GB = TRUE
    PCS_CH1_PCS_RX_RSTN = TRUE
    PCS_CH1_PCIE_SLAVE = SLAVE
    PCS_CH1_RX_64B66B_67B = NORMAL
    PCS_CH1_RX_BRIDGE_CLK_POLINV = RX_BRIDGE_CLK
    PCS_CH1_PCS_CB_RSTN = TRUE
    PCS_CH1_TX_BRIDGE_GEAR_SEL = FALSE
    PCS_CH1_TX_BYPASS_BRIDGE_UINT = FALSE
    PCS_CH1_TX_BYPASS_BRIDGE_FIFO = FALSE
    PCS_CH1_TX_BYPASS_GEAR = FALSE
    PCS_CH1_TX_BYPASS_ENC = FALSE
    PCS_CH1_TX_BYPASS_BIT_SLIP = TRUE
    PCS_CH1_TX_GEAR_SPLIT = TRUE
    PCS_CH1_TX_DRIVE_REG_MODE = NO_CHANGE
    PCS_CH1_TX_BIT_SLIP_CYCLES = 32'b00000000000000000000000000000000
    PCS_CH1_INT_TX_MASK_0 = FALSE
    PCS_CH1_INT_TX_MASK_1 = FALSE
    PCS_CH1_INT_TX_MASK_2 = FALSE
    PCS_CH1_INT_TX_CLR_0 = FALSE
    PCS_CH1_INT_TX_CLR_1 = FALSE
    PCS_CH1_INT_TX_CLR_2 = FALSE
    PCS_CH1_TX_PMA_TCLK_POLINV = PMA_TCLK
    PCS_CH1_TX_PCS_CLK_EN_SEL = TRUE
    PCS_CH1_TX_BRIDGE_TCLK_SEL = TCLK
    PCS_CH1_TX_TCLK_POLINV = TCLK
    PCS_CH1_PCS_TCLK_SEL = PMA_TCLK
    PCS_CH1_TX_PCS_TX_RSTN = TRUE
    PCS_CH1_TX_SLAVE = SLAVE
    PCS_CH1_TX_GEAR_CLK_EN_SEL = FALSE
    PCS_CH1_DATA_WIDTH_MODE = X20
    PCS_CH1_TX_64B66B_67B = NORMAL
    PCS_CH1_GEAR_TCLK_SEL = PMA_TCLK
    PCS_CH1_TX_TCLK2FABRIC_SEL = FALSE
    PCS_CH1_TX_OUTZZ = FALSE
    PCS_CH1_ENC_DUAL = TRUE
    PCS_CH1_TX_BITSLIP_DATA_MODE = X10
    PCS_CH1_TX_BRIDGE_CLK_POLINV = TX_BRIDGE_CLK
    PCS_CH1_COMMA_REG1 = 32'b00000000000000000000001010000011
    PCS_CH1_RAPID_IMAX = 32'b00000000000000000000000000000101
    PCS_CH1_RAPID_VMIN_1 = 32'b00000000000000000000000011111010
    PCS_CH1_RAPID_VMIN_2 = 32'b00000000000000000000000000000001
    PCS_CH1_RX_PRBS_MODE = DISABLE
    PCS_CH1_RX_ERRCNT_CLR = FALSE
    PCS_CH1_PRBS_ERR_LPBK = FALSE
    PCS_CH1_TX_PRBS_MODE = DISABLE
    PCS_CH1_TX_INSERT_ER = FALSE
    PCS_CH1_ENABLE_PRBS_GEN = FALSE
    PCS_CH1_DEFAULT_RADDR = 32'b00000000000000000000000000000110
    PCS_CH1_MASTER_CHECK_OFFSET = 32'b00000000000000000000000000000100
    PCS_CH1_DELAY_SET = 32'b00000000000000000000000000000010
    PCS_CH1_SEACH_OFFSET = 80BIT
    PCS_CH1_CEB_RAPIDLS_MMAX = 32'b00000000000000000000000000000101
    PCS_CH1_CTC_AFULL = 32'b00000000000000000000000000010100
    PCS_CH1_CTC_AEMPTY = 32'b00000000000000000000000000001100
    PCS_CH1_CTC_CONTI_SKP_SET = 32'b00000000000000000000000000000000
    PCS_CH1_FAR_LOOP = FALSE
    PCS_CH1_NEAR_LOOP = FALSE
    PCS_CH1_PMA_TX2RX_PLOOP_EN = TRUE
    PCS_CH1_PMA_TX2RX_SLOOP_EN = TRUE
    PCS_CH1_PMA_RX2TX_PLOOP_EN = TRUE
    PCS_CH1_INT_RX_MASK_0 = FALSE
    PCS_CH1_INT_RX_MASK_1 = FALSE
    PCS_CH1_INT_RX_MASK_2 = FALSE
    PCS_CH1_INT_RX_MASK_3 = FALSE
    PCS_CH1_INT_RX_MASK_4 = FALSE
    PCS_CH1_INT_RX_MASK_5 = FALSE
    PCS_CH1_INT_RX_MASK_6 = FALSE
    PCS_CH1_INT_RX_MASK_7 = FALSE
    PCS_CH1_INT_RX_CLR_0 = FALSE
    PCS_CH1_INT_RX_CLR_1 = FALSE
    PCS_CH1_INT_RX_CLR_2 = FALSE
    PCS_CH1_INT_RX_CLR_3 = FALSE
    PCS_CH1_INT_RX_CLR_4 = FALSE
    PCS_CH1_INT_RX_CLR_5 = FALSE
    PCS_CH1_INT_RX_CLR_6 = FALSE
    PCS_CH1_INT_RX_CLR_7 = FALSE
    PCS_CH1_CA_RSTN_RX = FALSE
    PCS_CH1_CA_DYN_DLY_EN_RX = FALSE
    PCS_CH1_CA_DYN_DLY_SEL_RX = FALSE
    PCS_CH1_CA_RX = 32'b00000000000000000000000000000000
    PCS_CH1_CA_RSTN_TX = FALSE
    PCS_CH1_CA_DYN_DLY_EN_TX = FALSE
    PCS_CH1_CA_DYN_DLY_SEL_TX = FALSE
    PCS_CH1_CA_TX = 32'b00000000000000000000000000000000
    PCS_CH1_RXPRBS_PWR_REDUCTION = NORMAL
    PCS_CH1_WDALIGN_PWR_REDUCTION = NORMAL
    PCS_CH1_RXDEC_PWR_REDUCTION = NORMAL
    PCS_CH1_RXCB_PWR_REDUCTION = NORMAL
    PCS_CH1_RXCTC_PWR_REDUCTION = NORMAL
    PCS_CH1_RXGEAR_PWR_REDUCTION = NORMAL
    PCS_CH1_RXBRG_PWR_REDUCTION = NORMAL
    PCS_CH1_RXTEST_PWR_REDUCTION = NORMAL
    PCS_CH1_TXBRG_PWR_REDUCTION = NORMAL
    PCS_CH1_TXGEAR_PWR_REDUCTION = NORMAL
    PCS_CH1_TXENC_PWR_REDUCTION = NORMAL
    PCS_CH1_TXBSLP_PWR_REDUCTION = NORMAL
    PCS_CH1_TXPRBS_PWR_REDUCTION = NORMAL
    PMA_CH1_REG_RX_PD = ON
    PMA_CH1_REG_RX_PD_EN = FALSE
    PMA_CH1_REG_RX_RESERVED_2 = FALSE
    PMA_CH1_REG_RX_RESERVED_3 = FALSE
    PMA_CH1_REG_RX_DATAPATH_PD = ON
    PMA_CH1_REG_RX_DATAPATH_PD_EN = TRUE
    PMA_CH1_REG_RX_SIGDET_PD = ON
    PMA_CH1_REG_RX_SIGDET_PD_EN = FALSE
    PMA_CH1_REG_RX_DCC_RST_N = TRUE
    PMA_CH1_REG_RX_DCC_RST_N_EN = FALSE
    PMA_CH1_REG_RX_CDR_RST_N = TRUE
    PMA_CH1_REG_RX_CDR_RST_N_EN = FALSE
    PMA_CH1_REG_RX_SIGDET_RST_N = TRUE
    PMA_CH1_REG_RX_SIGDET_RST_N_EN = FALSE
    PMA_CH1_REG_RXPCLK_SLIP = FALSE
    PMA_CH1_REG_RXPCLK_SLIP_OW = FALSE
    PMA_CH1_REG_RX_PCLKSWITCH_RST_N = TRUE
    PMA_CH1_REG_RX_PCLKSWITCH_RST_N_EN = FALSE
    PMA_CH1_REG_RX_PCLKSWITCH = FALSE
    PMA_CH1_REG_RX_PCLKSWITCH_EN = FALSE
    PMA_CH1_REG_RX_HIGHZ = FALSE
    PMA_CH1_REG_RX_HIGHZ_EN = FALSE
    PMA_CH1_REG_RX_SIGDET_CLK_WINDOW = FALSE
    PMA_CH1_REG_RX_SIGDET_CLK_WINDOW_OW = FALSE
    PMA_CH1_REG_RX_PD_BIAS_RX = FALSE
    PMA_CH1_REG_RX_PD_BIAS_RX_OW = FALSE
    PMA_CH1_REG_RX_RESET_N = FALSE
    PMA_CH1_REG_RX_RESET_N_OW = FALSE
    PMA_CH1_REG_RX_RESERVED_29_28 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_BUSWIDTH = 20BIT
    PMA_CH1_REG_RX_BUSWIDTH_EN = TRUE
    PMA_CH1_REG_RX_RATE = DIV1
    PMA_CH1_REG_RX_RESERVED_36 = FALSE
    PMA_CH1_REG_RX_RATE_EN = FALSE
    PMA_CH1_REG_RX_RES_TRIM = 32'b00000000000000000000000000101110
    PMA_CH1_REG_RX_RESERVED_44 = FALSE
    PMA_CH1_REG_RX_RESERVED_45 = FALSE
    PMA_CH1_REG_RX_SIGDET_STATUS_EN = FALSE
    PMA_CH1_REG_RX_RESERVED_48_47 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_ICTRL_SIGDET = 32'b00000000000000000000000000000101
    PMA_CH1_REG_CDR_READY_THD = 32'b00000000000000000000101010101110
    PMA_CH1_REG_RX_RESERVED_65 = FALSE
    PMA_CH1_REG_RX_PCLK_EDGE_SEL = POS_EDGE
    PMA_CH1_REG_RX_PIBUF_IC = 32'b00000000000000000000000000000001
    PMA_CH1_REG_RX_RESERVED_69 = FALSE
    PMA_CH1_REG_RX_DCC_IC_RX = 32'b00000000000000000000000000000001
    PMA_CH1_REG_CDR_READY_CHECK_CTRL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_ICTRL_TRX = 100PCT
    PMA_CH1_REG_RX_RESERVED_77_76 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_RESERVED_79_78 = 32'b00000000000000000000000000000001
    PMA_CH1_REG_RX_RESERVED_81_80 = 32'b00000000000000000000000000000001
    PMA_CH1_REG_RX_ICTRL_PIBUF = 100PCT
    PMA_CH1_REG_RX_ICTRL_PI = 100PCT
    PMA_CH1_REG_RX_ICTRL_DCC = 100PCT
    PMA_CH1_REG_RX_RESERVED_89_88 = 32'b00000000000000000000000000000001
    PMA_CH1_REG_TX_RATE = DIV1
    PMA_CH1_REG_RX_RESERVED_92 = FALSE
    PMA_CH1_REG_TX_RATE_EN = FALSE
    PMA_CH1_REG_RX_TX2RX_PLPBK_RST_N = TRUE
    PMA_CH1_REG_RX_TX2RX_PLPBK_RST_N_EN = FALSE
    PMA_CH1_REG_RX_TX2RX_PLPBK_EN = FALSE
    PMA_CH1_REG_TXCLK_SEL = PLL
    PMA_CH1_REG_RX_DATA_POLARITY = NORMAL
    PMA_CH1_REG_RX_ERR_INSERT = FALSE
    PMA_CH1_REG_UDP_CHK_EN = FALSE
    PMA_CH1_REG_PRBS_SEL = PRBS7
    PMA_CH1_REG_PRBS_CHK_EN = FALSE
    PMA_CH1_REG_PRBS_CHK_WIDTH_SEL = 20BIT
    PMA_CH1_REG_BIST_CHK_PAT_SEL = PRBS
    PMA_CH1_REG_LOAD_ERR_CNT = FALSE
    PMA_CH1_REG_CHK_COUNTER_EN = FALSE
    PMA_CH1_REG_CDR_PROP_GAIN = 32'b00000000000000000000000000000111
    PMA_CH1_REG_CDR_PROP_TURBO_GAIN = 32'b00000000000000000000000000000101
    PMA_CH1_REG_CDR_INT_GAIN = 32'b00000000000000000000000000000100
    PMA_CH1_REG_CDR_INT_TURBO_GAIN = 32'b00000000000000000000000000000101
    PMA_CH1_REG_CDR_INT_SAT_MAX = 32'b00000000000000000000001100000000
    PMA_CH1_REG_CDR_INT_SAT_MIN = 32'b00000000000000000000000011111111
    PMA_CH1_REG_CDR_INT_RST = FALSE
    PMA_CH1_REG_CDR_INT_RST_OW = FALSE
    PMA_CH1_REG_CDR_PROP_RST = FALSE
    PMA_CH1_REG_CDR_PROP_RST_OW = FALSE
    PMA_CH1_REG_CDR_LOCK_RST = FALSE
    PMA_CH1_REG_CDR_LOCK_RST_OW = FALSE
    PMA_CH1_REG_CDR_RX_PI_FORCE_SEL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_CDR_RX_PI_FORCE_D = 32'b00000000000000000000000000000000
    PMA_CH1_REG_CDR_LOCK_TIMER = 1_2U
    PMA_CH1_REG_CDR_TURBO_MODE_TIMER = 32'b00000000000000000000000000000001
    PMA_CH1_REG_CDR_LOCK_VAL = FALSE
    PMA_CH1_REG_CDR_LOCK_OW = FALSE
    PMA_CH1_REG_CDR_INT_SAT_DET_EN = TRUE
    PMA_CH1_REG_CDR_SAT_AUTO_DIS = TRUE
    PMA_CH1_REG_CDR_GAIN_AUTO = FALSE
    PMA_CH1_REG_CDR_TURBO_GAIN_AUTO = FALSE
    PMA_CH1_REG_RX_RESERVED_171_167 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_RESERVED_175_172 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_CDR_SAT_DET_STATUS_EN = FALSE
    PMA_CH1_REG_CDR_SAT_DET_STATUS_RESET_EN = FALSE
    PMA_CH1_REG_CDR_PI_CTRL_RST = FALSE
    PMA_CH1_REG_CDR_PI_CTRL_RST_OW = FALSE
    PMA_CH1_REG_CDR_SAT_DET_RST = FALSE
    PMA_CH1_REG_CDR_SAT_DET_RST_OW = FALSE
    PMA_CH1_REG_CDR_SAT_DET_STICKY_RST = FALSE
    PMA_CH1_REG_CDR_SAT_DET_STICKY_RST_OW = FALSE
    PMA_CH1_REG_CDR_SIGDET_STATUS_DIS = FALSE
    PMA_CH1_REG_CDR_SAT_DET_TIMER = 32'b00000000000000000000000000000010
    PMA_CH1_REG_CDR_SAT_DET_STATUS_VAL = FALSE
    PMA_CH1_REG_CDR_SAT_DET_STATUS_OW = FALSE
    PMA_CH1_REG_CDR_TURBO_MODE_EN = TRUE
    PMA_CH1_REG_RX_RESERVED_190 = FALSE
    PMA_CH1_REG_RX_RESERVED_193_191 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_CDR_STATUS_FIFO_EN = TRUE
    PMA_CH1_REG_PMA_TEST_SEL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_OOB_COMWAKE_GAP_MIN = 32'b00000000000000000000000000000011
    PMA_CH1_REG_OOB_COMWAKE_GAP_MAX = 32'b00000000000000000000000000001011
    PMA_CH1_REG_OOB_COMINIT_GAP_MIN = 32'b00000000000000000000000000001111
    PMA_CH1_REG_OOB_COMINIT_GAP_MAX = 32'b00000000000000000000000000100011
    PMA_CH1_REG_RX_RESERVED_227_226 = 32'b00000000000000000000000000000001
    PMA_CH1_REG_COMWAKE_STATUS_CLEAR = 32'b00000000000000000000000000000000
    PMA_CH1_REG_COMINIT_STATUS_CLEAR = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_SYNC_RST_N_EN = FALSE
    PMA_CH1_REG_RX_SYNC_RST_N = TRUE
    PMA_CH1_REG_RX_RESERVED_233_232 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_RESERVED_235_234 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_SATA_COMINIT_OW = FALSE
    PMA_CH1_REG_RX_SATA_COMINIT = FALSE
    PMA_CH1_REG_RX_SATA_COMWAKE_OW = FALSE
    PMA_CH1_REG_RX_SATA_COMWAKE = FALSE
    PMA_CH1_REG_RX_RESERVED_241_240 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_DCC_DISABLE = FALSE
    PMA_CH1_REG_RX_RESERVED_243 = FALSE
    PMA_CH1_REG_RX_SLIP_SEL_EN = FALSE
    PMA_CH1_REG_RX_SLIP_SEL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_SLIP_EN = FALSE
    PMA_CH1_REG_RX_SIGDET_STATUS_SEL = 32'b00000000000000000000000000000101
    PMA_CH1_REG_RX_SIGDET_FSM_RST_N = TRUE
    PMA_CH1_REG_RX_RESERVED_254 = FALSE
    PMA_CH1_REG_RX_SIGDET_STATUS = FALSE
    PMA_CH1_REG_RX_SIGDET_VTH = 72MV
    PMA_CH1_REG_RX_SIGDET_GRM = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_SIGDET_PULSE_EXT = FALSE
    PMA_CH1_REG_RX_SIGDET_CH2_SEL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_SIGDET_CH2_CHK_WINDOW = 32'b00000000000000000000000000000011
    PMA_CH1_REG_RX_SIGDET_CHK_WINDOW_EN = TRUE
    PMA_CH1_REG_RX_SIGDET_NOSIG_COUNT_SETTING = 32'b00000000000000000000000000000100
    PMA_CH1_REG_SLIP_FIFO_INV_EN = FALSE
    PMA_CH1_REG_SLIP_FIFO_INV = POS_EDGE
    PMA_CH1_REG_RX_SIGDET_OOB_DET_COUNT_VAL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_SIGDET_4OOB_DET_SEL = 32'b00000000000000000000000000000111
    PMA_CH1_REG_RX_RESERVED_285_283 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_RESERVED_286 = FALSE
    PMA_CH1_REG_RX_SIGDET_IC_I = 32'b00000000000000000000000000001010
    PMA_CH1_REG_RX_OOB_DETECTOR_RESET_N_OW = FALSE
    PMA_CH1_REG_RX_OOB_DETECTOR_RESET_N = FALSE
    PMA_CH1_REG_RX_OOB_DETECTOR_PD_OW = FALSE
    PMA_CH1_REG_RX_OOB_DETECTOR_PD = ON
    PMA_CH1_REG_RX_LS_MODE_EN = FALSE
    PMA_CH1_REG_ANA_RX_EQ1_R_SET_FB_O_SEL = TRUE
    PMA_CH1_REG_ANA_RX_EQ2_R_SET_FB_O_SEL = TRUE
    PMA_CH1_REG_RX_EQ1_R_SET_TOP = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_EQ1_R_SET_FB = 32'b00000000000000000000000000001111
    PMA_CH1_REG_RX_EQ1_C_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_EQ1_OFF = FALSE
    PMA_CH1_REG_RX_EQ2_R_SET_TOP = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_EQ2_R_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_EQ2_C_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_EQ2_OFF = FALSE
    PMA_CH1_REG_EQ_DAC = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_ICTRL_EQ = 32'b00000000000000000000000000000010
    PMA_CH1_REG_EQ_DC_CALIB_EN = TRUE
    PMA_CH1_REG_EQ_DC_CALIB_SEL = FALSE
    PMA_CH1_REG_RX_RESERVED_337_330 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_RESERVED_345_338 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_RESERVED_353_346 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RX_RESERVED_361_354 = 32'b00000000000000000000000000000000
    PMA_CH1_CTLE_CTRL_REG_I = 32'b00000000000000000000000000000000
    PMA_CH1_CTLE_REG_FORCE_SEL_I = FALSE
    PMA_CH1_CTLE_REG_HOLD_I = FALSE
    PMA_CH1_CTLE_REG_INIT_DAC_I = 32'b00000000000000000000000000000000
    PMA_CH1_CTLE_REG_POLARITY_I = FALSE
    PMA_CH1_CTLE_REG_SHIFTER_GAIN_I = 32'b00000000000000000000000000000001
    PMA_CH1_CTLE_REG_THRESHOLD_I = 32'b00000000000000000000110000000000
    PMA_CH1_REG_RX_RES_TRIM_EN = TRUE
    PMA_CH1_REG_RX_RESERVED_393_389 = 32'b00000000000000000000000000000000
    PMA_CH1_CFG_RX_LANE_POWERUP = ON
    PMA_CH1_CFG_RX_PMA_RSTN = TRUE
    PMA_CH1_INT_PMA_RX_MASK_0 = FALSE
    PMA_CH1_INT_PMA_RX_CLR_0 = FALSE
    PMA_CH1_CFG_CTLE_ADP_RSTN = TRUE
    PMA_CH1_REG_TX_PD = ON
    PMA_CH1_REG_TX_PD_OW = FALSE
    PMA_CH1_REG_TX_MAIN_PRE_Z = FALSE
    PMA_CH1_REG_TX_MAIN_PRE_Z_OW = FALSE
    PMA_CH1_REG_TX_BEACON_TIMER_SEL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RXDET_REQ_OW = FALSE
    PMA_CH1_REG_TX_RXDET_REQ = FALSE
    PMA_CH1_REG_TX_BEACON_EN_OW = FALSE
    PMA_CH1_REG_TX_BEACON_EN = FALSE
    PMA_CH1_REG_TX_EI_EN_OW = FALSE
    PMA_CH1_REG_TX_EI_EN = FALSE
    PMA_CH1_REG_TX_BIT_CONV = FALSE
    PMA_CH1_REG_TX_RES_CAL = 32'b00000000000000000000000000110000
    PMA_CH1_REG_TX_RESERVED_19 = FALSE
    PMA_CH1_REG_TX_RESERVED_25_20 = 32'b00000000000000000000000000100000
    PMA_CH1_REG_TX_RESERVED_33_26 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_41_34 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_49_42 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_57_50 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_SYNC_OW = FALSE
    PMA_CH1_REG_TX_SYNC = FALSE
    PMA_CH1_REG_TX_PD_POST = ON
    PMA_CH1_REG_TX_PD_POST_OW = TRUE
    PMA_CH1_REG_TX_RESET_N_OW = FALSE
    PMA_CH1_REG_TX_RESET_N = TRUE
    PMA_CH1_REG_TX_RESERVED_64 = FALSE
    PMA_CH1_REG_TX_RESERVED_65 = TRUE
    PMA_CH1_REG_TX_BUSWIDTH_OW = TRUE
    PMA_CH1_REG_TX_BUSWIDTH = 20BIT
    PMA_CH1_REG_PLL_READY_OW = FALSE
    PMA_CH1_REG_PLL_READY = TRUE
    PMA_CH1_REG_TX_RESERVED_72 = FALSE
    PMA_CH1_REG_TX_RESERVED_73 = FALSE
    PMA_CH1_REG_TX_RESERVED_74 = FALSE
    PMA_CH1_REG_EI_PCLK_DELAY_SEL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_77 = FALSE
    PMA_CH1_REG_TX_RESERVED_83_78 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_89_84 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_95_90 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_101_96 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_107_102 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_113_108 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_AMP_DAC0 = 32'b00000000000000000000000000011001
    PMA_CH1_REG_TX_AMP_DAC1 = 32'b00000000000000000000000000010011
    PMA_CH1_REG_TX_AMP_DAC2 = 32'b00000000000000000000000000001110
    PMA_CH1_REG_TX_AMP_DAC3 = 32'b00000000000000000000000000001001
    PMA_CH1_REG_TX_RESERVED_143_138 = 32'b00000000000000000000000000000101
    PMA_CH1_REG_TX_MARGIN = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_MARGIN_OW = FALSE
    PMA_CH1_REG_TX_RESERVED_149_148 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_150 = FALSE
    PMA_CH1_REG_TX_SWING = FALSE
    PMA_CH1_REG_TX_SWING_OW = FALSE
    PMA_CH1_REG_TX_RESERVED_153 = FALSE
    PMA_CH1_REG_TX_RXDET_THRESHOLD = 84MV
    PMA_CH1_REG_TX_RESERVED_157_156 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_BEACON_OSC_CTRL = FALSE
    PMA_CH1_REG_TX_RESERVED_160_159 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_162_161 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_TX2RX_SLPBACK_EN = FALSE
    PMA_CH1_REG_TX_PCLK_EDGE_SEL = FALSE
    PMA_CH1_REG_TX_RXDET_STATUS_OW = FALSE
    PMA_CH1_REG_TX_RXDET_STATUS = TRUE
    PMA_CH1_REG_TX_PRBS_GEN_EN = FALSE
    PMA_CH1_REG_TX_PRBS_GEN_WIDTH_SEL = 20BIT
    PMA_CH1_REG_TX_PRBS_SEL = PRBS7
    PMA_CH1_REG_TX_UDP_DATA_7_TO_0 = 32'b00000000000000000000000000000101
    PMA_CH1_REG_TX_UDP_DATA_15_TO_8 = 32'b00000000000000000000000011101011
    PMA_CH1_REG_TX_UDP_DATA_19_TO_16 = 32'b00000000000000000000000000000011
    PMA_CH1_REG_TX_RESERVED_192 = FALSE
    PMA_CH1_REG_TX_FIFO_WP_CTRL = 32'b00000000000000000000000000000100
    PMA_CH1_REG_TX_FIFO_EN = FALSE
    PMA_CH1_REG_TX_DATA_MUX_SEL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_ERR_INSERT = FALSE
    PMA_CH1_REG_TX_RESERVED_203_200 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_204 = FALSE
    PMA_CH1_REG_TX_SATA_EN = FALSE
    PMA_CH1_REG_TX_RESERVED_207_206 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_RATE_CHANGE_TXPCLK_ON_OW = FALSE
    PMA_CH1_REG_RATE_CHANGE_TXPCLK_ON = TRUE
    PMA_CH1_REG_TX_CFG_POST1 = 32'b00000000000000000000000000010011
    PMA_CH1_REG_TX_CFG_POST2 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_DEEMP = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_DEEMP_OW = FALSE
    PMA_CH1_REG_TX_RESERVED_224_223 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RESERVED_225 = FALSE
    PMA_CH1_REG_TX_RESERVED_229_226 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_OOB_DELAY_SEL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_POLARITY = NORMAL
    PMA_CH1_REG_ANA_TX_JTAG_DATA_O_SEL = FALSE
    PMA_CH1_REG_TX_RESERVED_236 = FALSE
    PMA_CH1_REG_TX_LS_MODE_EN = FALSE
    PMA_CH1_REG_TX_JTAG_MODE_EN_OW = FALSE
    PMA_CH1_REG_TX_JTAG_MODE_EN = FALSE
    PMA_CH1_REG_RX_JTAG_MODE_EN_OW = FALSE
    PMA_CH1_REG_RX_JTAG_MODE_EN = FALSE
    PMA_CH1_REG_RX_JTAG_OE = TRUE
    PMA_CH1_REG_RX_ACJTAG_VHYSTSEL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_RES_CAL_EN = FALSE
    PMA_CH1_REG_RX_TERM_MODE_CTRL = 32'b00000000000000000000000000000101
    PMA_CH1_REG_TX_RESERVED_251_250 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_PLPBK_TXPCLK_EN = FALSE
    PMA_CH1_REG_TX_RESERVED_253 = FALSE
    PMA_CH1_REG_TX_RESERVED_254 = FALSE
    PMA_CH1_REG_TX_RESERVED_255 = FALSE
    PMA_CH1_REG_TX_RESERVED_256 = FALSE
    PMA_CH1_REG_TX_RESERVED_257 = FALSE
    PMA_CH1_REG_TX_PH_SEL = 32'b00000000000000000000000000000001
    PMA_CH1_REG_TX_CFG_PRE = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_CFG_MAIN = 32'b00000000000000000000000000000000
    PMA_CH1_REG_CFG_POST = 32'b00000000000000000000000000001100
    PMA_CH1_REG_PD_MAIN = TRUE
    PMA_CH1_REG_PD_PRE = TRUE
    PMA_CH1_REG_TX_LS_DATA = FALSE
    PMA_CH1_REG_TX_DCC_BUF_SZ_SEL = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_DCC_CAL_CUR_TUNE = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_DCC_CAL_EN = FALSE
    PMA_CH1_REG_TX_DCC_CUR_SS = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_DCC_FA_CTRL = FALSE
    PMA_CH1_REG_TX_DCC_RI_CTRL = FALSE
    PMA_CH1_REG_ATB_SEL_2_TO_0 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_ATB_SEL_9_TO_3 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_CFG_7_TO_0 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_CFG_15_TO_8 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_CFG_23_TO_16 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_CFG_31_TO_24 = 32'b00000000000000000000000010000000
    PMA_CH1_REG_TX_OOB_EI_EN = FALSE
    PMA_CH1_REG_TX_OOB_EI_EN_OW = FALSE
    PMA_CH1_REG_TX_BEACON_EN_DELAYED = FALSE
    PMA_CH1_REG_TX_BEACON_EN_DELAYED_OW = FALSE
    PMA_CH1_REG_TX_JTAG_DATA = FALSE
    PMA_CH1_REG_TX_RXDET_TIMER_SEL = 32'b00000000000000000000000001010111
    PMA_CH1_REG_TX_CFG1_7_0 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_CFG1_15_8 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_CFG1_23_16 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_TX_CFG1_31_24 = 32'b00000000000000000000000000000000
    PMA_CH1_REG_CFG_LANE_POWERUP = ON
    PMA_CH1_REG_CFG_TX_LANE_POWERUP_CLKPATH = TRUE
    PMA_CH1_REG_CFG_TX_LANE_POWERUP_PISO = TRUE
    PMA_CH1_REG_CFG_TX_LANE_POWERUP_DRIVER = TRUE
    CH2_MUX_BIAS = 32'b00000000000000000000000000000010
    CH2_PD_CLK = 32'b00000000000000000000000000000000
    CH2_REG_SYNC = 32'b00000000000000000000000000000000
    CH2_REG_SYNC_OW = 32'b00000000000000000000000000000000
    CH2_PLL_LOCK_OW = 32'b00000000000000000000000000000000
    CH2_PLL_LOCK_OW_EN = 32'b00000000000000000000000000000000
    PCS_CH2_SLAVE = 32'b00000000000000000000000000000000
    PCS_CH2_BYPASS_WORD_ALIGN = TRUE
    PCS_CH2_BYPASS_DENC = TRUE
    PCS_CH2_BYPASS_BONDING = TRUE
    PCS_CH2_BYPASS_CTC = TRUE
    PCS_CH2_BYPASS_GEAR = FALSE
    PCS_CH2_BYPASS_BRIDGE = FALSE
    PCS_CH2_BYPASS_BRIDGE_FIFO = FALSE
    PCS_CH2_DATA_MODE = X16
    PCS_CH2_RX_POLARITY_INV = DELAY
    PCS_CH2_ALIGN_MODE = 1GB
    PCS_CH2_SAMP_16B = X16
    PCS_CH2_FARLP_PWR_REDUCTION = FALSE
    PCS_CH2_COMMA_REG0 = 32'b00000000000000000000000000000000
    PCS_CH2_COMMA_MASK = 32'b00000000000000000000000000000000
    PCS_CH2_CEB_MODE = 10GB
    PCS_CH2_CTC_MODE = 1SKIP
    PCS_CH2_A_REG = 32'b00000000000000000000000001111100
    PCS_CH2_GE_AUTO_EN = FALSE
    PCS_CH2_SKIP_REG0 = 32'b00000000000000000000000000000000
    PCS_CH2_SKIP_REG1 = 32'b00000000000000000000000000000000
    PCS_CH2_SKIP_REG2 = 32'b00000000000000000000000000000000
    PCS_CH2_SKIP_REG3 = 32'b00000000000000000000000000000000
    PCS_CH2_DEC_DUAL = FALSE
    PCS_CH2_SPLIT = FALSE
    PCS_CH2_FIFOFLAG_CTC = FALSE
    PCS_CH2_COMMA_DET_MODE = COMMA_PATTERN
    PCS_CH2_ERRDETECT_SILENCE = TRUE
    PCS_CH2_PMA_RCLK_POLINV = PMA_RCLK
    PCS_CH2_PCS_RCLK_SEL = PMA_RCLK
    PCS_CH2_CB_RCLK_SEL = PMA_RCLK
    PCS_CH2_AFTER_CTC_RCLK_SEL = PMA_RCLK
    PCS_CH2_RCLK_POLINV = RCLK
    PCS_CH2_BRIDGE_RCLK_SEL = PMA_RCLK
    PCS_CH2_PCS_RCLK_EN = FALSE
    PCS_CH2_CB_RCLK_EN = FALSE
    PCS_CH2_AFTER_CTC_RCLK_EN = FALSE
    PCS_CH2_AFTER_CTC_RCLK_EN_GB = TRUE
    PCS_CH2_PCS_RX_RSTN = TRUE
    PCS_CH2_PCIE_SLAVE = MASTER
    PCS_CH2_RX_64B66B_67B = NORMAL
    PCS_CH2_RX_BRIDGE_CLK_POLINV = RX_BRIDGE_CLK
    PCS_CH2_PCS_CB_RSTN = TRUE
    PCS_CH2_TX_BRIDGE_GEAR_SEL = FALSE
    PCS_CH2_TX_BYPASS_BRIDGE_UINT = FALSE
    PCS_CH2_TX_BYPASS_BRIDGE_FIFO = FALSE
    PCS_CH2_TX_BYPASS_GEAR = FALSE
    PCS_CH2_TX_BYPASS_ENC = TRUE
    PCS_CH2_TX_BYPASS_BIT_SLIP = TRUE
    PCS_CH2_TX_GEAR_SPLIT = TRUE
    PCS_CH2_TX_DRIVE_REG_MODE = NO_CHANGE
    PCS_CH2_TX_BIT_SLIP_CYCLES = 32'b00000000000000000000000000000000
    PCS_CH2_INT_TX_MASK_0 = FALSE
    PCS_CH2_INT_TX_MASK_1 = FALSE
    PCS_CH2_INT_TX_MASK_2 = FALSE
    PCS_CH2_INT_TX_CLR_0 = FALSE
    PCS_CH2_INT_TX_CLR_1 = FALSE
    PCS_CH2_INT_TX_CLR_2 = FALSE
    PCS_CH2_TX_PMA_TCLK_POLINV = PMA_TCLK
    PCS_CH2_TX_PCS_CLK_EN_SEL = TRUE
    PCS_CH2_TX_BRIDGE_TCLK_SEL = TCLK
    PCS_CH2_TX_TCLK_POLINV = TCLK
    PCS_CH2_PCS_TCLK_SEL = PMA_TCLK
    PCS_CH2_TX_PCS_TX_RSTN = TRUE
    PCS_CH2_TX_SLAVE = MASTER
    PCS_CH2_TX_GEAR_CLK_EN_SEL = FALSE
    PCS_CH2_DATA_WIDTH_MODE = X16
    PCS_CH2_TX_64B66B_67B = NORMAL
    PCS_CH2_GEAR_TCLK_SEL = PMA_TCLK
    PCS_CH2_TX_TCLK2FABRIC_SEL = TRUE
    PCS_CH2_TX_OUTZZ = FALSE
    PCS_CH2_ENC_DUAL = TRUE
    PCS_CH2_TX_BITSLIP_DATA_MODE = X10
    PCS_CH2_TX_BRIDGE_CLK_POLINV = TX_BRIDGE_CLK
    PCS_CH2_COMMA_REG1 = 32'b00000000000000000000001111111111
    PCS_CH2_RAPID_IMAX = 32'b00000000000000000000000000000101
    PCS_CH2_RAPID_VMIN_1 = 32'b00000000000000000000000011111010
    PCS_CH2_RAPID_VMIN_2 = 32'b00000000000000000000000000000001
    PCS_CH2_RX_PRBS_MODE = DISABLE
    PCS_CH2_RX_ERRCNT_CLR = FALSE
    PCS_CH2_PRBS_ERR_LPBK = FALSE
    PCS_CH2_TX_PRBS_MODE = DISABLE
    PCS_CH2_TX_INSERT_ER = FALSE
    PCS_CH2_ENABLE_PRBS_GEN = FALSE
    PCS_CH2_DEFAULT_RADDR = 32'b00000000000000000000000000000110
    PCS_CH2_MASTER_CHECK_OFFSET = 32'b00000000000000000000000000000100
    PCS_CH2_DELAY_SET = 32'b00000000000000000000000000000001
    PCS_CH2_SEACH_OFFSET = 80BIT
    PCS_CH2_CEB_RAPIDLS_MMAX = 32'b00000000000000000000000000000101
    PCS_CH2_CTC_AFULL = 32'b00000000000000000000000000010100
    PCS_CH2_CTC_AEMPTY = 32'b00000000000000000000000000001100
    PCS_CH2_CTC_CONTI_SKP_SET = 32'b00000000000000000000000000000000
    PCS_CH2_FAR_LOOP = FALSE
    PCS_CH2_NEAR_LOOP = FALSE
    PCS_CH2_PMA_TX2RX_PLOOP_EN = FALSE
    PCS_CH2_PMA_TX2RX_SLOOP_EN = FALSE
    PCS_CH2_PMA_RX2TX_PLOOP_EN = FALSE
    PCS_CH2_INT_RX_MASK_0 = FALSE
    PCS_CH2_INT_RX_MASK_1 = FALSE
    PCS_CH2_INT_RX_MASK_2 = FALSE
    PCS_CH2_INT_RX_MASK_3 = FALSE
    PCS_CH2_INT_RX_MASK_4 = FALSE
    PCS_CH2_INT_RX_MASK_5 = FALSE
    PCS_CH2_INT_RX_MASK_6 = FALSE
    PCS_CH2_INT_RX_MASK_7 = FALSE
    PCS_CH2_INT_RX_CLR_0 = FALSE
    PCS_CH2_INT_RX_CLR_1 = FALSE
    PCS_CH2_INT_RX_CLR_2 = FALSE
    PCS_CH2_INT_RX_CLR_3 = FALSE
    PCS_CH2_INT_RX_CLR_4 = FALSE
    PCS_CH2_INT_RX_CLR_5 = FALSE
    PCS_CH2_INT_RX_CLR_6 = FALSE
    PCS_CH2_INT_RX_CLR_7 = FALSE
    PCS_CH2_CA_RSTN_RX = FALSE
    PCS_CH2_CA_DYN_DLY_EN_RX = FALSE
    PCS_CH2_CA_DYN_DLY_SEL_RX = FALSE
    PCS_CH2_CA_RX = 32'b00000000000000000000000000000000
    PCS_CH2_CA_RSTN_TX = FALSE
    PCS_CH2_CA_DYN_DLY_EN_TX = FALSE
    PCS_CH2_CA_DYN_DLY_SEL_TX = FALSE
    PCS_CH2_CA_TX = 32'b00000000000000000000000000000000
    PCS_CH2_RXPRBS_PWR_REDUCTION = NORMAL
    PCS_CH2_WDALIGN_PWR_REDUCTION = NORMAL
    PCS_CH2_RXDEC_PWR_REDUCTION = NORMAL
    PCS_CH2_RXCB_PWR_REDUCTION = NORMAL
    PCS_CH2_RXCTC_PWR_REDUCTION = NORMAL
    PCS_CH2_RXGEAR_PWR_REDUCTION = NORMAL
    PCS_CH2_RXBRG_PWR_REDUCTION = NORMAL
    PCS_CH2_RXTEST_PWR_REDUCTION = NORMAL
    PCS_CH2_TXBRG_PWR_REDUCTION = NORMAL
    PCS_CH2_TXGEAR_PWR_REDUCTION = NORMAL
    PCS_CH2_TXENC_PWR_REDUCTION = NORMAL
    PCS_CH2_TXBSLP_PWR_REDUCTION = NORMAL
    PCS_CH2_TXPRBS_PWR_REDUCTION = NORMAL
    PMA_CH2_REG_RX_PD = ON
    PMA_CH2_REG_RX_PD_EN = FALSE
    PMA_CH2_REG_RX_RESERVED_2 = FALSE
    PMA_CH2_REG_RX_RESERVED_3 = FALSE
    PMA_CH2_REG_RX_DATAPATH_PD = ON
    PMA_CH2_REG_RX_DATAPATH_PD_EN = TRUE
    PMA_CH2_REG_RX_SIGDET_PD = ON
    PMA_CH2_REG_RX_SIGDET_PD_EN = FALSE
    PMA_CH2_REG_RX_DCC_RST_N = TRUE
    PMA_CH2_REG_RX_DCC_RST_N_EN = FALSE
    PMA_CH2_REG_RX_CDR_RST_N = TRUE
    PMA_CH2_REG_RX_CDR_RST_N_EN = FALSE
    PMA_CH2_REG_RX_SIGDET_RST_N = TRUE
    PMA_CH2_REG_RX_SIGDET_RST_N_EN = FALSE
    PMA_CH2_REG_RXPCLK_SLIP = FALSE
    PMA_CH2_REG_RXPCLK_SLIP_OW = FALSE
    PMA_CH2_REG_RX_PCLKSWITCH_RST_N = TRUE
    PMA_CH2_REG_RX_PCLKSWITCH_RST_N_EN = FALSE
    PMA_CH2_REG_RX_PCLKSWITCH = FALSE
    PMA_CH2_REG_RX_PCLKSWITCH_EN = FALSE
    PMA_CH2_REG_RX_HIGHZ = FALSE
    PMA_CH2_REG_RX_HIGHZ_EN = FALSE
    PMA_CH2_REG_RX_SIGDET_CLK_WINDOW = FALSE
    PMA_CH2_REG_RX_SIGDET_CLK_WINDOW_OW = FALSE
    PMA_CH2_REG_RX_PD_BIAS_RX = FALSE
    PMA_CH2_REG_RX_PD_BIAS_RX_OW = FALSE
    PMA_CH2_REG_RX_RESET_N = FALSE
    PMA_CH2_REG_RX_RESET_N_OW = FALSE
    PMA_CH2_REG_RX_RESERVED_29_28 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_BUSWIDTH = 16BIT
    PMA_CH2_REG_RX_BUSWIDTH_EN = TRUE
    PMA_CH2_REG_RX_RATE = DIV1
    PMA_CH2_REG_RX_RESERVED_36 = FALSE
    PMA_CH2_REG_RX_RATE_EN = FALSE
    PMA_CH2_REG_RX_RES_TRIM = 32'b00000000000000000000000000101110
    PMA_CH2_REG_RX_RESERVED_44 = FALSE
    PMA_CH2_REG_RX_RESERVED_45 = FALSE
    PMA_CH2_REG_RX_SIGDET_STATUS_EN = FALSE
    PMA_CH2_REG_RX_RESERVED_48_47 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_ICTRL_SIGDET = 32'b00000000000000000000000000000101
    PMA_CH2_REG_CDR_READY_THD = 32'b00000000000000000000101010101110
    PMA_CH2_REG_RX_RESERVED_65 = FALSE
    PMA_CH2_REG_RX_PCLK_EDGE_SEL = POS_EDGE
    PMA_CH2_REG_RX_PIBUF_IC = 32'b00000000000000000000000000000001
    PMA_CH2_REG_RX_RESERVED_69 = FALSE
    PMA_CH2_REG_RX_DCC_IC_RX = 32'b00000000000000000000000000000001
    PMA_CH2_REG_CDR_READY_CHECK_CTRL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_ICTRL_TRX = 100PCT
    PMA_CH2_REG_RX_RESERVED_77_76 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_RESERVED_79_78 = 32'b00000000000000000000000000000001
    PMA_CH2_REG_RX_RESERVED_81_80 = 32'b00000000000000000000000000000001
    PMA_CH2_REG_RX_ICTRL_PIBUF = 100PCT
    PMA_CH2_REG_RX_ICTRL_PI = 100PCT
    PMA_CH2_REG_RX_ICTRL_DCC = 100PCT
    PMA_CH2_REG_RX_RESERVED_89_88 = 32'b00000000000000000000000000000001
    PMA_CH2_REG_TX_RATE = DIV1
    PMA_CH2_REG_RX_RESERVED_92 = FALSE
    PMA_CH2_REG_TX_RATE_EN = FALSE
    PMA_CH2_REG_RX_TX2RX_PLPBK_RST_N = TRUE
    PMA_CH2_REG_RX_TX2RX_PLPBK_RST_N_EN = FALSE
    PMA_CH2_REG_RX_TX2RX_PLPBK_EN = FALSE
    PMA_CH2_REG_TXCLK_SEL = PLL
    PMA_CH2_REG_RX_DATA_POLARITY = NORMAL
    PMA_CH2_REG_RX_ERR_INSERT = FALSE
    PMA_CH2_REG_UDP_CHK_EN = FALSE
    PMA_CH2_REG_PRBS_SEL = PRBS7
    PMA_CH2_REG_PRBS_CHK_EN = FALSE
    PMA_CH2_REG_PRBS_CHK_WIDTH_SEL = 16BIT
    PMA_CH2_REG_BIST_CHK_PAT_SEL = PRBS
    PMA_CH2_REG_LOAD_ERR_CNT = FALSE
    PMA_CH2_REG_CHK_COUNTER_EN = FALSE
    PMA_CH2_REG_CDR_PROP_GAIN = 32'b00000000000000000000000000000111
    PMA_CH2_REG_CDR_PROP_TURBO_GAIN = 32'b00000000000000000000000000000101
    PMA_CH2_REG_CDR_INT_GAIN = 32'b00000000000000000000000000000100
    PMA_CH2_REG_CDR_INT_TURBO_GAIN = 32'b00000000000000000000000000000101
    PMA_CH2_REG_CDR_INT_SAT_MAX = 32'b00000000000000000000001100000000
    PMA_CH2_REG_CDR_INT_SAT_MIN = 32'b00000000000000000000000011111111
    PMA_CH2_REG_CDR_INT_RST = FALSE
    PMA_CH2_REG_CDR_INT_RST_OW = FALSE
    PMA_CH2_REG_CDR_PROP_RST = FALSE
    PMA_CH2_REG_CDR_PROP_RST_OW = FALSE
    PMA_CH2_REG_CDR_LOCK_RST = FALSE
    PMA_CH2_REG_CDR_LOCK_RST_OW = FALSE
    PMA_CH2_REG_CDR_RX_PI_FORCE_SEL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_CDR_RX_PI_FORCE_D = 32'b00000000000000000000000000000000
    PMA_CH2_REG_CDR_LOCK_TIMER = 25_6U
    PMA_CH2_REG_CDR_TURBO_MODE_TIMER = 32'b00000000000000000000000000000001
    PMA_CH2_REG_CDR_LOCK_VAL = FALSE
    PMA_CH2_REG_CDR_LOCK_OW = FALSE
    PMA_CH2_REG_CDR_INT_SAT_DET_EN = TRUE
    PMA_CH2_REG_CDR_SAT_AUTO_DIS = TRUE
    PMA_CH2_REG_CDR_GAIN_AUTO = FALSE
    PMA_CH2_REG_CDR_TURBO_GAIN_AUTO = FALSE
    PMA_CH2_REG_RX_RESERVED_171_167 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_RESERVED_175_172 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_CDR_SAT_DET_STATUS_EN = FALSE
    PMA_CH2_REG_CDR_SAT_DET_STATUS_RESET_EN = FALSE
    PMA_CH2_REG_CDR_PI_CTRL_RST = FALSE
    PMA_CH2_REG_CDR_PI_CTRL_RST_OW = FALSE
    PMA_CH2_REG_CDR_SAT_DET_RST = FALSE
    PMA_CH2_REG_CDR_SAT_DET_RST_OW = FALSE
    PMA_CH2_REG_CDR_SAT_DET_STICKY_RST = FALSE
    PMA_CH2_REG_CDR_SAT_DET_STICKY_RST_OW = FALSE
    PMA_CH2_REG_CDR_SIGDET_STATUS_DIS = FALSE
    PMA_CH2_REG_CDR_SAT_DET_TIMER = 32'b00000000000000000000000000000010
    PMA_CH2_REG_CDR_SAT_DET_STATUS_VAL = FALSE
    PMA_CH2_REG_CDR_SAT_DET_STATUS_OW = FALSE
    PMA_CH2_REG_CDR_TURBO_MODE_EN = TRUE
    PMA_CH2_REG_RX_RESERVED_190 = FALSE
    PMA_CH2_REG_RX_RESERVED_193_191 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_CDR_STATUS_FIFO_EN = TRUE
    PMA_CH2_REG_PMA_TEST_SEL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_OOB_COMWAKE_GAP_MIN = 32'b00000000000000000000000000000011
    PMA_CH2_REG_OOB_COMWAKE_GAP_MAX = 32'b00000000000000000000000000001011
    PMA_CH2_REG_OOB_COMINIT_GAP_MIN = 32'b00000000000000000000000000001111
    PMA_CH2_REG_OOB_COMINIT_GAP_MAX = 32'b00000000000000000000000000100011
    PMA_CH2_REG_RX_RESERVED_227_226 = 32'b00000000000000000000000000000001
    PMA_CH2_REG_COMWAKE_STATUS_CLEAR = 32'b00000000000000000000000000000000
    PMA_CH2_REG_COMINIT_STATUS_CLEAR = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_SYNC_RST_N_EN = FALSE
    PMA_CH2_REG_RX_SYNC_RST_N = TRUE
    PMA_CH2_REG_RX_RESERVED_233_232 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_RESERVED_235_234 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_SATA_COMINIT_OW = FALSE
    PMA_CH2_REG_RX_SATA_COMINIT = FALSE
    PMA_CH2_REG_RX_SATA_COMWAKE_OW = FALSE
    PMA_CH2_REG_RX_SATA_COMWAKE = FALSE
    PMA_CH2_REG_RX_RESERVED_241_240 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_DCC_DISABLE = FALSE
    PMA_CH2_REG_RX_RESERVED_243 = FALSE
    PMA_CH2_REG_RX_SLIP_SEL_EN = FALSE
    PMA_CH2_REG_RX_SLIP_SEL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_SLIP_EN = FALSE
    PMA_CH2_REG_RX_SIGDET_STATUS_SEL = 32'b00000000000000000000000000000101
    PMA_CH2_REG_RX_SIGDET_FSM_RST_N = TRUE
    PMA_CH2_REG_RX_RESERVED_254 = FALSE
    PMA_CH2_REG_RX_SIGDET_STATUS = FALSE
    PMA_CH2_REG_RX_SIGDET_VTH = 72MV
    PMA_CH2_REG_RX_SIGDET_GRM = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_SIGDET_PULSE_EXT = FALSE
    PMA_CH2_REG_RX_SIGDET_CH2_SEL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_SIGDET_CH2_CHK_WINDOW = 32'b00000000000000000000000000000011
    PMA_CH2_REG_RX_SIGDET_CHK_WINDOW_EN = TRUE
    PMA_CH2_REG_RX_SIGDET_NOSIG_COUNT_SETTING = 32'b00000000000000000000000000000100
    PMA_CH2_REG_SLIP_FIFO_INV_EN = FALSE
    PMA_CH2_REG_SLIP_FIFO_INV = POS_EDGE
    PMA_CH2_REG_RX_SIGDET_OOB_DET_COUNT_VAL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_SIGDET_4OOB_DET_SEL = 32'b00000000000000000000000000000111
    PMA_CH2_REG_RX_RESERVED_285_283 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_RESERVED_286 = FALSE
    PMA_CH2_REG_RX_SIGDET_IC_I = 32'b00000000000000000000000000001010
    PMA_CH2_REG_RX_OOB_DETECTOR_RESET_N_OW = FALSE
    PMA_CH2_REG_RX_OOB_DETECTOR_RESET_N = FALSE
    PMA_CH2_REG_RX_OOB_DETECTOR_PD_OW = FALSE
    PMA_CH2_REG_RX_OOB_DETECTOR_PD = ON
    PMA_CH2_REG_RX_LS_MODE_EN = FALSE
    PMA_CH2_REG_ANA_RX_EQ1_R_SET_FB_O_SEL = TRUE
    PMA_CH2_REG_ANA_RX_EQ2_R_SET_FB_O_SEL = TRUE
    PMA_CH2_REG_RX_EQ1_R_SET_TOP = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_EQ1_R_SET_FB = 32'b00000000000000000000000000001111
    PMA_CH2_REG_RX_EQ1_C_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_EQ1_OFF = FALSE
    PMA_CH2_REG_RX_EQ2_R_SET_TOP = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_EQ2_R_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_EQ2_C_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_EQ2_OFF = FALSE
    PMA_CH2_REG_EQ_DAC = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_ICTRL_EQ = 32'b00000000000000000000000000000010
    PMA_CH2_REG_EQ_DC_CALIB_EN = TRUE
    PMA_CH2_REG_EQ_DC_CALIB_SEL = FALSE
    PMA_CH2_REG_RX_RESERVED_337_330 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_RESERVED_345_338 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_RESERVED_353_346 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RX_RESERVED_361_354 = 32'b00000000000000000000000000000000
    PMA_CH2_CTLE_CTRL_REG_I = 32'b00000000000000000000000000000000
    PMA_CH2_CTLE_REG_FORCE_SEL_I = FALSE
    PMA_CH2_CTLE_REG_HOLD_I = FALSE
    PMA_CH2_CTLE_REG_INIT_DAC_I = 32'b00000000000000000000000000000000
    PMA_CH2_CTLE_REG_POLARITY_I = FALSE
    PMA_CH2_CTLE_REG_SHIFTER_GAIN_I = 32'b00000000000000000000000000000001
    PMA_CH2_CTLE_REG_THRESHOLD_I = 32'b00000000000000000000110000000000
    PMA_CH2_REG_RX_RES_TRIM_EN = TRUE
    PMA_CH2_REG_RX_RESERVED_393_389 = 32'b00000000000000000000000000000000
    PMA_CH2_CFG_RX_LANE_POWERUP = ON
    PMA_CH2_CFG_RX_PMA_RSTN = TRUE
    PMA_CH2_INT_PMA_RX_MASK_0 = FALSE
    PMA_CH2_INT_PMA_RX_CLR_0 = FALSE
    PMA_CH2_CFG_CTLE_ADP_RSTN = TRUE
    PMA_CH2_REG_TX_PD = ON
    PMA_CH2_REG_TX_PD_OW = FALSE
    PMA_CH2_REG_TX_MAIN_PRE_Z = FALSE
    PMA_CH2_REG_TX_MAIN_PRE_Z_OW = FALSE
    PMA_CH2_REG_TX_BEACON_TIMER_SEL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RXDET_REQ_OW = FALSE
    PMA_CH2_REG_TX_RXDET_REQ = FALSE
    PMA_CH2_REG_TX_BEACON_EN_OW = FALSE
    PMA_CH2_REG_TX_BEACON_EN = FALSE
    PMA_CH2_REG_TX_EI_EN_OW = FALSE
    PMA_CH2_REG_TX_EI_EN = FALSE
    PMA_CH2_REG_TX_BIT_CONV = FALSE
    PMA_CH2_REG_TX_RES_CAL = 32'b00000000000000000000000000110000
    PMA_CH2_REG_TX_RESERVED_19 = FALSE
    PMA_CH2_REG_TX_RESERVED_25_20 = 32'b00000000000000000000000000100000
    PMA_CH2_REG_TX_RESERVED_33_26 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_41_34 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_49_42 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_57_50 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_SYNC_OW = FALSE
    PMA_CH2_REG_TX_SYNC = FALSE
    PMA_CH2_REG_TX_PD_POST = OFF
    PMA_CH2_REG_TX_PD_POST_OW = TRUE
    PMA_CH2_REG_TX_RESET_N_OW = FALSE
    PMA_CH2_REG_TX_RESET_N = TRUE
    PMA_CH2_REG_TX_RESERVED_64 = FALSE
    PMA_CH2_REG_TX_RESERVED_65 = TRUE
    PMA_CH2_REG_TX_BUSWIDTH_OW = TRUE
    PMA_CH2_REG_TX_BUSWIDTH = 16BIT
    PMA_CH2_REG_PLL_READY_OW = FALSE
    PMA_CH2_REG_PLL_READY = TRUE
    PMA_CH2_REG_TX_RESERVED_72 = FALSE
    PMA_CH2_REG_TX_RESERVED_73 = FALSE
    PMA_CH2_REG_TX_RESERVED_74 = FALSE
    PMA_CH2_REG_EI_PCLK_DELAY_SEL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_77 = FALSE
    PMA_CH2_REG_TX_RESERVED_83_78 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_89_84 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_95_90 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_101_96 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_107_102 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_113_108 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_AMP_DAC0 = 32'b00000000000000000000000000011001
    PMA_CH2_REG_TX_AMP_DAC1 = 32'b00000000000000000000000000010011
    PMA_CH2_REG_TX_AMP_DAC2 = 32'b00000000000000000000000000001110
    PMA_CH2_REG_TX_AMP_DAC3 = 32'b00000000000000000000000000001001
    PMA_CH2_REG_TX_RESERVED_143_138 = 32'b00000000000000000000000000000101
    PMA_CH2_REG_TX_MARGIN = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_MARGIN_OW = FALSE
    PMA_CH2_REG_TX_RESERVED_149_148 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_150 = FALSE
    PMA_CH2_REG_TX_SWING = FALSE
    PMA_CH2_REG_TX_SWING_OW = FALSE
    PMA_CH2_REG_TX_RESERVED_153 = FALSE
    PMA_CH2_REG_TX_RXDET_THRESHOLD = 84MV
    PMA_CH2_REG_TX_RESERVED_157_156 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_BEACON_OSC_CTRL = FALSE
    PMA_CH2_REG_TX_RESERVED_160_159 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_162_161 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_TX2RX_SLPBACK_EN = FALSE
    PMA_CH2_REG_TX_PCLK_EDGE_SEL = FALSE
    PMA_CH2_REG_TX_RXDET_STATUS_OW = FALSE
    PMA_CH2_REG_TX_RXDET_STATUS = TRUE
    PMA_CH2_REG_TX_PRBS_GEN_EN = FALSE
    PMA_CH2_REG_TX_PRBS_GEN_WIDTH_SEL = 16BIT
    PMA_CH2_REG_TX_PRBS_SEL = PRBS7
    PMA_CH2_REG_TX_UDP_DATA_7_TO_0 = 32'b00000000000000000000000000000101
    PMA_CH2_REG_TX_UDP_DATA_15_TO_8 = 32'b00000000000000000000000011101011
    PMA_CH2_REG_TX_UDP_DATA_19_TO_16 = 32'b00000000000000000000000000000011
    PMA_CH2_REG_TX_RESERVED_192 = FALSE
    PMA_CH2_REG_TX_FIFO_WP_CTRL = 32'b00000000000000000000000000000100
    PMA_CH2_REG_TX_FIFO_EN = FALSE
    PMA_CH2_REG_TX_DATA_MUX_SEL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_ERR_INSERT = FALSE
    PMA_CH2_REG_TX_RESERVED_203_200 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_204 = FALSE
    PMA_CH2_REG_TX_SATA_EN = FALSE
    PMA_CH2_REG_TX_RESERVED_207_206 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_RATE_CHANGE_TXPCLK_ON_OW = FALSE
    PMA_CH2_REG_RATE_CHANGE_TXPCLK_ON = TRUE
    PMA_CH2_REG_TX_CFG_POST1 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_CFG_POST2 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_DEEMP = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_DEEMP_OW = FALSE
    PMA_CH2_REG_TX_RESERVED_224_223 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RESERVED_225 = FALSE
    PMA_CH2_REG_TX_RESERVED_229_226 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_OOB_DELAY_SEL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_POLARITY = NORMAL
    PMA_CH2_REG_ANA_TX_JTAG_DATA_O_SEL = FALSE
    PMA_CH2_REG_TX_RESERVED_236 = FALSE
    PMA_CH2_REG_TX_LS_MODE_EN = FALSE
    PMA_CH2_REG_TX_JTAG_MODE_EN_OW = FALSE
    PMA_CH2_REG_TX_JTAG_MODE_EN = FALSE
    PMA_CH2_REG_RX_JTAG_MODE_EN_OW = FALSE
    PMA_CH2_REG_RX_JTAG_MODE_EN = FALSE
    PMA_CH2_REG_RX_JTAG_OE = TRUE
    PMA_CH2_REG_RX_ACJTAG_VHYSTSEL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_RES_CAL_EN = FALSE
    PMA_CH2_REG_RX_TERM_MODE_CTRL = 32'b00000000000000000000000000000110
    PMA_CH2_REG_TX_RESERVED_251_250 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_PLPBK_TXPCLK_EN = FALSE
    PMA_CH2_REG_TX_RESERVED_253 = FALSE
    PMA_CH2_REG_TX_RESERVED_254 = FALSE
    PMA_CH2_REG_TX_RESERVED_255 = FALSE
    PMA_CH2_REG_TX_RESERVED_256 = FALSE
    PMA_CH2_REG_TX_RESERVED_257 = FALSE
    PMA_CH2_REG_TX_PH_SEL = 32'b00000000000000000000000000000001
    PMA_CH2_REG_TX_CFG_PRE = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_CFG_MAIN = 32'b00000000000000000000000000000000
    PMA_CH2_REG_CFG_POST = 32'b00000000000000000000000000000000
    PMA_CH2_REG_PD_MAIN = TRUE
    PMA_CH2_REG_PD_PRE = TRUE
    PMA_CH2_REG_TX_LS_DATA = FALSE
    PMA_CH2_REG_TX_DCC_BUF_SZ_SEL = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_DCC_CAL_CUR_TUNE = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_DCC_CAL_EN = FALSE
    PMA_CH2_REG_TX_DCC_CUR_SS = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_DCC_FA_CTRL = FALSE
    PMA_CH2_REG_TX_DCC_RI_CTRL = FALSE
    PMA_CH2_REG_ATB_SEL_2_TO_0 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_ATB_SEL_9_TO_3 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_CFG_7_TO_0 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_CFG_15_TO_8 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_CFG_23_TO_16 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_CFG_31_TO_24 = 32'b00000000000000000000000010000000
    PMA_CH2_REG_TX_OOB_EI_EN = FALSE
    PMA_CH2_REG_TX_OOB_EI_EN_OW = FALSE
    PMA_CH2_REG_TX_BEACON_EN_DELAYED = FALSE
    PMA_CH2_REG_TX_BEACON_EN_DELAYED_OW = FALSE
    PMA_CH2_REG_TX_JTAG_DATA = FALSE
    PMA_CH2_REG_TX_RXDET_TIMER_SEL = 32'b00000000000000000000000001010111
    PMA_CH2_REG_TX_CFG1_7_0 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_CFG1_15_8 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_CFG1_23_16 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_TX_CFG1_31_24 = 32'b00000000000000000000000000000000
    PMA_CH2_REG_CFG_LANE_POWERUP = ON
    PMA_CH2_REG_CFG_TX_LANE_POWERUP_CLKPATH = TRUE
    PMA_CH2_REG_CFG_TX_LANE_POWERUP_PISO = TRUE
    PMA_CH2_REG_CFG_TX_LANE_POWERUP_DRIVER = TRUE
    CH3_MUX_BIAS = 32'b00000000000000000000000000000010
    CH3_PD_CLK = 32'b00000000000000000000000000000000
    CH3_REG_SYNC = 32'b00000000000000000000000000000000
    CH3_REG_SYNC_OW = 32'b00000000000000000000000000000000
    CH3_PLL_LOCK_OW = 32'b00000000000000000000000000000000
    CH3_PLL_LOCK_OW_EN = 32'b00000000000000000000000000000000
    PCS_CH3_SLAVE = 32'b00000000000000000000000000000000
    PCS_CH3_BYPASS_WORD_ALIGN = TRUE
    PCS_CH3_BYPASS_DENC = TRUE
    PCS_CH3_BYPASS_BONDING = TRUE
    PCS_CH3_BYPASS_CTC = TRUE
    PCS_CH3_BYPASS_GEAR = FALSE
    PCS_CH3_BYPASS_BRIDGE = FALSE
    PCS_CH3_BYPASS_BRIDGE_FIFO = FALSE
    PCS_CH3_DATA_MODE = X16
    PCS_CH3_RX_POLARITY_INV = DELAY
    PCS_CH3_ALIGN_MODE = 1GB
    PCS_CH3_SAMP_16B = X16
    PCS_CH3_FARLP_PWR_REDUCTION = FALSE
    PCS_CH3_COMMA_REG0 = 32'b00000000000000000000000000000000
    PCS_CH3_COMMA_MASK = 32'b00000000000000000000000000000000
    PCS_CH3_CEB_MODE = 10GB
    PCS_CH3_CTC_MODE = 1SKIP
    PCS_CH3_A_REG = 32'b00000000000000000000000001111100
    PCS_CH3_GE_AUTO_EN = FALSE
    PCS_CH3_SKIP_REG0 = 32'b00000000000000000000000000000000
    PCS_CH3_SKIP_REG1 = 32'b00000000000000000000000000000000
    PCS_CH3_SKIP_REG2 = 32'b00000000000000000000000000000000
    PCS_CH3_SKIP_REG3 = 32'b00000000000000000000000000000000
    PCS_CH3_DEC_DUAL = FALSE
    PCS_CH3_SPLIT = FALSE
    PCS_CH3_FIFOFLAG_CTC = FALSE
    PCS_CH3_COMMA_DET_MODE = COMMA_PATTERN
    PCS_CH3_ERRDETECT_SILENCE = TRUE
    PCS_CH3_PMA_RCLK_POLINV = PMA_RCLK
    PCS_CH3_PCS_RCLK_SEL = PMA_RCLK
    PCS_CH3_CB_RCLK_SEL = PMA_RCLK
    PCS_CH3_AFTER_CTC_RCLK_SEL = RCLK2
    PCS_CH3_RCLK_POLINV = RCLK
    PCS_CH3_BRIDGE_RCLK_SEL = PMA_RCLK
    PCS_CH3_PCS_RCLK_EN = FALSE
    PCS_CH3_CB_RCLK_EN = FALSE
    PCS_CH3_AFTER_CTC_RCLK_EN = FALSE
    PCS_CH3_AFTER_CTC_RCLK_EN_GB = TRUE
    PCS_CH3_PCS_RX_RSTN = TRUE
    PCS_CH3_PCIE_SLAVE = MASTER
    PCS_CH3_RX_64B66B_67B = NORMAL
    PCS_CH3_RX_BRIDGE_CLK_POLINV = RX_BRIDGE_CLK
    PCS_CH3_PCS_CB_RSTN = TRUE
    PCS_CH3_TX_BRIDGE_GEAR_SEL = FALSE
    PCS_CH3_TX_BYPASS_BRIDGE_UINT = FALSE
    PCS_CH3_TX_BYPASS_BRIDGE_FIFO = FALSE
    PCS_CH3_TX_BYPASS_GEAR = FALSE
    PCS_CH3_TX_BYPASS_ENC = TRUE
    PCS_CH3_TX_BYPASS_BIT_SLIP = TRUE
    PCS_CH3_TX_GEAR_SPLIT = TRUE
    PCS_CH3_TX_DRIVE_REG_MODE = NO_CHANGE
    PCS_CH3_TX_BIT_SLIP_CYCLES = 32'b00000000000000000000000000000000
    PCS_CH3_INT_TX_MASK_0 = FALSE
    PCS_CH3_INT_TX_MASK_1 = FALSE
    PCS_CH3_INT_TX_MASK_2 = FALSE
    PCS_CH3_INT_TX_CLR_0 = FALSE
    PCS_CH3_INT_TX_CLR_1 = FALSE
    PCS_CH3_INT_TX_CLR_2 = FALSE
    PCS_CH3_TX_PMA_TCLK_POLINV = PMA_TCLK
    PCS_CH3_TX_PCS_CLK_EN_SEL = TRUE
    PCS_CH3_TX_BRIDGE_TCLK_SEL = TCLK
    PCS_CH3_TX_TCLK_POLINV = TCLK
    PCS_CH3_PCS_TCLK_SEL = PMA_TCLK
    PCS_CH3_TX_PCS_TX_RSTN = TRUE
    PCS_CH3_TX_SLAVE = MASTER
    PCS_CH3_TX_GEAR_CLK_EN_SEL = FALSE
    PCS_CH3_DATA_WIDTH_MODE = X16
    PCS_CH3_TX_64B66B_67B = NORMAL
    PCS_CH3_GEAR_TCLK_SEL = PMA_TCLK
    PCS_CH3_TX_TCLK2FABRIC_SEL = TRUE
    PCS_CH3_TX_OUTZZ = FALSE
    PCS_CH3_ENC_DUAL = TRUE
    PCS_CH3_TX_BITSLIP_DATA_MODE = X10
    PCS_CH3_TX_BRIDGE_CLK_POLINV = TX_BRIDGE_CLK
    PCS_CH3_COMMA_REG1 = 32'b00000000000000000000001111111111
    PCS_CH3_RAPID_IMAX = 32'b00000000000000000000000000000101
    PCS_CH3_RAPID_VMIN_1 = 32'b00000000000000000000000011111010
    PCS_CH3_RAPID_VMIN_2 = 32'b00000000000000000000000000000001
    PCS_CH3_RX_PRBS_MODE = DISABLE
    PCS_CH3_RX_ERRCNT_CLR = FALSE
    PCS_CH3_PRBS_ERR_LPBK = FALSE
    PCS_CH3_TX_PRBS_MODE = DISABLE
    PCS_CH3_TX_INSERT_ER = FALSE
    PCS_CH3_ENABLE_PRBS_GEN = FALSE
    PCS_CH3_DEFAULT_RADDR = 32'b00000000000000000000000000000110
    PCS_CH3_MASTER_CHECK_OFFSET = 32'b00000000000000000000000000000100
    PCS_CH3_DELAY_SET = 32'b00000000000000000000000000000000
    PCS_CH3_SEACH_OFFSET = 80BIT
    PCS_CH3_CEB_RAPIDLS_MMAX = 32'b00000000000000000000000000000101
    PCS_CH3_CTC_AFULL = 32'b00000000000000000000000000010100
    PCS_CH3_CTC_AEMPTY = 32'b00000000000000000000000000001100
    PCS_CH3_CTC_CONTI_SKP_SET = 32'b00000000000000000000000000000000
    PCS_CH3_FAR_LOOP = FALSE
    PCS_CH3_NEAR_LOOP = FALSE
    PCS_CH3_PMA_TX2RX_PLOOP_EN = FALSE
    PCS_CH3_PMA_TX2RX_SLOOP_EN = FALSE
    PCS_CH3_PMA_RX2TX_PLOOP_EN = FALSE
    PCS_CH3_INT_RX_MASK_0 = FALSE
    PCS_CH3_INT_RX_MASK_1 = FALSE
    PCS_CH3_INT_RX_MASK_2 = FALSE
    PCS_CH3_INT_RX_MASK_3 = FALSE
    PCS_CH3_INT_RX_MASK_4 = FALSE
    PCS_CH3_INT_RX_MASK_5 = FALSE
    PCS_CH3_INT_RX_MASK_6 = FALSE
    PCS_CH3_INT_RX_MASK_7 = FALSE
    PCS_CH3_INT_RX_CLR_0 = FALSE
    PCS_CH3_INT_RX_CLR_1 = FALSE
    PCS_CH3_INT_RX_CLR_2 = FALSE
    PCS_CH3_INT_RX_CLR_3 = FALSE
    PCS_CH3_INT_RX_CLR_4 = FALSE
    PCS_CH3_INT_RX_CLR_5 = FALSE
    PCS_CH3_INT_RX_CLR_6 = FALSE
    PCS_CH3_INT_RX_CLR_7 = FALSE
    PCS_CH3_CA_RSTN_RX = FALSE
    PCS_CH3_CA_DYN_DLY_EN_RX = FALSE
    PCS_CH3_CA_DYN_DLY_SEL_RX = FALSE
    PCS_CH3_CA_RX = 32'b00000000000000000000000000000000
    PCS_CH3_CA_RSTN_TX = FALSE
    PCS_CH3_CA_DYN_DLY_EN_TX = FALSE
    PCS_CH3_CA_DYN_DLY_SEL_TX = FALSE
    PCS_CH3_CA_TX = 32'b00000000000000000000000000000000
    PCS_CH3_RXPRBS_PWR_REDUCTION = NORMAL
    PCS_CH3_WDALIGN_PWR_REDUCTION = NORMAL
    PCS_CH3_RXDEC_PWR_REDUCTION = NORMAL
    PCS_CH3_RXCB_PWR_REDUCTION = NORMAL
    PCS_CH3_RXCTC_PWR_REDUCTION = NORMAL
    PCS_CH3_RXGEAR_PWR_REDUCTION = NORMAL
    PCS_CH3_RXBRG_PWR_REDUCTION = NORMAL
    PCS_CH3_RXTEST_PWR_REDUCTION = NORMAL
    PCS_CH3_TXBRG_PWR_REDUCTION = NORMAL
    PCS_CH3_TXGEAR_PWR_REDUCTION = NORMAL
    PCS_CH3_TXENC_PWR_REDUCTION = NORMAL
    PCS_CH3_TXBSLP_PWR_REDUCTION = NORMAL
    PCS_CH3_TXPRBS_PWR_REDUCTION = NORMAL
    PMA_CH3_REG_RX_PD = ON
    PMA_CH3_REG_RX_PD_EN = FALSE
    PMA_CH3_REG_RX_RESERVED_2 = FALSE
    PMA_CH3_REG_RX_RESERVED_3 = FALSE
    PMA_CH3_REG_RX_DATAPATH_PD = ON
    PMA_CH3_REG_RX_DATAPATH_PD_EN = TRUE
    PMA_CH3_REG_RX_SIGDET_PD = ON
    PMA_CH3_REG_RX_SIGDET_PD_EN = FALSE
    PMA_CH3_REG_RX_DCC_RST_N = TRUE
    PMA_CH3_REG_RX_DCC_RST_N_EN = FALSE
    PMA_CH3_REG_RX_CDR_RST_N = TRUE
    PMA_CH3_REG_RX_CDR_RST_N_EN = FALSE
    PMA_CH3_REG_RX_SIGDET_RST_N = TRUE
    PMA_CH3_REG_RX_SIGDET_RST_N_EN = FALSE
    PMA_CH3_REG_RXPCLK_SLIP = FALSE
    PMA_CH3_REG_RXPCLK_SLIP_OW = FALSE
    PMA_CH3_REG_RX_PCLKSWITCH_RST_N = TRUE
    PMA_CH3_REG_RX_PCLKSWITCH_RST_N_EN = FALSE
    PMA_CH3_REG_RX_PCLKSWITCH = FALSE
    PMA_CH3_REG_RX_PCLKSWITCH_EN = FALSE
    PMA_CH3_REG_RX_HIGHZ = FALSE
    PMA_CH3_REG_RX_HIGHZ_EN = FALSE
    PMA_CH3_REG_RX_SIGDET_CLK_WINDOW = FALSE
    PMA_CH3_REG_RX_SIGDET_CLK_WINDOW_OW = FALSE
    PMA_CH3_REG_RX_PD_BIAS_RX = FALSE
    PMA_CH3_REG_RX_PD_BIAS_RX_OW = FALSE
    PMA_CH3_REG_RX_RESET_N = FALSE
    PMA_CH3_REG_RX_RESET_N_OW = FALSE
    PMA_CH3_REG_RX_RESERVED_29_28 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_BUSWIDTH = 16BIT
    PMA_CH3_REG_RX_BUSWIDTH_EN = TRUE
    PMA_CH3_REG_RX_RATE = DIV1
    PMA_CH3_REG_RX_RESERVED_36 = FALSE
    PMA_CH3_REG_RX_RATE_EN = FALSE
    PMA_CH3_REG_RX_RES_TRIM = 32'b00000000000000000000000000101110
    PMA_CH3_REG_RX_RESERVED_44 = FALSE
    PMA_CH3_REG_RX_RESERVED_45 = FALSE
    PMA_CH3_REG_RX_SIGDET_STATUS_EN = FALSE
    PMA_CH3_REG_RX_RESERVED_48_47 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_ICTRL_SIGDET = 32'b00000000000000000000000000000101
    PMA_CH3_REG_CDR_READY_THD = 32'b00000000000000000000101010101110
    PMA_CH3_REG_RX_RESERVED_65 = FALSE
    PMA_CH3_REG_RX_PCLK_EDGE_SEL = POS_EDGE
    PMA_CH3_REG_RX_PIBUF_IC = 32'b00000000000000000000000000000001
    PMA_CH3_REG_RX_RESERVED_69 = FALSE
    PMA_CH3_REG_RX_DCC_IC_RX = 32'b00000000000000000000000000000001
    PMA_CH3_REG_CDR_READY_CHECK_CTRL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_ICTRL_TRX = 100PCT
    PMA_CH3_REG_RX_RESERVED_77_76 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_RESERVED_79_78 = 32'b00000000000000000000000000000001
    PMA_CH3_REG_RX_RESERVED_81_80 = 32'b00000000000000000000000000000001
    PMA_CH3_REG_RX_ICTRL_PIBUF = 100PCT
    PMA_CH3_REG_RX_ICTRL_PI = 100PCT
    PMA_CH3_REG_RX_ICTRL_DCC = 100PCT
    PMA_CH3_REG_RX_RESERVED_89_88 = 32'b00000000000000000000000000000001
    PMA_CH3_REG_TX_RATE = DIV1
    PMA_CH3_REG_RX_RESERVED_92 = FALSE
    PMA_CH3_REG_TX_RATE_EN = FALSE
    PMA_CH3_REG_RX_TX2RX_PLPBK_RST_N = TRUE
    PMA_CH3_REG_RX_TX2RX_PLPBK_RST_N_EN = FALSE
    PMA_CH3_REG_RX_TX2RX_PLPBK_EN = FALSE
    PMA_CH3_REG_TXCLK_SEL = PLL
    PMA_CH3_REG_RX_DATA_POLARITY = NORMAL
    PMA_CH3_REG_RX_ERR_INSERT = FALSE
    PMA_CH3_REG_UDP_CHK_EN = FALSE
    PMA_CH3_REG_PRBS_SEL = PRBS7
    PMA_CH3_REG_PRBS_CHK_EN = FALSE
    PMA_CH3_REG_PRBS_CHK_WIDTH_SEL = 16BIT
    PMA_CH3_REG_BIST_CHK_PAT_SEL = PRBS
    PMA_CH3_REG_LOAD_ERR_CNT = FALSE
    PMA_CH3_REG_CHK_COUNTER_EN = FALSE
    PMA_CH3_REG_CDR_PROP_GAIN = 32'b00000000000000000000000000000111
    PMA_CH3_REG_CDR_PROP_TURBO_GAIN = 32'b00000000000000000000000000000101
    PMA_CH3_REG_CDR_INT_GAIN = 32'b00000000000000000000000000000100
    PMA_CH3_REG_CDR_INT_TURBO_GAIN = 32'b00000000000000000000000000000101
    PMA_CH3_REG_CDR_INT_SAT_MAX = 32'b00000000000000000000001100000000
    PMA_CH3_REG_CDR_INT_SAT_MIN = 32'b00000000000000000000000011111111
    PMA_CH3_REG_CDR_INT_RST = FALSE
    PMA_CH3_REG_CDR_INT_RST_OW = FALSE
    PMA_CH3_REG_CDR_PROP_RST = FALSE
    PMA_CH3_REG_CDR_PROP_RST_OW = FALSE
    PMA_CH3_REG_CDR_LOCK_RST = FALSE
    PMA_CH3_REG_CDR_LOCK_RST_OW = FALSE
    PMA_CH3_REG_CDR_RX_PI_FORCE_SEL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_CDR_RX_PI_FORCE_D = 32'b00000000000000000000000000000000
    PMA_CH3_REG_CDR_LOCK_TIMER = 25_6U
    PMA_CH3_REG_CDR_TURBO_MODE_TIMER = 32'b00000000000000000000000000000001
    PMA_CH3_REG_CDR_LOCK_VAL = FALSE
    PMA_CH3_REG_CDR_LOCK_OW = FALSE
    PMA_CH3_REG_CDR_INT_SAT_DET_EN = TRUE
    PMA_CH3_REG_CDR_SAT_AUTO_DIS = TRUE
    PMA_CH3_REG_CDR_GAIN_AUTO = FALSE
    PMA_CH3_REG_CDR_TURBO_GAIN_AUTO = FALSE
    PMA_CH3_REG_RX_RESERVED_171_167 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_RESERVED_175_172 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_CDR_SAT_DET_STATUS_EN = FALSE
    PMA_CH3_REG_CDR_SAT_DET_STATUS_RESET_EN = FALSE
    PMA_CH3_REG_CDR_PI_CTRL_RST = FALSE
    PMA_CH3_REG_CDR_PI_CTRL_RST_OW = FALSE
    PMA_CH3_REG_CDR_SAT_DET_RST = FALSE
    PMA_CH3_REG_CDR_SAT_DET_RST_OW = FALSE
    PMA_CH3_REG_CDR_SAT_DET_STICKY_RST = FALSE
    PMA_CH3_REG_CDR_SAT_DET_STICKY_RST_OW = FALSE
    PMA_CH3_REG_CDR_SIGDET_STATUS_DIS = FALSE
    PMA_CH3_REG_CDR_SAT_DET_TIMER = 32'b00000000000000000000000000000010
    PMA_CH3_REG_CDR_SAT_DET_STATUS_VAL = FALSE
    PMA_CH3_REG_CDR_SAT_DET_STATUS_OW = FALSE
    PMA_CH3_REG_CDR_TURBO_MODE_EN = TRUE
    PMA_CH3_REG_RX_RESERVED_190 = FALSE
    PMA_CH3_REG_RX_RESERVED_193_191 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_CDR_STATUS_FIFO_EN = TRUE
    PMA_CH3_REG_PMA_TEST_SEL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_OOB_COMWAKE_GAP_MIN = 32'b00000000000000000000000000000011
    PMA_CH3_REG_OOB_COMWAKE_GAP_MAX = 32'b00000000000000000000000000001011
    PMA_CH3_REG_OOB_COMINIT_GAP_MIN = 32'b00000000000000000000000000001111
    PMA_CH3_REG_OOB_COMINIT_GAP_MAX = 32'b00000000000000000000000000100011
    PMA_CH3_REG_RX_RESERVED_227_226 = 32'b00000000000000000000000000000001
    PMA_CH3_REG_COMWAKE_STATUS_CLEAR = 32'b00000000000000000000000000000000
    PMA_CH3_REG_COMINIT_STATUS_CLEAR = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_SYNC_RST_N_EN = FALSE
    PMA_CH3_REG_RX_SYNC_RST_N = TRUE
    PMA_CH3_REG_RX_RESERVED_233_232 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_RESERVED_235_234 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_SATA_COMINIT_OW = FALSE
    PMA_CH3_REG_RX_SATA_COMINIT = FALSE
    PMA_CH3_REG_RX_SATA_COMWAKE_OW = FALSE
    PMA_CH3_REG_RX_SATA_COMWAKE = FALSE
    PMA_CH3_REG_RX_RESERVED_241_240 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_DCC_DISABLE = FALSE
    PMA_CH3_REG_RX_RESERVED_243 = FALSE
    PMA_CH3_REG_RX_SLIP_SEL_EN = FALSE
    PMA_CH3_REG_RX_SLIP_SEL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_SLIP_EN = FALSE
    PMA_CH3_REG_RX_SIGDET_STATUS_SEL = 32'b00000000000000000000000000000101
    PMA_CH3_REG_RX_SIGDET_FSM_RST_N = TRUE
    PMA_CH3_REG_RX_RESERVED_254 = FALSE
    PMA_CH3_REG_RX_SIGDET_STATUS = FALSE
    PMA_CH3_REG_RX_SIGDET_VTH = 72MV
    PMA_CH3_REG_RX_SIGDET_GRM = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_SIGDET_PULSE_EXT = FALSE
    PMA_CH3_REG_RX_SIGDET_CH2_SEL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_SIGDET_CH2_CHK_WINDOW = 32'b00000000000000000000000000000011
    PMA_CH3_REG_RX_SIGDET_CHK_WINDOW_EN = TRUE
    PMA_CH3_REG_RX_SIGDET_NOSIG_COUNT_SETTING = 32'b00000000000000000000000000000100
    PMA_CH3_REG_SLIP_FIFO_INV_EN = FALSE
    PMA_CH3_REG_SLIP_FIFO_INV = POS_EDGE
    PMA_CH3_REG_RX_SIGDET_OOB_DET_COUNT_VAL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_SIGDET_4OOB_DET_SEL = 32'b00000000000000000000000000000111
    PMA_CH3_REG_RX_RESERVED_285_283 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_RESERVED_286 = FALSE
    PMA_CH3_REG_RX_SIGDET_IC_I = 32'b00000000000000000000000000001010
    PMA_CH3_REG_RX_OOB_DETECTOR_RESET_N_OW = FALSE
    PMA_CH3_REG_RX_OOB_DETECTOR_RESET_N = FALSE
    PMA_CH3_REG_RX_OOB_DETECTOR_PD_OW = FALSE
    PMA_CH3_REG_RX_OOB_DETECTOR_PD = ON
    PMA_CH3_REG_RX_LS_MODE_EN = FALSE
    PMA_CH3_REG_ANA_RX_EQ1_R_SET_FB_O_SEL = TRUE
    PMA_CH3_REG_ANA_RX_EQ2_R_SET_FB_O_SEL = TRUE
    PMA_CH3_REG_RX_EQ1_R_SET_TOP = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_EQ1_R_SET_FB = 32'b00000000000000000000000000001111
    PMA_CH3_REG_RX_EQ1_C_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_EQ1_OFF = FALSE
    PMA_CH3_REG_RX_EQ2_R_SET_TOP = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_EQ2_R_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_EQ2_C_SET_FB = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_EQ2_OFF = FALSE
    PMA_CH3_REG_EQ_DAC = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_ICTRL_EQ = 32'b00000000000000000000000000000010
    PMA_CH3_REG_EQ_DC_CALIB_EN = TRUE
    PMA_CH3_REG_EQ_DC_CALIB_SEL = FALSE
    PMA_CH3_REG_RX_RESERVED_337_330 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_RESERVED_345_338 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_RESERVED_353_346 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RX_RESERVED_361_354 = 32'b00000000000000000000000000000000
    PMA_CH3_CTLE_CTRL_REG_I = 32'b00000000000000000000000000000000
    PMA_CH3_CTLE_REG_FORCE_SEL_I = FALSE
    PMA_CH3_CTLE_REG_HOLD_I = FALSE
    PMA_CH3_CTLE_REG_INIT_DAC_I = 32'b00000000000000000000000000000000
    PMA_CH3_CTLE_REG_POLARITY_I = FALSE
    PMA_CH3_CTLE_REG_SHIFTER_GAIN_I = 32'b00000000000000000000000000000001
    PMA_CH3_CTLE_REG_THRESHOLD_I = 32'b00000000000000000000110000000000
    PMA_CH3_REG_RX_RES_TRIM_EN = TRUE
    PMA_CH3_REG_RX_RESERVED_393_389 = 32'b00000000000000000000000000000000
    PMA_CH3_CFG_RX_LANE_POWERUP = ON
    PMA_CH3_CFG_RX_PMA_RSTN = TRUE
    PMA_CH3_INT_PMA_RX_MASK_0 = FALSE
    PMA_CH3_INT_PMA_RX_CLR_0 = FALSE
    PMA_CH3_CFG_CTLE_ADP_RSTN = TRUE
    PMA_CH3_REG_TX_PD = ON
    PMA_CH3_REG_TX_PD_OW = FALSE
    PMA_CH3_REG_TX_MAIN_PRE_Z = FALSE
    PMA_CH3_REG_TX_MAIN_PRE_Z_OW = FALSE
    PMA_CH3_REG_TX_BEACON_TIMER_SEL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RXDET_REQ_OW = FALSE
    PMA_CH3_REG_TX_RXDET_REQ = FALSE
    PMA_CH3_REG_TX_BEACON_EN_OW = FALSE
    PMA_CH3_REG_TX_BEACON_EN = FALSE
    PMA_CH3_REG_TX_EI_EN_OW = FALSE
    PMA_CH3_REG_TX_EI_EN = FALSE
    PMA_CH3_REG_TX_BIT_CONV = FALSE
    PMA_CH3_REG_TX_RES_CAL = 32'b00000000000000000000000000110000
    PMA_CH3_REG_TX_RESERVED_19 = FALSE
    PMA_CH3_REG_TX_RESERVED_25_20 = 32'b00000000000000000000000000100000
    PMA_CH3_REG_TX_RESERVED_33_26 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_41_34 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_49_42 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_57_50 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_SYNC_OW = FALSE
    PMA_CH3_REG_TX_SYNC = FALSE
    PMA_CH3_REG_TX_PD_POST = OFF
    PMA_CH3_REG_TX_PD_POST_OW = TRUE
    PMA_CH3_REG_TX_RESET_N_OW = FALSE
    PMA_CH3_REG_TX_RESET_N = TRUE
    PMA_CH3_REG_TX_RESERVED_64 = FALSE
    PMA_CH3_REG_TX_RESERVED_65 = TRUE
    PMA_CH3_REG_TX_BUSWIDTH_OW = TRUE
    PMA_CH3_REG_TX_BUSWIDTH = 16BIT
    PMA_CH3_REG_PLL_READY_OW = FALSE
    PMA_CH3_REG_PLL_READY = TRUE
    PMA_CH3_REG_TX_RESERVED_72 = FALSE
    PMA_CH3_REG_TX_RESERVED_73 = FALSE
    PMA_CH3_REG_TX_RESERVED_74 = FALSE
    PMA_CH3_REG_EI_PCLK_DELAY_SEL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_77 = FALSE
    PMA_CH3_REG_TX_RESERVED_83_78 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_89_84 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_95_90 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_101_96 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_107_102 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_113_108 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_AMP_DAC0 = 32'b00000000000000000000000000011001
    PMA_CH3_REG_TX_AMP_DAC1 = 32'b00000000000000000000000000010011
    PMA_CH3_REG_TX_AMP_DAC2 = 32'b00000000000000000000000000001110
    PMA_CH3_REG_TX_AMP_DAC3 = 32'b00000000000000000000000000001001
    PMA_CH3_REG_TX_RESERVED_143_138 = 32'b00000000000000000000000000000101
    PMA_CH3_REG_TX_MARGIN = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_MARGIN_OW = FALSE
    PMA_CH3_REG_TX_RESERVED_149_148 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_150 = FALSE
    PMA_CH3_REG_TX_SWING = FALSE
    PMA_CH3_REG_TX_SWING_OW = FALSE
    PMA_CH3_REG_TX_RESERVED_153 = FALSE
    PMA_CH3_REG_TX_RXDET_THRESHOLD = 84MV
    PMA_CH3_REG_TX_RESERVED_157_156 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_BEACON_OSC_CTRL = FALSE
    PMA_CH3_REG_TX_RESERVED_160_159 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_162_161 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_TX2RX_SLPBACK_EN = FALSE
    PMA_CH3_REG_TX_PCLK_EDGE_SEL = FALSE
    PMA_CH3_REG_TX_RXDET_STATUS_OW = FALSE
    PMA_CH3_REG_TX_RXDET_STATUS = TRUE
    PMA_CH3_REG_TX_PRBS_GEN_EN = FALSE
    PMA_CH3_REG_TX_PRBS_GEN_WIDTH_SEL = 16BIT
    PMA_CH3_REG_TX_PRBS_SEL = PRBS7
    PMA_CH3_REG_TX_UDP_DATA_7_TO_0 = 32'b00000000000000000000000000000101
    PMA_CH3_REG_TX_UDP_DATA_15_TO_8 = 32'b00000000000000000000000011101011
    PMA_CH3_REG_TX_UDP_DATA_19_TO_16 = 32'b00000000000000000000000000000011
    PMA_CH3_REG_TX_RESERVED_192 = FALSE
    PMA_CH3_REG_TX_FIFO_WP_CTRL = 32'b00000000000000000000000000000100
    PMA_CH3_REG_TX_FIFO_EN = FALSE
    PMA_CH3_REG_TX_DATA_MUX_SEL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_ERR_INSERT = FALSE
    PMA_CH3_REG_TX_RESERVED_203_200 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_204 = FALSE
    PMA_CH3_REG_TX_SATA_EN = FALSE
    PMA_CH3_REG_TX_RESERVED_207_206 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_RATE_CHANGE_TXPCLK_ON_OW = FALSE
    PMA_CH3_REG_RATE_CHANGE_TXPCLK_ON = TRUE
    PMA_CH3_REG_TX_CFG_POST1 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_CFG_POST2 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_DEEMP = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_DEEMP_OW = FALSE
    PMA_CH3_REG_TX_RESERVED_224_223 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RESERVED_225 = FALSE
    PMA_CH3_REG_TX_RESERVED_229_226 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_OOB_DELAY_SEL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_POLARITY = NORMAL
    PMA_CH3_REG_ANA_TX_JTAG_DATA_O_SEL = FALSE
    PMA_CH3_REG_TX_RESERVED_236 = FALSE
    PMA_CH3_REG_TX_LS_MODE_EN = FALSE
    PMA_CH3_REG_TX_JTAG_MODE_EN_OW = FALSE
    PMA_CH3_REG_TX_JTAG_MODE_EN = FALSE
    PMA_CH3_REG_RX_JTAG_MODE_EN_OW = FALSE
    PMA_CH3_REG_RX_JTAG_MODE_EN = FALSE
    PMA_CH3_REG_RX_JTAG_OE = TRUE
    PMA_CH3_REG_RX_ACJTAG_VHYSTSEL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_RES_CAL_EN = FALSE
    PMA_CH3_REG_RX_TERM_MODE_CTRL = 32'b00000000000000000000000000000110
    PMA_CH3_REG_TX_RESERVED_251_250 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_PLPBK_TXPCLK_EN = FALSE
    PMA_CH3_REG_TX_RESERVED_253 = FALSE
    PMA_CH3_REG_TX_RESERVED_254 = FALSE
    PMA_CH3_REG_TX_RESERVED_255 = FALSE
    PMA_CH3_REG_TX_RESERVED_256 = FALSE
    PMA_CH3_REG_TX_RESERVED_257 = FALSE
    PMA_CH3_REG_TX_PH_SEL = 32'b00000000000000000000000000000001
    PMA_CH3_REG_TX_CFG_PRE = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_CFG_MAIN = 32'b00000000000000000000000000000000
    PMA_CH3_REG_CFG_POST = 32'b00000000000000000000000000000000
    PMA_CH3_REG_PD_MAIN = TRUE
    PMA_CH3_REG_PD_PRE = TRUE
    PMA_CH3_REG_TX_LS_DATA = FALSE
    PMA_CH3_REG_TX_DCC_BUF_SZ_SEL = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_DCC_CAL_CUR_TUNE = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_DCC_CAL_EN = FALSE
    PMA_CH3_REG_TX_DCC_CUR_SS = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_DCC_FA_CTRL = FALSE
    PMA_CH3_REG_TX_DCC_RI_CTRL = FALSE
    PMA_CH3_REG_ATB_SEL_2_TO_0 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_ATB_SEL_9_TO_3 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_CFG_7_TO_0 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_CFG_15_TO_8 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_CFG_23_TO_16 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_CFG_31_TO_24 = 32'b00000000000000000000000010000000
    PMA_CH3_REG_TX_OOB_EI_EN = FALSE
    PMA_CH3_REG_TX_OOB_EI_EN_OW = FALSE
    PMA_CH3_REG_TX_BEACON_EN_DELAYED = FALSE
    PMA_CH3_REG_TX_BEACON_EN_DELAYED_OW = FALSE
    PMA_CH3_REG_TX_JTAG_DATA = FALSE
    PMA_CH3_REG_TX_RXDET_TIMER_SEL = 32'b00000000000000000000000001010111
    PMA_CH3_REG_TX_CFG1_7_0 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_CFG1_15_8 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_CFG1_23_16 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_TX_CFG1_31_24 = 32'b00000000000000000000000000000000
    PMA_CH3_REG_CFG_LANE_POWERUP = ON
    PMA_CH3_REG_CFG_TX_LANE_POWERUP_CLKPATH = TRUE
    PMA_CH3_REG_CFG_TX_LANE_POWERUP_PISO = TRUE
    PMA_CH3_REG_CFG_TX_LANE_POWERUP_DRIVER = TRUE
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v(line number: 2676)] Elaborating instance U_APB_BRIDGE
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_apb_bridge_v1_2.v(line number: 17)] Elaborating module ipm2l_hsstlp_apb_bridge_v1_2
I: Module instance {pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/U_APB_BRIDGE} parameter value:
    PLL0_EN = TRUE
    PLL1_EN = FALSE
    CHANNEL0_EN = TRUE
    CHANNEL1_EN = TRUE
    CHANNEL2_EN = FALSE
    CHANNEL3_EN = FALSE
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v(line number: 2830)] Elaborating instance U_GTP_HSSTLP_PLL0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v(line number: 3501)] Elaborating instance U_GTP_HSSTLP_LANE0
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v(line number: 4108)] Elaborating instance U_GTP_HSSTLP_LANE1
W: Verilog-2021: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v(line number: 2386)] Net LANE_CIN_BUS_FORWARD_0 in ipm2l_hsstlp_wrapper_v1_6(original module ipm2l_hsstlp_wrapper_v1_6) does not have a driver, tie it to 0
W: Verilog-2021: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v(line number: 2433)] Net APATTERN_STATUS_CIN_1 in ipm2l_hsstlp_wrapper_v1_6(original module ipm2l_hsstlp_wrapper_v1_6) does not have a driver, tie it to 0
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v(line number: 2321)] Give initial value 0 for the no drive pin REFCLK_CML_N_1 in module instance pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP.U_GTP_HSSTLP_WRAPPER
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v(line number: 2321)] Give initial value 0 for the no drive pin REFCLK_CML_P_1 in module instance pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP.U_GTP_HSSTLP_WRAPPER
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v(line number: 2321)] Give initial value 0 for the no drive pin P_RX_SDN_2 in module instance pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP.U_GTP_HSSTLP_WRAPPER
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v(line number: 2321)] Give initial value 0 for the no drive pin P_RX_SDP_2 in module instance pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP.U_GTP_HSSTLP_WRAPPER
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v(line number: 2321)] Give initial value 0 for the no drive pin P_RX_SDN_3 in module instance pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP.U_GTP_HSSTLP_WRAPPER
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v(line number: 2321)] Give initial value 0 for the no drive pin P_RX_SDP_3 in module instance pcie_dma_test/u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP.U_GTP_HSSTLP_WRAPPER
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 146)] Net P_PCS_LSM_SYNCED[2] in ips2l_pcie_soft_phy_v1_3(original module ips2l_pcie_soft_phy_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 146)] Net P_PCS_LSM_SYNCED[3] in ips2l_pcie_soft_phy_v1_3(original module ips2l_pcie_soft_phy_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 170)] Net rx_valid_i[2] in ips2l_pcie_soft_phy_v1_3(original module ips2l_pcie_soft_phy_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 170)] Net rx_valid_i[3] in ips2l_pcie_soft_phy_v1_3(original module ips2l_pcie_soft_phy_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 276)] Net TCLK2FABRIC[2] in ips2l_pcie_soft_phy_v1_3(original module ips2l_pcie_soft_phy_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/ips2l_pcie_soft_phy_v1_3.v(line number: 276)] Net TCLK2FABRIC[3] in ips2l_pcie_soft_phy_v1_3(original module ips2l_pcie_soft_phy_v1_3) does not have a driver, tie it to 0
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1769)] Width mismatch between port pcs_nearend_loop and signal bound to it for instantiated module pcie_test
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1769)] Width mismatch between port pma_nearend_ploop and signal bound to it for instantiated module pcie_test
W: Verilog-2019: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1769)] Width mismatch between port pma_nearend_sloop and signal bound to it for instantiated module pcie_test
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net ddr_ip_clk connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net M_AXI_AWREADY connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net M_AXI_WLAST connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net M_AXI_WUSER connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net M_AXI_WREADY connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net M_AXI_ARREADY connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net M_AXI_RID connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net M_AXI_RDATA connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net M_AXI_RLAST connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net M_AXI_RVALID connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net vs_in connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net vs_out connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net pix_clk_in connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net zoom_de_out connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net video0_rd_en connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net video1_rd_en connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net video2_rd_en connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 402)] Net video3_rd_en connected to input port of module instance pcie_dma_test.user_axi_m_arbitration has no driver, tie it to 0
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1124)] Give initial value 0 for the no drive pin myReg2 in module instance pcie_dma_test.i2cSlave_u
W: Verilog-2036: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 1331)] Net rxd connected to input port of module instance pcie_dma_test.u_uart2apb_top has no driver, tie it to 0
W: Verilog-2024: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 9)] Give an initial value for the no drive output pin eth_rst_n_0 in graph of sdm module pcie_dma_test
W: Verilog-2024: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 9)] Give an initial value for the no drive output pin eth_rgmii_txc_0 in graph of sdm module pcie_dma_test
W: Verilog-2024: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 9)] Give an initial value for the no drive output pin eth_rgmii_tx_ctl_0 in graph of sdm module pcie_dma_test
W: Verilog-2024: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 9)] Give an initial value for the no drive output pin eth_rgmii_txd_0 in graph of sdm module pcie_dma_test
W: Verilog-2021: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 119)] Net video_pre_rd_flag in pcie_dma_test(original module pcie_dma_test) does not have a driver, tie it to 0
W: Verilog-2021: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 405)] Net ddr_ip_rst_n in pcie_dma_test(original module pcie_dma_test) does not have a driver, tie it to 0
W: Verilog-2021: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 440)] Net zoom_data_out in pcie_dma_test(original module pcie_dma_test) does not have a driver, tie it to 0
W: Verilog-2021: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 473)] Net y_act in pcie_dma_test(original module pcie_dma_test) does not have a driver, tie it to 0
W: Verilog-2021: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 474)] Net x_act in pcie_dma_test(original module pcie_dma_test) does not have a driver, tie it to 0
Executing : rtl-elaborate successfully. Time elapsed: 1.141s wall, 0.922s user + 0.203s system = 1.125s CPU (98.6%)

Start rtl-prep.
Executing : rtl-prep successfully. Time elapsed: 0.643s wall, 0.641s user + 0.000s system = 0.641s CPU (99.6%)

Start rtl-infer.
Start DFF-inference.
W: Sdm-2014: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_test.v(line number: 823)] Feedback mux created for signal 'counter_24bit_end'. It is possible a async set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. 
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 51)] Removed register node coms2_reg_config/clock_20k_cnt[15] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 51)] Removed register node coms2_reg_config/clock_20k_cnt[14] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 51)] Removed register node coms2_reg_config/clock_20k_cnt[13] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 51)] Removed register node coms2_reg_config/clock_20k_cnt[12] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 51)] Removed register node coms2_reg_config/clock_20k_cnt[11] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 51)] Removed register node coms1_reg_config/clock_20k_cnt[15] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 51)] Removed register node coms1_reg_config/clock_20k_cnt[14] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 51)] Removed register node coms1_reg_config/clock_20k_cnt[13] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 51)] Removed register node coms1_reg_config/clock_20k_cnt[12] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/OV5640/reg_config.v(line number: 51)] Removed register node coms1_reg_config/clock_20k_cnt[11] that is stuck at constant 0.
I: Removed inst ddrphy_update_req that is redundant to update_start.
W: Sdm-2014: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/pgr_apb_mif_32bit.v(line number: 119)] Feedback mux created for signal 'clk_cnt_start1'. It is possible a async set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. 
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp(line number: 372)] Removed register node u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/cnt[6] that is stuck at constant 0.
I: Removed inst wrlvl_cs_n that is redundant to wrlvl_cas_n.
I: Removed inst wrlvl_we_n that is redundant to wrlvl_cas_n.
I: Removed inst genblk2.init_ras_n that is redundant to genblk2.init_cas_n.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 354)] Removed register node u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[3] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 354)] Removed register node u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[2] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 354)] Removed register node u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[3] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 354)] Removed register node u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[2] that is stuck at constant 0.
I: Removed inst dqs_gate_comp_en_r that is redundant to dqs_gate_comp_done.
Executing : DFF-inference successfully.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_controller.v(line number: 442)] Removed register node u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/o_user_define_data_flag that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp(line number: 217)] Removed register node u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/rst_clk_adj_dir that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp(line number: 147)] Removed register node u_ddr3/u_ddrphy_top/ddrphy_gate_update_ctrl/update_start that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_cpld_tx_ctrl.v(line number: 330)] Removed register node u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/o_axis_slave0_tuser that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mrd_tx_ctrl.v(line number: 276)] Removed register node u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tuser that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ips2l_pcie_dma_mwr_tx_ctrl.v(line number: 255)] Removed register node u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/o_axis_slave2_tuser that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp(line number: 427)] Removed register node u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[2] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp(line number: 427)] Removed register node u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[1] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp(line number: 427)] Removed register node u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[0] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 732)] Removed register node u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[2] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 732)] Removed register node u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[1] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 732)] Removed register node u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/wr_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_read_ddr_fifo/U_ipml_fifo_read_ddr_fifo/U_ipml_sdpram/rd_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 558)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/wr_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit0_ff that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit1_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl3/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl2/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl1/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/write_ddr_fifo/rtl/ipml_sdpram_v1_6_write_ddr_fifo.v(line number: 753)] Removed register node user_axi_m_arbitration/user_rw_fifo_ctrl0/user_write_ddr_fifo/U_ipml_fifo_write_ddr_fifo/U_ipml_sdpram/rd_cs_bit2_bus_ff[0] that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v(line number: 62)] Removed register node u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v(line number: 62)] Removed register node u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v(line number: 62)] Removed register node u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN that is stuck at constant 0.
W: Sdm-2000: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/ipcore/pcie_test/rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v(line number: 62)] Removed register node u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN that is stuck at constant 0.
I: Removed inst ddr_fifo_rd_en_pcie that is redundant to bar0_wr_en.
I: Removed inst mrs2dfi_ras_n that is redundant to mrs2dfi_cs_n.
I: Removed inst lp_ras_n[1:0] that is redundant to lp_cs_n[1:0].
I: Removed inst o_axis_slave1_tvld that is redundant to o_axis_slave1_tlast.
I: Sdm-0001: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/ipm_distributed_sdpram_v1_2.v(line number: 77)] Found Ram mem, depth=64, width=10.
I: Sdm-0001: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 180)] Found Ram mem, depth=16, width=2.
I: Sdm-0001: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/uart2apb_32bit/fifo/pgm_distributed_sdpram_v1_1.v(line number: 82)] Found Ram mem, depth=16, width=8.
I: Sdm-0001: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/ipm_distributed_sdpram_v1_2_distributed_fifo.v(line number: 82)] Found Ram mem, depth=64, width=104.
I: Removed inst P_PMA_TX_PD that is redundant to P_PMA_LANE_PD.
I: Sdm-0001: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 180)] Found Ram mem, depth=16, width=43.
I: Sdm-0001: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/DDR3/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 180)] Found Ram mem, depth=32, width=5.
I: Sdm-0001: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/hdl/pcie_dma_ctrl/fifo/ipm_distributed_sdpram_v1_2_distributed_fifo.v(line number: 82)] Found Ram mem, depth=128, width=128.
Executing : rtl-infer successfully. Time elapsed: 5.816s wall, 4.078s user + 1.703s system = 5.781s CPU (99.4%)

Start rtl-control-opt.
Executing : rtl-control-opt successfully. Time elapsed: 0.108s wall, 0.109s user + 0.000s system = 0.109s CPU (100.8%)

Start rtl-data-opt.
Executing : rtl-data-opt successfully. Time elapsed: 0.675s wall, 0.672s user + 0.000s system = 0.672s CPU (99.5%)

Start FSM inference.
I: FSM blk_state_fsm[1:0] inferred.
I: FSM curr_wr_reg_fsm[1:0] inferred.
I: FSM curr_rd_reg_fsm[1:0] inferred.
I: FSM config_step_fsm[1:0] inferred.
I: FSM arbitration_wr_state_fsm[4:0] inferred.
I: FSM arbitration_rd_state_fsm[2:0] inferred.
I: FSM r_fifo_state_fsm[1:0] inferred.
I: FSM w_fifo_state_fsm[1:0] inferred.
I: FSM r_fifo_state_fsm[1:0] inferred.
I: FSM w_fifo_state_fsm[1:0] inferred.
I: FSM r_fifo_state_fsm[1:0] inferred.
I: FSM w_fifo_state_fsm[1:0] inferred.
I: FSM r_fifo_state_fsm[1:0] inferred.
I: FSM w_fifo_state_fsm[1:0] inferred.
I: FSM CurrState_SISt_fsm[3:0] inferred.
I: FSM streamSt_fsm[1:0] inferred.
I: FSM dcp2dfi_odt_fsm[3:2] inferred.
I: FSM dcp2dfi_odt_fsm[1:0] inferred.
I: FSM mode_state_fsm[1:0] inferred.
I: FSM cstate_fsm[5:0] inferred.
I: FSM state_fsm[9:0] inferred.
I: FSM state_fsm[6:0] inferred.
I: FSM cpd_state_fsm[2:0] inferred.
I: FSM cpd_state_fsm[3:0] inferred.
I: FSM state_fsm[3:0] inferred.
I: FSM state_fsm[1:0] inferred.
I: FSM crt_st_fsm[8:0] inferred.
I: FSM state_fsm[1:0] inferred.
I: FSM state_fsm[1:0] inferred.
I: FSM state_fsm[1:0] inferred.
I: FSM state_fsm[1:0] inferred.
I: FSM state_fsm[2:0] inferred.
I: FSM init_state_fsm[3:0] inferred.
I: FSM wrlvl_state_fsm[3:0] inferred.
W: Loop was found during constant probe.
I: FSM genblk1.rdcal_state_fsm[4:0] inferred.
I: FSM upcal_state_fsm[3:0] inferred.
I: FSM wrcal_state_fsm[3:0] inferred.
I: FSM eyecal_state_fsm[3:0] inferred.
I: FSM error_status_fsm[3:0] inferred.
I: FSM main_state_fsm[3:0] inferred.
I: FSM seio_state_fsm[1:0] inferred.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
I: FSM wl_state_fsm[2:0] inferred.
I: FSM state_fsm[3:0] inferred.
I: FSM state_fsm[3:0] inferred.
I: FSM gdet_state_fsm[2:0] inferred.
I: FSM rdchk_state0_fsm[3:0] inferred.
I: FSM rdchk_state1_fsm[3:0] inferred.
I: FSM gate_state_fsm[2:0] inferred.
I: FSM hsst_fsm_fsm[3:0] inferred.
I: FSM rx_main_fsm_fsm[3:0] inferred.
I: FSM main_done_fsm[3:0] inferred.
I: FSM rx_init_fsm_fsm[3:0] inferred.
Executing : FSM inference successfully. Time elapsed: 0.679s wall, 0.609s user + 0.078s system = 0.688s CPU (101.2%)

Start sdm2adm.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
I: Constant propagation done on N6 (bmsWIDEMUX).
I: Constant propagation done on N84_10 (bmsREDXOR).
I: Constant propagation done on N74 (bmsREDXOR).
I: Constant propagation done on N29 (bmsREDXOR).
I: Constant propagation done on N34 (bmsREDXOR).
I: Constant propagation done on N39 (bmsREDXOR).
I: Constant propagation done on N44 (bmsREDXOR).
I: Constant propagation done on N49 (bmsREDXOR).
I: Constant propagation done on N54 (bmsREDXOR).
I: Constant propagation done on N59 (bmsREDXOR).
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
E: Sdm-4011: [E:/PDS_Verilog/FPGA-Video-Capture-main/FPGA-Video-Capture-main/board_3_oneboard_design/ipcore/read_ddr_fifo/rtl/ipml_sdpram_v1_6_read_ddr_fifo.v(line number: 852)] Module GTP_DRM9K is not support.
Program Error Out.
Action compile: Real time elapsed is 0h:0m:33s
Action compile: CPU time elapsed is 0h:0m:10s
Action compile: Process CPU time elapsed is 0h:0m:10s
Current time: Fri Nov  7 01:16:07 2025
Action compile: Peak memory pool usage is 275 MB
