(_flow fab_demo "2022.2-SP6.4"
    (_comment "Generated by Fabric Compiler on Tue Dec 01 16:03:40 2019")
    (_version "1.0.5")
    (_status "initial")
    (_project
        (_option prj_work_dir (_string ""))
        (_option prj_impl_dir (_string ""))
    )
    (_task tsk_setup
        (_widget wgt_select_arch
            (_input
                (_part
                    (_family Logos2)
                    (_device PG2L50H)
                    (_speedgrade -6)
                    (_package FBG484)
                )
            )
        )
        (_widget wgt_my_design_src
            (_input
                (_file "../example_design/rtl/prbs15_64bit_v1_0.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/prbs31_128bit_v1_0.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/axi_bist_top_v1_0.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/test_main_ctrl_v1_0.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/test_rd_ctrl_v1_0.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/test_wr_ctrl_v1_0.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/uart_rd_lock.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/test_ddr.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/uart_ctrl_32bit/ips2l_clk_gen_32bit.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/uart_ctrl_32bit/ips2l_cmd_parser_32bit.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/uart_ctrl_32bit/ips2l_seu_rs232_intf.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_rx.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_tx.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_32bit.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_top_32bit.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/uart_ctrl_32bit/ips2l_ver_ctrl_32bit.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/adc/adc.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../example_design/rtl/adc/adc_ctrl.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ips2l_rst_sync_v1_3.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/pll/ips2l_ddrphy_gpll_v1_3.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/pll/ips2l_ddrphy_ppll_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../ddr3.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../ddr3_ddrphy_top.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
                (_file "../rtl/ddrphy/ddr3_slice_top_v1_10.v"
                    (_format verilog)
                    (_timespec "2019-12-01T15:23:47")
                )
            )
        )
        (_widget wgt_my_ips_src
        )
        (_widget wgt_import_logic_con_file
            (_input
                (_file "ddr_test.fdc"
                    (_format fdc)
                    (_timespec "2018-12-01T15:23:47")
                )
            )
        )
        (_widget wgt_edit_user_cons
            (_attribute _click_to_run (_switch ON))
        )
        (_widget wgt_simulation
        )
    )
     (_task tsk_compile
         (_command cmd_compile
             (_gci_state (_integer 0))
         )
         (_widget wgt_rtl_view
             (_attribute _click_to_run (_switch ON))
         )
     )
    (_task tsk_synthesis
        (_command cmd_synthesize
        (_gci_state (_integer 4))
            (_option ads (_switch ON))
            (_option selected_syn_tool_opt (_integer 2))
        )
       (_widget wgt_tech_view
           (_attribute _click_to_run (_switch ON))
       )
       (_widget wgt_map_constraint
       )
       (_widget wgt_my_fic_src
       )
       (_widget wgt_inserter_gui_view
           (_attribute _click_to_run (_switch ON))
       )
    )
    (_task tsk_devmap
        (_command cmd_devmap
        (_gci_state (_integer 4))
        )
        (_widget wgt_edit_placement_cons
            (_attribute _click_to_run (_switch ON))
        )
        (_widget wgt_edit_route_cons
            (_attribute _click_to_run (_switch ON))
            (_input
                (_file "ddr3.rcf"
                    (_format rcf)
                    (_timespec "2020-09-30T08:31:21")
                )
            )
        )
    )
    (_task tsk_pnr
        (_command cmd_pnr
        (_gci_state (_integer 4))
            (_option optimize_multi_corner_timing (_switch ON))
            (_option fix_hold_violation (_switch ON))
        )
        (_command cmd_report_post_pnr_timing
        (_gci_state (_integer 4))
            (_attribute _auto_exe_lock (_switch OFF))
            (_option configuration (_switch ON))
        )
        (_widget wgt_arch_browser
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_gen_bitstream
        (_command cmd_gen_bitstream
        (_gci_state (_integer 4))
        )
    )
)
