<?xml version="1.0" encoding="UTF-8"?>
<ip_inst>
    <header>
        <vendor>Pango</vendor>
        <id>042003</id>
        <display_name>DDR3 Interface</display_name>
        <name>Logos2 HMIC_S</name>
        <version>1.10</version>
        <instance>ddr3</instance>
        <family>Logos2</family>
        <device>PG2L50H</device>
        <package>FBG484</package>
        <speedgrade>-6</speedgrade>
        <generator version="2022.2-SP6.4" build="146967">IP Compiler</generator>
    </header>
    <param_list>
        <param>
            <name>GROUP_DQG_4</name>
            <value>G0</value>
        </param>
        <param>
            <name>PHY_TRP</name>
            <value>2</value>
        </param>
        <param>
            <name>PAD_DQ65</name>
            <value>N26</value>
        </param>
        <param>
            <name>A1_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>PAD_DQ62</name>
            <value>V14</value>
        </param>
        <param>
            <name>DDRC_T_RAS</name>
            <value>14</value>
        </param>
        <param>
            <name>PAD_DQ67</name>
            <value>R26</value>
        </param>
        <param>
            <name>tREFI</name>
            <value>7800</value>
        </param>
        <param>
            <name>CAS_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>GPLL_BANDWIDTH</name>
            <value>OPTIMIZED</value>
        </param>
        <param>
            <name>PAD_DQ14</name>
            <value>L3</value>
        </param>
        <param>
            <name>PAD_DM6</name>
            <value>V19</value>
        </param>
        <param>
            <name>CUSTOMIZE_CA</name>
            <value>true</value>
        </param>
        <param>
            <name>DQ0_BANK_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>PAD_DQ71</name>
            <value>T23</value>
        </param>
        <param>
            <name>A15_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>A10_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>GUI_DDR2_TREFI</name>
            <value>7.800</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>PAD_DQ37</name>
            <value>Y26</value>
        </param>
        <param>
            <name>BANK2</name>
            <value>L4</value>
        </param>
        <param>
            <name>PAD_A4</name>
            <item>R2</item>
            <item>R3</item>
            <item>T1</item>
            <item>T3</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>V2</item>
            <item>V3</item>
            <item>W1</item>
            <item>W2</item>
            <item>Y1</item>
            <item>Y2</item>
            <value>R3</value>
        </param>
        <param>
            <name>PAD_DQSN7</name>
            <value>T18</value>
        </param>
        <param>
            <name>CS_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>PAD_DQ40</name>
            <value>AA24</value>
        </param>
        <param>
            <name>PAD_CKE</name>
            <item>AA1</item>
            <item>AA3</item>
            <item>AA4</item>
            <item>AA5</item>
            <item>AB1</item>
            <item>AB2</item>
            <item>AB3</item>
            <item>AB5</item>
            <item>V4</item>
            <item>W4</item>
            <item>Y3</item>
            <item>Y4</item>
            <value>W4</value>
        </param>
        <param>
            <name>LPDDR_DRIVER_STRENGTH</name>
            <value>000</value>
        </param>
        <param>
            <name>PAD_DQ69</name>
            <value>T22</value>
        </param>
        <param>
            <name>GUI_LPDDR_CL_400</name>
            <value>2</value>
        </param>
        <param>
            <name>A3_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>PAD_DQ27</name>
            <value>N2</value>
        </param>
        <param>
            <name>PAD_A11</name>
            <item>AA1</item>
            <item>AA3</item>
            <item>AA4</item>
            <item>AA5</item>
            <item>AB1</item>
            <item>AB2</item>
            <item>AB3</item>
            <item>AB5</item>
            <item>V4</item>
            <item>W4</item>
            <item>Y3</item>
            <item>Y4</item>
            <value>AA1</value>
        </param>
        <param>
            <name>GUI_LPDDR_TREFI</name>
            <value>7.800</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>DDR3_CL</name>
            <value>6</value>
        </param>
        <param>
            <name>BANK_DQG_7</name>
            <item>L3</item>
            <item>L4</item>
            <item>L5</item>
            <item>R4</item>
            <item>R5</item>
            <value>L4</value>
        </param>
        <param>
            <name>PAD_DQ11</name>
            <value>K4</value>
        </param>
        <param>
            <name>PAD_DQ70</name>
            <value>R22</value>
        </param>
        <param>
            <name>PAD_DQ19</name>
            <value>J6</value>
        </param>
        <param>
            <name>GROUP_A11</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G1</value>
        </param>
        <param>
            <name>DQ0_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>PAD_DQ35</name>
            <value>W26</value>
        </param>
        <param>
            <name>PHY_TRFC</name>
            <value>26</value>
        </param>
        <param>
            <name>PAD_DQSN3</name>
            <value>P4</value>
        </param>
        <param>
            <name>BANK_DQG_2</name>
            <item>L3</item>
            <item>L4</item>
            <item>L5</item>
            <item>R4</item>
            <item>R5</item>
            <value>R4</value>
        </param>
        <param>
            <name>PAD_ODT</name>
            <item>AA6</item>
            <item>R4</item>
            <item>R6</item>
            <item>T4</item>
            <item>T5</item>
            <item>T6</item>
            <item>U5</item>
            <item>U6</item>
            <item>V5</item>
            <item>W5</item>
            <item>W6</item>
            <item>Y6</item>
            <value>R6</value>
        </param>
        <param>
            <name>MEM_DQS_WIDTH</name>
            <value>2</value>
        </param>
        <param>
            <name>GROUP_A15</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G2</value>
        </param>
        <param>
            <name>DDR2_AL</name>
            <value>2</value>
        </param>
        <param>
            <name>A14_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>DQ5_BANK_NUM</name>
            <value>2</value>
        </param>
        <param>
            <name>PAD_DQ13</name>
            <value>L4</value>
        </param>
        <param>
            <name>WE_GROUP_NUM</name>
            <value>2</value>
        </param>
        <param>
            <name>ACTUAL_RATE</name>
            <value>800.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>PAD_WE</name>
            <item>AA6</item>
            <item>R4</item>
            <item>R6</item>
            <item>T4</item>
            <item>T5</item>
            <item>T6</item>
            <item>U5</item>
            <item>U6</item>
            <item>V5</item>
            <item>W5</item>
            <item>W6</item>
            <item>Y6</item>
            <value>W6</value>
        </param>
        <param>
            <name>A6_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>GUI_DDR3_TRCD</name>
            <value>13.910</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>DDR2_ODT_VALUE</name>
            <value>01</value>
        </param>
        <param>
            <name>PAD_DQSN1</name>
            <value>L1</value>
        </param>
        <param>
            <name>PAD_DQ21</name>
            <value>K6</value>
        </param>
        <param>
            <name>GROUP_ODT</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G2</value>
        </param>
        <param>
            <name>MEM_TYPE</name>
            <value>DDR3</value>
        </param>
        <param>
            <name>GUI_DDR2_TRTP</name>
            <value>7.500</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>GROUP_CS</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G2</value>
        </param>
        <param>
            <name>ODT_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>PAD_A5</name>
            <item>R2</item>
            <item>R3</item>
            <item>T1</item>
            <item>T3</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>V2</item>
            <item>V3</item>
            <item>W1</item>
            <item>W2</item>
            <item>Y1</item>
            <item>Y2</item>
            <value>R2</value>
        </param>
        <param>
            <name>PAD_A6</name>
            <item>R2</item>
            <item>R3</item>
            <item>T1</item>
            <item>T3</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>V2</item>
            <item>V3</item>
            <item>W1</item>
            <item>W2</item>
            <item>Y1</item>
            <item>Y2</item>
            <value>W2</value>
        </param>
        <param>
            <name>PAD_DQ2</name>
            <value>M6</value>
        </param>
        <param>
            <name>DQ7_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>GROUP_DQG_2</name>
            <value>G2</value>
        </param>
        <param>
            <name>OPERATING_MODE</name>
            <item>Controller + PHY</item>
            <item>PHY Only</item>
            <value>Controller + PHY</value>
        </param>
        <param>
            <name>DDRC_T_RCD</name>
            <value>6</value>
        </param>
        <param>
            <name>A14_GROUP_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>PAD_DQ18</name>
            <value>L3</value>
        </param>
        <param>
            <name>PAD_DQ44</name>
            <value>V23</value>
        </param>
        <param>
            <name>PAD_RAS</name>
            <item>AA6</item>
            <item>R4</item>
            <item>R6</item>
            <item>T4</item>
            <item>T5</item>
            <item>T6</item>
            <item>U5</item>
            <item>U6</item>
            <item>V5</item>
            <item>W5</item>
            <item>W6</item>
            <item>Y6</item>
            <value>W5</value>
        </param>
        <param>
            <name>DQ3_BANK_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>USER_PINS_CON_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>LPDDR_MEM_ROW_WIDTH</name>
            <value>14</value>
        </param>
        <param>
            <name>DDR2_OUTPUT_DRIVER</name>
            <value>0</value>
        </param>
        <param>
            <name>GUI_DDR3_TRAS</name>
            <value>35.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>PAD_DQS8</name>
            <value>T24</value>
        </param>
        <param>
            <name>LPDDR_BASE_MEM_PART</name>
            <value>MT46H128M16XXXX-5L-IT</value>
        </param>
        <param>
            <name>GUI_DDR2_AL</name>
            <value>2</value>
        </param>
        <param>
            <name>BANK1</name>
            <value>R4</value>
        </param>
        <param>
            <name>DQ4_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>GROUP_A14</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G1</value>
        </param>
        <param>
            <name>DQ8_BANK_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>PAD_DQ57</name>
            <value>T14</value>
        </param>
        <param>
            <name>PAD_DM2</name>
            <value>M2</value>
        </param>
        <param>
            <name>GUI_LPDDR_TWTR</name>
            <value>2</value>
        </param>
        <param>
            <name>BANK_DQG_1</name>
            <item>L3</item>
            <item>L4</item>
            <item>L5</item>
            <item>R4</item>
            <item>R5</item>
            <value>R4</value>
        </param>
        <param>
            <name>MEM_BANK_WIDTH</name>
            <value>3</value>
        </param>
        <param>
            <name>PAD_DQSN5</name>
            <value>AC24</value>
        </param>
        <param>
            <name>GROUP_A8</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G0</value>
        </param>
        <param>
            <name>PAD_DQ56</name>
            <value>V18</value>
        </param>
        <param>
            <name>DDR3_AL</name>
            <value>2</value>
        </param>
        <param>
            <name>CS_n_En</name>
            <value>true</value>
        </param>
        <param>
            <name>DDR3_MEM_COLUMN_WIDTH</name>
            <value>10</value>
        </param>
        <param>
            <name>A12_GROUP_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>PAD_A9</name>
            <item>R2</item>
            <item>R3</item>
            <item>T1</item>
            <item>T3</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>V2</item>
            <item>V3</item>
            <item>W1</item>
            <item>W2</item>
            <item>Y1</item>
            <item>Y2</item>
            <value>Y1</value>
        </param>
        <param>
            <name>DDR3_CWL</name>
            <value>5</value>
        </param>
        <param>
            <name>GROUP_CAS</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G2</value>
        </param>
        <param>
            <name>PAD_DQSN0</name>
            <value>D1</value>
        </param>
        <param>
            <name>GROUP_A13</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G1</value>
        </param>
        <param>
            <name>GUI_LPDDR_TWR</name>
            <value>15.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>LPDDR_MEM_COLUMN_WIDTH</name>
            <value>11</value>
        </param>
        <param>
            <name>MEM_COLUMN_WIDTH</name>
            <value>10</value>
        </param>
        <param>
            <name>PAD_A2</name>
            <item>R2</item>
            <item>R3</item>
            <item>T1</item>
            <item>T3</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>V2</item>
            <item>V3</item>
            <item>W1</item>
            <item>W2</item>
            <item>Y1</item>
            <item>Y2</item>
            <value>U2</value>
        </param>
        <param>
            <name>BANK_CA</name>
            <item>L3</item>
            <item>L4</item>
            <item>L5</item>
            <item>R4</item>
            <item>R5</item>
            <value>R5</value>
        </param>
        <param>
            <name>A2_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>PAD_DQ38</name>
            <value>Y25</value>
        </param>
        <param>
            <name>GUI_DDR3_AL</name>
            <value>CL-2</value>
        </param>
        <param>
            <name>GROUP_A12</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G1</value>
        </param>
        <param>
            <name>PAD_DQ10</name>
            <value>K3</value>
        </param>
        <param>
            <name>A5_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>BANK_DQG_8</name>
            <item>L3</item>
            <item>L4</item>
            <item>L5</item>
            <item>R4</item>
            <item>R5</item>
            <value>L5</value>
        </param>
        <param>
            <name>DQ5_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>BA2_GROUP_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>PAD_CS</name>
            <item>AA6</item>
            <item>R4</item>
            <item>R6</item>
            <item>T4</item>
            <item>T5</item>
            <item>T6</item>
            <item>U5</item>
            <item>U6</item>
            <item>V5</item>
            <item>W5</item>
            <item>W6</item>
            <item>Y6</item>
            <value>V5</value>
        </param>
        <param>
            <name>PAD_DQ41</name>
            <value>AB25</value>
        </param>
        <param>
            <name>CUSTOMIZE_MEM</name>
            <value>true</value>
        </param>
        <param>
            <name>GROUP_WE</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G2</value>
        </param>
        <param>
            <name>GUI_DDR3_TWR</name>
            <value>15.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>A13_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>DDR2_DFT_MEM_PART</name>
            <value>MT47H128M16XX-25E</value>
        </param>
        <param>
            <name>DDR2_WR</name>
            <value>5</value>
        </param>
        <param>
            <name>A15_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>PAD_BA1</name>
            <item>AA1</item>
            <item>AA3</item>
            <item>AA4</item>
            <item>AA5</item>
            <item>AB1</item>
            <item>AB2</item>
            <item>AB3</item>
            <item>AB5</item>
            <item>V4</item>
            <item>W4</item>
            <item>Y3</item>
            <item>Y4</item>
            <value>AA5</value>
        </param>
        <param>
            <name>LPDDR_MEM_BANK_WIDTH</name>
            <value>2</value>
        </param>
        <param>
            <name>GROUP_DQG_6</name>
            <value>G2</value>
        </param>
        <param>
            <name>PAD_DQ12</name>
            <value>K6</value>
        </param>
        <param>
            <name>CS_GROUP_NUM</name>
            <value>2</value>
        </param>
        <param>
            <name>GUI_LPDDR_TRP</name>
            <value>22.500</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>PAD_DQ46</name>
            <value>Y22</value>
        </param>
        <param>
            <name>DDR2_MEM_ROW_WIDTH</name>
            <value>14</value>
        </param>
        <param>
            <name>PHY_TMRD</name>
            <value>4</value>
        </param>
        <param>
            <name>A0_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>CS_N_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>CK_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>DDR_CHIP_DQ_WIDTH</name>
            <value>true</value>
        </param>
        <param>
            <name>PAD_DQ47</name>
            <value>Y23</value>
        </param>
        <param>
            <name>PAD_DQS1</name>
            <value>M1</value>
        </param>
        <param>
            <name>PAD_A14</name>
            <item>AA1</item>
            <item>AA3</item>
            <item>AA4</item>
            <item>AA5</item>
            <item>AB1</item>
            <item>AB2</item>
            <item>AB3</item>
            <item>AB5</item>
            <item>V4</item>
            <item>W4</item>
            <item>Y3</item>
            <item>Y4</item>
            <value>AB2</value>
        </param>
        <param>
            <name>PAD_DQ36</name>
            <value>W25</value>
        </param>
        <param>
            <name>PAD_DQ51</name>
            <value>Y21</value>
        </param>
        <param>
            <name>A8_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>DQ7_BANK_NUM</name>
            <value>2</value>
        </param>
        <param>
            <name>CK_GROUP_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>PAD_DQ55</name>
            <value>U19</value>
        </param>
        <param>
            <name>PAD_DQSN2</name>
            <value>L1</value>
        </param>
        <param>
            <name>PAD_DM1</name>
            <value>M2</value>
        </param>
        <param>
            <name>PAD_CK</name>
            <item>AA1</item>
            <item>AA3</item>
            <item>AA4</item>
            <item>AA5</item>
            <item>AB1</item>
            <item>AB2</item>
            <item>AB3</item>
            <item>AB5</item>
            <item>V4</item>
            <item>W4</item>
            <item>Y3</item>
            <item>Y4</item>
            <value>Y4</value>
        </param>
        <param>
            <name>PAD_DQ6</name>
            <value>N5</value>
        </param>
        <param>
            <name>GROUP_A1</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G0</value>
        </param>
        <param>
            <name>A6_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>GROUP_A2</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G0</value>
        </param>
        <param>
            <name>DDR2_INIT_WR</name>
            <value>6</value>
        </param>
        <param>
            <name>DQ1_BANK_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>PAD_DQ0</name>
            <value>L6</value>
        </param>
        <param>
            <name>A9_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>A8_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>DDR2_MEM_BANK_WIDTH</name>
            <value>3</value>
        </param>
        <param>
            <name>PAD_DQ43</name>
            <value>AA23</value>
        </param>
        <param>
            <name>DDR2_MEM_COLUMN_WIDTH</name>
            <value>10</value>
        </param>
        <param>
            <name>BA2_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>GROUP_DQG_1</name>
            <value>G2</value>
        </param>
        <param>
            <name>GROUP_A7</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G0</value>
        </param>
        <param>
            <name>PAD_DQ17</name>
            <value>M3</value>
        </param>
        <param>
            <name>PAD_DQ23</name>
            <value>L5</value>
        </param>
        <param>
            <name>DQ6_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>USER_FDC_PATH</name>
            <value>Please select a fdc file</value>
        </param>
        <param>
            <name>PAD_DQ24</name>
            <value>P1</value>
        </param>
        <param>
            <name>GUI_DDR3_TRTP</name>
            <value>7.500</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>DDR3_INIT_WR</name>
            <value>6</value>
        </param>
        <param>
            <name>A11_GROUP_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>DESIRED_DDR3_RATE</name>
            <value>800.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>PAD_DM7</name>
            <value>V17</value>
        </param>
        <param>
            <name>PAD_A13</name>
            <item>AA1</item>
            <item>AA3</item>
            <item>AA4</item>
            <item>AA5</item>
            <item>AB1</item>
            <item>AB2</item>
            <item>AB3</item>
            <item>AB5</item>
            <item>V4</item>
            <item>W4</item>
            <item>Y3</item>
            <item>Y4</item>
            <value>AB3</value>
        </param>
        <param>
            <name>PAD_DM0</name>
            <value>P5</value>
        </param>
        <param>
            <name>PAD_DQS6</name>
            <value>T20</value>
        </param>
        <param>
            <name>PAD_DQ54</name>
            <value>T19</value>
        </param>
        <param>
            <name>A15_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>GUI_DDR3_CL_1066</name>
            <value>6</value>
        </param>
        <param>
            <name>A5_DQS_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>STATIC_RATIOF</name>
            <value>64</value>
        </param>
        <param>
            <name>A10_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>DDRC_T_WTR</name>
            <value>4</value>
        </param>
        <param>
            <name>A1_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>GUI_DDR3_TREFI</name>
            <value>7.800</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>GROUP_A4</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G0</value>
        </param>
        <param>
            <name>DQ2_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>BANK_DQG_4</name>
            <item>L3</item>
            <item>L4</item>
            <item>L5</item>
            <item>R4</item>
            <item>R5</item>
            <value>L4</value>
        </param>
        <param>
            <name>PHY_TRCD</name>
            <value>2</value>
        </param>
        <param>
            <name>GROUP_CKE</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G1</value>
        </param>
        <param>
            <name>PAD_DQS5</name>
            <value>AB24</value>
        </param>
        <param>
            <name>BANK_DQG_6</name>
            <item>L3</item>
            <item>L4</item>
            <item>L5</item>
            <item>R4</item>
            <item>R5</item>
            <value>L4</value>
        </param>
        <param>
            <name>GROUP_DQG_8</name>
            <value>G0</value>
        </param>
        <param>
            <name>DQ8_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>GROUP_BA1</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G1</value>
        </param>
        <param>
            <name>PAD_DQ49</name>
            <value>V21</value>
        </param>
        <param>
            <name>PAD_DQ25</name>
            <value>N4</value>
        </param>
        <param>
            <name>GROUP_DQG_5</name>
            <value>G1</value>
        </param>
        <param>
            <name>RAS_DQS_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>DDR3_DFT_MEM_PART</name>
            <value>MT41K128M16XX</value>
        </param>
        <param>
            <name>PHY_TMOD</name>
            <value>12</value>
        </param>
        <param>
            <name>CS_n_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>LPDDR_CL_VALUE</name>
            <value>2</value>
        </param>
        <param>
            <name>PAD_DQ31</name>
            <value>P2</value>
        </param>
        <param>
            <name>CTRL_ADDR_WIDTH</name>
            <value>28</value>
        </param>
        <param>
            <name>GUI_DDR2_TRAS</name>
            <value>45.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>GUI_LPDDR_TRCD</name>
            <value>22.500</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>GUI_DDR3_TWTR</name>
            <value>7.500</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>BA0_DQS_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>GROUP_A9</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G0</value>
        </param>
        <param>
            <name>DDRC_TREFI</name>
            <value>3120</value>
        </param>
        <param>
            <name>GROUP_A0</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G0</value>
        </param>
        <param>
            <name>PAD_DQ50</name>
            <value>W21</value>
        </param>
        <param>
            <name>BA1_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>PAD_DM5</name>
            <value>U22</value>
        </param>
        <param>
            <name>MEM_ROW_WIDTH</name>
            <value>15</value>
        </param>
        <param>
            <name>DDRC_T_RP</name>
            <value>6</value>
        </param>
        <param>
            <name>DFI_CLK_PERIOD</name>
            <value>10000</value>
        </param>
        <param>
            <name>PAD_DQ48</name>
            <value>U21</value>
        </param>
        <param>
            <name>CAS_GROUP_NUM</name>
            <value>2</value>
        </param>
        <param>
            <name>PAD_DQS0</name>
            <value>P4</value>
        </param>
        <param>
            <name>GUI_LPDDR_TRFC</name>
            <value>140.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>DQ6_BANK_NUM</name>
            <value>2</value>
        </param>
        <param>
            <name>tRFC_MIN</name>
            <value>260000.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>DDRC_T_WR</name>
            <value>6</value>
        </param>
        <param>
            <name>GUI_DDR3_CWL_800</name>
            <value>5</value>
        </param>
        <param>
            <name>DDR3_BASE_MEM_PART</name>
            <value>MT41K256M16XX</value>
        </param>
        <param>
            <name>PAD_DQS2</name>
            <value>M1</value>
        </param>
        <param>
            <name>PAD_DQ3</name>
            <value>N2</value>
        </param>
        <param>
            <name>BANK_NUM</name>
            <value>2</value>
        </param>
        <param>
            <name>PAD_DQS7</name>
            <value>T17</value>
        </param>
        <param>
            <name>PAD_DQ39</name>
            <value>AA25</value>
        </param>
        <param>
            <name>GUI_DDR2_TRFC</name>
            <value>195.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>GUI_LPDDR_TRAS</name>
            <value>45.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>GUI_DDR2_TWTR</name>
            <value>7.500</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>DESIRED_RATE</name>
            <value>800.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>DDRC_T_RC</name>
            <value>20</value>
        </param>
        <param>
            <name>GUI_DDR3_CL_800</name>
            <value>6</value>
        </param>
        <param>
            <name>PAD_DQ5</name>
            <value>N4</value>
        </param>
        <param>
            <name>PAD_DQ33</name>
            <value>U26</value>
        </param>
        <param>
            <name>GROUP_A5</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G0</value>
        </param>
        <param>
            <name>PAD_CAS</name>
            <item>AA6</item>
            <item>R4</item>
            <item>R6</item>
            <item>T4</item>
            <item>T5</item>
            <item>T6</item>
            <item>U5</item>
            <item>U6</item>
            <item>V5</item>
            <item>W5</item>
            <item>W6</item>
            <item>Y6</item>
            <value>U6</value>
        </param>
        <param>
            <name>DQ4_BANK_NUM</name>
            <value>2</value>
        </param>
        <param>
            <name>PAD_A10</name>
            <item>R2</item>
            <item>R3</item>
            <item>T1</item>
            <item>T3</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>V2</item>
            <item>V3</item>
            <item>W1</item>
            <item>W2</item>
            <item>Y1</item>
            <item>Y2</item>
            <value>U3</value>
        </param>
        <param>
            <name>PAD_DQ58</name>
            <value>T15</value>
        </param>
        <param>
            <name>GROUP_CKN</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G1</value>
        </param>
        <param>
            <name>A7_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>PAD_A15</name>
            <item>AA6</item>
            <item>R4</item>
            <item>R6</item>
            <item>T4</item>
            <item>T5</item>
            <item>T6</item>
            <item>U5</item>
            <item>U6</item>
            <item>V5</item>
            <item>W5</item>
            <item>W6</item>
            <item>Y6</item>
            <value>U6</value>
        </param>
        <param>
            <name>PAD_DQ64</name>
            <value>R25</value>
        </param>
        <param>
            <name>PAD_DQSN8</name>
            <value>T25</value>
        </param>
        <param>
            <name>DEVICE_100H_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>PAD_DQ61</name>
            <value>U14</value>
        </param>
        <param>
            <name>A11_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>DDR3_OUTPUT_DRIVER</name>
            <value>00</value>
        </param>
        <param>
            <name>PAD_DQ53</name>
            <value>Y20</value>
        </param>
        <param>
            <name>PAD_DQ63</name>
            <value>V16</value>
        </param>
        <param>
            <name>PAD_DQ20</name>
            <value>K3</value>
        </param>
        <param>
            <name>A7_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>BANK_PLL_REF</name>
            <item>L3</item>
            <item>L4</item>
            <item>L5</item>
            <item>R4</item>
            <item>R5</item>
            <value>R5</value>
        </param>
        <param>
            <name>PAD_A12</name>
            <item>AA1</item>
            <item>AA3</item>
            <item>AA4</item>
            <item>AA5</item>
            <item>AB1</item>
            <item>AB2</item>
            <item>AB3</item>
            <item>AB5</item>
            <item>V4</item>
            <item>W4</item>
            <item>Y3</item>
            <item>Y4</item>
            <value>AB1</value>
        </param>
        <param>
            <name>MEM_ADDR_WIDTH</name>
            <value>15</value>
        </param>
        <param>
            <name>GROUP_BA0</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G1</value>
        </param>
        <param>
            <name>A0_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>LPDDR_CL</name>
            <value>2</value>
        </param>
        <param>
            <name>PAD_A8</name>
            <item>R2</item>
            <item>R3</item>
            <item>T1</item>
            <item>T3</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>V2</item>
            <item>V3</item>
            <item>W1</item>
            <item>W2</item>
            <item>Y1</item>
            <item>Y2</item>
            <value>W1</value>
        </param>
        <param>
            <name>PAD_DQ42</name>
            <value>AA22</value>
        </param>
        <param>
            <name>PPLL_BANDWIDTH</name>
            <value>LOW</value>
        </param>
        <param>
            <name>MEM_DM_WIDTH</name>
            <value>2</value>
        </param>
        <param>
            <name>A3_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>DESIRED_LPDDR_RATE</name>
            <value>200.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>CKE_GROUP_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>PAD_DQ29</name>
            <value>N5</value>
        </param>
        <param>
            <name>PAD_DQ45</name>
            <value>W23</value>
        </param>
        <param>
            <name>PAD_DQ8</name>
            <value>J4</value>
        </param>
        <param>
            <name>CKE_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>PAD_DQ34</name>
            <value>V26</value>
        </param>
        <param>
            <name>PAD_A1</name>
            <item>R2</item>
            <item>R3</item>
            <item>T1</item>
            <item>T3</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>V2</item>
            <item>V3</item>
            <item>W1</item>
            <item>W2</item>
            <item>Y1</item>
            <item>Y2</item>
            <value>U1</value>
        </param>
        <param>
            <name>BA1_GROUP_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>PAD_DQ26</name>
            <value>R1</value>
        </param>
        <param>
            <name>GUI_DDR2_TRP</name>
            <value>13.500</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>A9_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>GROUP_DQG_0</name>
            <value>G3</value>
        </param>
        <param>
            <name>DDR3_WR</name>
            <value>2</value>
        </param>
        <param>
            <name>BA0_GROUP_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>PAD_A7</name>
            <item>R2</item>
            <item>R3</item>
            <item>T1</item>
            <item>T3</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>V2</item>
            <item>V3</item>
            <item>W1</item>
            <item>W2</item>
            <item>Y1</item>
            <item>Y2</item>
            <value>Y2</value>
        </param>
        <param>
            <name>PAD_A3</name>
            <item>R2</item>
            <item>R3</item>
            <item>T1</item>
            <item>T3</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>V2</item>
            <item>V3</item>
            <item>W1</item>
            <item>W2</item>
            <item>Y1</item>
            <item>Y2</item>
            <value>V2</value>
        </param>
        <param>
            <name>PAD_DQ16</name>
            <value>L4</value>
        </param>
        <param>
            <name>DDRC_T_FAW</name>
            <value>18</value>
        </param>
        <param>
            <name>PAD_BA2</name>
            <item>AA1</item>
            <item>AA3</item>
            <item>AA4</item>
            <item>AA5</item>
            <item>AB1</item>
            <item>AB2</item>
            <item>AB3</item>
            <item>AB5</item>
            <item>V4</item>
            <item>W4</item>
            <item>Y3</item>
            <item>Y4</item>
            <value>AB5</value>
        </param>
        <param>
            <name>GROUP_RAS</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G2</value>
        </param>
        <param>
            <name>GUI_DDR3_TRFC</name>
            <value>260.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>PHY_TXPR</name>
            <value>27</value>
        </param>
        <param>
            <name>PAD_DM4</name>
            <value>V24</value>
        </param>
        <param>
            <name>ODT_GROUP_NUM</name>
            <value>2</value>
        </param>
        <param>
            <name>GROUP_A3</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G0</value>
        </param>
        <param>
            <name>A12_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>A13_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>LPDDR_DFT_MEM_PART</name>
            <value>MT46H128M16XXXX-5L-IT</value>
        </param>
        <param>
            <name>PAD_DQ59</name>
            <value>U15</value>
        </param>
        <param>
            <name>BANK0</name>
            <value>R5</value>
        </param>
        <param>
            <name>PAD_DQ32</name>
            <value>U25</value>
        </param>
        <param>
            <name>A2_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>GROUP_A10</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G0</value>
        </param>
        <param>
            <name>DDR2_BASE_MEM_PART</name>
            <value>MT47H128M16XX-25E</value>
        </param>
        <param>
            <name>GROUP_DQG_7</name>
            <value>G3</value>
        </param>
        <param>
            <name>GUI_DDR2_TRCD</name>
            <value>12.500</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>CA_GROUP_NUM</name>
            <value>3</value>
        </param>
        <param>
            <name>PAD_DQ22</name>
            <value>J4</value>
        </param>
        <param>
            <name>A4_DQS_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>CLKIN_FREQ</name>
            <value>25.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>GUI_LPDDR_CL_200</name>
            <value>2</value>
        </param>
        <param>
            <name>GROUP_BA2</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G1</value>
        </param>
        <param>
            <name>WE_DQS_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>GUI_DDR3_CWL_1066</name>
            <value>5</value>
        </param>
        <param>
            <name>PAD_A0</name>
            <item>R2</item>
            <item>R3</item>
            <item>T1</item>
            <item>T3</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>V2</item>
            <item>V3</item>
            <item>W1</item>
            <item>W2</item>
            <item>Y1</item>
            <item>Y2</item>
            <value>T1</value>
        </param>
        <param>
            <name>DESIRED_DDR2_RATE</name>
            <value>600.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>PAD_DQ15</name>
            <value>L4</value>
        </param>
        <param>
            <name>BANK_DQG_5</name>
            <item>L3</item>
            <item>L4</item>
            <item>L5</item>
            <item>R4</item>
            <item>R5</item>
            <value>L4</value>
        </param>
        <param>
            <name>GROUP_CK</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G1</value>
        </param>
        <param>
            <name>PAD_DQS3</name>
            <value>P5</value>
        </param>
        <param>
            <name>DDRC_TRFC</name>
            <value>104</value>
        </param>
        <param>
            <name>DQ3_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>PAD_DQSN4</name>
            <value>AC26</value>
        </param>
        <param>
            <name>GUI_DDR3_TRP</name>
            <value>13.910</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>GROUP_A6</name>
            <item>G0</item>
            <item>G1</item>
            <item>G2</item>
            <item>G3</item>
            <value>G0</value>
        </param>
        <param>
            <name>PAD_DQ1</name>
            <value>M5</value>
        </param>
        <param>
            <name>BANK_DQG_0</name>
            <item>L3</item>
            <item>L4</item>
            <item>L5</item>
            <item>R4</item>
            <item>R5</item>
            <value>R4</value>
        </param>
        <param>
            <name>DDR3_ODT_VALUE</name>
            <value>001</value>
        </param>
        <param>
            <name>PAD_DM8</name>
            <value>R23</value>
        </param>
        <param>
            <name>BANK_DQG_3</name>
            <item>L3</item>
            <item>L4</item>
            <item>L5</item>
            <item>R4</item>
            <item>R5</item>
            <value>R4</value>
        </param>
        <param>
            <name>PAD_DQ52</name>
            <value>W20</value>
        </param>
        <param>
            <name>PAD_DQ60</name>
            <value>U16</value>
        </param>
        <param>
            <name>MEM_DQ_WIDTH</name>
            <item>32</item>
            <item>24</item>
            <item>16</item>
            <item>8</item>
            <value>16</value>
        </param>
        <param>
            <name>DDR_MEM_PART</name>
            <value>MT41K256M16XX</value>
        </param>
        <param>
            <name>GUI_DDR2_CL</name>
            <value>4</value>
        </param>
        <param>
            <name>A14_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>DDR3_MEM_BANK_WIDTH</name>
            <value>3</value>
        </param>
        <param>
            <name>STATIC_RATIOI</name>
            <value>1</value>
        </param>
        <param>
            <name>PAD_BA0</name>
            <item>AA1</item>
            <item>AA3</item>
            <item>AA4</item>
            <item>AA5</item>
            <item>AB1</item>
            <item>AB2</item>
            <item>AB3</item>
            <item>AB5</item>
            <item>V4</item>
            <item>W4</item>
            <item>Y3</item>
            <item>Y4</item>
            <value>AA3</value>
        </param>
        <param>
            <name>PAD_CKN</name>
            <item>AA1</item>
            <item>AA3</item>
            <item>AA4</item>
            <item>AA5</item>
            <item>AB1</item>
            <item>AB2</item>
            <item>AB3</item>
            <item>AB5</item>
            <item>V4</item>
            <item>W4</item>
            <item>Y3</item>
            <item>Y4</item>
            <value>AA4</value>
        </param>
        <param>
            <name>PAD_DQ30</name>
            <value>P6</value>
        </param>
        <param>
            <name>DQ2_BANK_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>STATIC_RATIO0</name>
            <value>2</value>
        </param>
        <param>
            <name>RAS_GROUP_NUM</name>
            <value>2</value>
        </param>
        <param>
            <name>PAD_DQ7</name>
            <value>P1</value>
        </param>
        <param>
            <name>DDRC_T_RRD</name>
            <value>4</value>
        </param>
        <param>
            <name>PAD_DM3</name>
            <value>M5</value>
        </param>
        <param>
            <name>PAD_RESET</name>
            <item>AA1</item>
            <item>AA3</item>
            <item>AA4</item>
            <item>AA5</item>
            <item>AA6</item>
            <item>AA8</item>
            <item>AB1</item>
            <item>AB2</item>
            <item>AB3</item>
            <item>AB5</item>
            <item>AB6</item>
            <item>AB7</item>
            <item>AB8</item>
            <item>R2</item>
            <item>R3</item>
            <item>R4</item>
            <item>R6</item>
            <item>T1</item>
            <item>T3</item>
            <item>T4</item>
            <item>T5</item>
            <item>T6</item>
            <item>U1</item>
            <item>U2</item>
            <item>U3</item>
            <item>U5</item>
            <item>U6</item>
            <item>U7</item>
            <item>V2</item>
            <item>V3</item>
            <item>V4</item>
            <item>V5</item>
            <item>V7</item>
            <item>V8</item>
            <item>V9</item>
            <item>W1</item>
            <item>W2</item>
            <item>W4</item>
            <item>W5</item>
            <item>W6</item>
            <item>W7</item>
            <item>W9</item>
            <item>Y1</item>
            <item>Y2</item>
            <item>Y3</item>
            <item>Y4</item>
            <item>Y6</item>
            <item>Y7</item>
            <item>Y8</item>
            <item>Y9</item>
            <value>T3</value>
        </param>
        <param>
            <name>DDRC_T_XP</name>
            <value>3</value>
        </param>
        <param>
            <name>PAD_DQ9</name>
            <value>J6</value>
        </param>
        <param>
            <name>BA2_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>PAD_DQ28</name>
            <value>M6</value>
        </param>
        <param>
            <name>DDRC_T_RTP</name>
            <value>4</value>
        </param>
        <param>
            <name>DDR2_CL_VALUE</name>
            <value>4</value>
        </param>
        <param>
            <name>PAD_DQ66</name>
            <value>M26</value>
        </param>
        <param>
            <name>PAD_DQSN6</name>
            <value>U20</value>
        </param>
        <param>
            <name>A13_GROUP_NUM</name>
            <value>1</value>
        </param>
        <param>
            <name>PAD_DQS4</name>
            <value>AB26</value>
        </param>
        <param>
            <name>DDR3_MEM_ROW_WIDTH</name>
            <value>15</value>
        </param>
        <param>
            <name>PAD_DQ68</name>
            <value>P26</value>
        </param>
        <param>
            <name>GROUP_DQG_3</name>
            <value>G3</value>
        </param>
        <param>
            <name>GUI_DDR2_TWR</name>
            <value>15.000</value>
            <decimal>3</decimal>
        </param>
        <param>
            <name>DQ1_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>DDR3_CL_VALUE</name>
            <value>4</value>
        </param>
        <param>
            <name>A4_GROUP_NUM</name>
            <value>0</value>
        </param>
        <param>
            <name>A12_DQS_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>PAD_DQ4</name>
            <value>N3</value>
        </param>
        <param>
            <name>DDR2_CL</name>
            <value>4</value>
        </param>
    </param_list>
    <pin_list>
        <pin>
            <name>resetn</name>
            <text>resetn</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>core_clk</name>
            <text>core_clk</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>pll_lock</name>
            <text>pll_lock</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>phy_pll_lock</name>
            <text>phy_pll_lock</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>gpll_lock</name>
            <text>gpll_lock</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>rst_gpll_lock</name>
            <text>rst_gpll_lock</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>ddrphy_cpd_lock</name>
            <text>ddrphy_cpd_lock</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>ddr_init_done</name>
            <text>ddr_init_done</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>axi_awaddr</name>
            <text>axi_awaddr</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>27</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axi_awuser_ap</name>
            <text>axi_awuser_ap</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axi_awuser_id</name>
            <text>axi_awuser_id</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axi_awlen</name>
            <text>axi_awlen</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axi_awready</name>
            <text>axi_awready</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>axi_awvalid</name>
            <text>axi_awvalid</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axi_wdata</name>
            <text>axi_wdata</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>127</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axi_wstrb</name>
            <text>axi_wstrb</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>15</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axi_wready</name>
            <text>axi_wready</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>axi_wusero_id</name>
            <text>axi_wusero_id</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axi_wusero_last</name>
            <text>axi_wusero_last</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>axi_araddr</name>
            <text>axi_araddr</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>27</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axi_aruser_ap</name>
            <text>axi_aruser_ap</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axi_aruser_id</name>
            <text>axi_aruser_id</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axi_arlen</name>
            <text>axi_arlen</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axi_arready</name>
            <text>axi_arready</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>axi_arvalid</name>
            <text>axi_arvalid</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axi_rdata</name>
            <text>axi_rdata</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>127</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axi_rid</name>
            <text>axi_rid</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axi_rlast</name>
            <text>axi_rlast</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>axi_rvalid</name>
            <text>axi_rvalid</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>apb_clk</name>
            <text>apb_clk</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>apb_rst_n</name>
            <text>apb_rst_n</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>apb_sel</name>
            <text>apb_sel</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>apb_enable</name>
            <text>apb_enable</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>apb_addr</name>
            <text>apb_addr</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>7</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>apb_write</name>
            <text>apb_write</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>apb_ready</name>
            <text>apb_ready</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>apb_wdata</name>
            <text>apb_wdata</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>15</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>apb_rdata</name>
            <text>apb_rdata</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>15</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>mem_cs_n</name>
            <text>mem_cs_n</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>mem_rst_n</name>
            <text>mem_rst_n</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>mem_ck</name>
            <text>mem_ck</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>mem_ck_n</name>
            <text>mem_ck_n</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>mem_cke</name>
            <text>mem_cke</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>mem_ras_n</name>
            <text>mem_ras_n</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>mem_cas_n</name>
            <text>mem_cas_n</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>mem_we_n</name>
            <text>mem_we_n</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>mem_odt</name>
            <text>mem_odt</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>mem_a</name>
            <text>mem_a</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>14</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>mem_ba</name>
            <text>mem_ba</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>2</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>mem_dqs</name>
            <text>mem_dqs</text>
            <dir>inout</dir>
            <pos>left</pos>
            <msb>1</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>mem_dqs_n</name>
            <text>mem_dqs_n</text>
            <dir>inout</dir>
            <pos>left</pos>
            <msb>1</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>mem_dq</name>
            <text>mem_dq</text>
            <dir>inout</dir>
            <pos>left</pos>
            <msb>15</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>mem_dm</name>
            <text>mem_dm</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>1</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>dbg_gate_start</name>
            <text>dbg_gate_start</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>dbg_cpd_start</name>
            <text>dbg_cpd_start</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>dbg_ddrphy_rst_n</name>
            <text>dbg_ddrphy_rst_n</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>dbg_gpll_scan_rst</name>
            <text>dbg_gpll_scan_rst</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>samp_position_dyn_adj</name>
            <text>samp_position_dyn_adj</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>init_samp_position_even</name>
            <text>init_samp_position_even</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>15</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>init_samp_position_odd</name>
            <text>init_samp_position_odd</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>15</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>wrcal_position_dyn_adj</name>
            <text>wrcal_position_dyn_adj</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>init_wrcal_position</name>
            <text>init_wrcal_position</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>15</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>force_read_clk_ctrl</name>
            <text>force_read_clk_ctrl</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>init_slip_step</name>
            <text>init_slip_step</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>7</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>init_read_clk_ctrl</name>
            <text>init_read_clk_ctrl</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>5</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>debug_calib_ctrl</name>
            <text>debug_calib_ctrl</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>33</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>dbg_slice_status</name>
            <text>dbg_slice_status</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>33</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>dbg_slice_state</name>
            <text>dbg_slice_state</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>43</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>debug_data</name>
            <text>debug_data</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>137</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>dbg_dll_upd_state</name>
            <text>dbg_dll_upd_state</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>1</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>debug_gpll_dps_phase</name>
            <text>debug_gpll_dps_phase</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>8</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>dbg_rst_dps_state</name>
            <text>dbg_rst_dps_state</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>2</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>dbg_tran_err_rst_cnt</name>
            <text>dbg_tran_err_rst_cnt</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>5</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>dbg_ddrphy_init_fail</name>
            <text>dbg_ddrphy_init_fail</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>debug_cpd_offset_adj</name>
            <text>debug_cpd_offset_adj</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>debug_cpd_offset_dir</name>
            <text>debug_cpd_offset_dir</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>debug_cpd_offset</name>
            <text>debug_cpd_offset</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>9</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>debug_dps_cnt_dir0</name>
            <text>debug_dps_cnt_dir0</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>9</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>debug_dps_cnt_dir1</name>
            <text>debug_dps_cnt_dir1</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>9</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>ck_dly_en</name>
            <text>ck_dly_en</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>init_ck_dly_step</name>
            <text>init_ck_dly_step</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>7</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>ck_dly_set_bin</name>
            <text>ck_dly_set_bin</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>7</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>align_error</name>
            <text>align_error</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>debug_rst_state</name>
            <text>debug_rst_state</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>debug_cpd_state</name>
            <text>debug_cpd_state</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
    </pin_list>
    <synthesis>
        <script><![CDATA[set_option -vlog_std v2001]]></script>
        <script><![CDATA[set_option -disable_io_insertion 1]]></script>
    </synthesis>
    <file_list>
        <output>
            <file pathname="generate.log" format="log" description="Generate Log"/>
            <file pathname="sim_lib/ddrphy/ddr3_slice_top_v1_10.v" format="verilog" description="Compiled File"/>
            <file pathname="rtl/ddrphy/ddr3_slice_top_v1_10.v" format="verilog" description="Compiled File"/>
            <file pathname="example_design/rtl/test_ddr.v" format="verilog" description="Compiled File"/>
            <file pathname="example_design/bench/ddr3_tb/ddr3_test_top_tb.v" format="verilog" description="Compiled File"/>
            <file pathname="example_design/bench/ddr2_tb/ddr2_test_top_tb.v" format="verilog" description="Compiled File"/>
            <file pathname="example_design/bench/lpddr_tb/lpddr_test_top_tb.v" format="verilog" description="Compiled File"/>
            <file pathname="ddr3_tmpl.v" format="verilog" description="Instantiation Template"/>
            <file pathname="ddr3_tmpl.vhdl" format="vhdl" description="Instantiation Template"/>
        </output>
        <source>
            <file pathname="rtl/ips2l_rst_sync_v1_3.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp"/>
            <file pathname="rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp"/>
            <file pathname="rtl/pll/ips2l_ddrphy_gpll_v1_3.vp"/>
            <file pathname="rtl/pll/ips2l_ddrphy_ppll_v1_0.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp"/>
            <file pathname="rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp"/>
            <file pathname="rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp"/>
            <file pathname="rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp"/>
            <file pathname="rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp"/>
            <file pathname="rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp"/>
            <file pathname="ddr3.v"/>
            <file pathname="ddr3_ddrphy_top.v"/>
            <file pathname="rtl/ddrphy/ddr3_slice_top_v1_10.v"/>
        </source>
    </file_list>
</ip_inst>
