Generated by Fabric Compiler ( version 2022.2-SP6.4 <build 146967> ) at Thu Nov  6 19:56:36 2025


Cell Usage:
GTP_CLKBUFG                   3 uses
GTP_CLKBUFM                   1 use
GTP_CLKBUFR                   2 uses
GTP_CLKPD                     1 use
GTP_DDC_E2                    5 uses
GTP_DFF                     141 uses
GTP_DFF_C                  3897 uses
GTP_DFF_CE                 4032 uses
GTP_DFF_E                     8 uses
GTP_DFF_P                   141 uses
GTP_DFF_PE                  117 uses
GTP_DFF_R                    47 uses
GTP_DFF_RE                  156 uses
GTP_DFF_S                    41 uses
GTP_DFF_SE                   16 uses
GTP_DLL_E2                    2 uses
GTP_DRM18K_E1                83 uses
GTP_DRM36K_E1                 8 uses
GTP_GPLL                      3 uses
GTP_GRS                       1 use
GTP_HSSTLP_LANE               2 uses
GTP_HSSTLP_PLL                1 use
GTP_INV                      48 uses
GTP_IOCLKDIV_E3               2 uses
GTP_IODELAY_E2               41 uses
GTP_ISERDES_E2               16 uses
GTP_LUT1                     45 uses
GTP_LUT2                    243 uses
GTP_LUT3                    142 uses
GTP_LUT4                    438 uses
GTP_LUT5                    708 uses
GTP_LUT6                   2462 uses
GTP_LUT6CARRY              1116 uses
GTP_LUT6D                  1698 uses
GTP_MUX2LUT7                 26 uses
GTP_MUX2LUT8                  3 uses
GTP_OSERDES_E2               55 uses
GTP_PCIEGEN2                  1 use
GTP_PPLL                      2 uses
GTP_RAM32X1DP                 1 use
GTP_RAM32X2DP                43 uses
GTP_RAM64X1DP               574 uses
GTP_ROM64X1                   5 uses

I/O ports: 83
GTP_INBUF                  28 uses
GTP_IOBUF                  17 uses
GTP_IOBUFCO                 2 uses
GTP_OUTBUF                  5 uses
GTP_OUTBUFT                30 uses
GTP_OUTBUFTCO               1 use

Mapping Summary:
Total LUTs: 7475 of 35800 (20.88%)
	LUTs as dram: 618 of 9500 (6.51%)
	LUTs as logic: 6857
Total Registers: 8596 of 71600 (12.01%)
Total Latches: 0

DRM36K/FIFO:
Total DRM = 49.5 of 85 (58.24%)

APMs:
Total APMs = 0.00 of 120 (0.00%)

Total I/O ports = 86 of 250 (34.40%)


Overview of Control Sets:

Number of unique control sets : 328

Histogram:
**************************************************************
  Fanout      | Count    | Sync Set/Reset    Async Set/Reset
--------------------------------------------------------------
  [0, 2)      | 7        | 2                 5
  [2, 4)      | 58       | 9                 49
  [4, 6)      | 32       | 2                 30
  [6, 8)      | 30       | 2                 28
  [8, 10)     | 61       | 9                 52
  [10, 12)    | 25       | 1                 24
  [12, 14)    | 14       | 1                 13
  [14, 16)    | 22       | 2                 20
  [16, Inf)   | 79       | 9                 70
--------------------------------------------------------------
  The maximum fanout: 1266
==============================================================

Flip-Flop Distribution:
************************************************************************
  Clock Enable    Sync Set/Reset    Async Set/Reset    Total Registers
------------------------------------------------------------------------
  NO              NO                NO                 141
  NO              NO                YES                4038
  NO              YES               NO                 88
  YES             NO                NO                 8
  YES             NO                YES                4149
  YES             YES               NO                 172
========================================================================

Latch Distribution:
************************************************
  Gate Enable    Preset/Clear    Total Latches
************************************************
  NO             NO              0
  NO             YES             0
  YES            NO              0
  YES            YES             0
************************************************

View the details of control sets in the file pcie_dma_test_controlsets.txt.


Device Utilization Summary Of Each Module:
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module Inst Name                                               | LUT      | FF       | Distributed RAM     | APM     | DRM      | ADC     | ANALOG     | CCS     | DDRPHY_CPD     | DDRPHY_IOCLK_DIV     | DDR_PHY     | GCLK_INBUF_SYN     | GPLL     | HCKB     | HSSTLP     | IO     | IOCKB     | KEYRAM     | LUT CARRY     | LUT6 MUX     | LUT7 MUX     | LUT8 MUX     | MRCKB     | PCIEGEN3     | PPLL     | RCKB     | RESCAL     | SCANCHAIN     | USCM     
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| pcie_dma_test                                                  | 7475     | 8596     | 618                 | 0       | 49.5     | 0       | 0          | 1       | 1              | 2                    | 7           | 0                  | 3        | 0        | 0.5        | 86     | 0         | 0          | 1116          | 0            | 26           | 3            | 1         | 0            | 2        | 2        | 0          | 0             | 3        
| + cmos1_8_16bit                                                | 7        | 83       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 2             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + cmos2_8_16bit                                                | 7        | 83       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 2             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + coms1_reg_config                                             | 47       | 35       | 0                   | 0       | 0.5      | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 10            | 0            | 2            | 1            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u1                                                         | 19       | 9        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 2            | 1            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + coms2_reg_config                                             | 32       | 23       | 0                   | 0       | 0.5      | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 2            | 1            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u1                                                         | 20       | 9        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 2            | 1            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + i2cSlave_u                                                   | 85       | 123      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u_registerInterface                                        | 17       | 24       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u_serialInterface                                          | 58       | 58       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + power_on_delay_inst                                          | 41       | 37       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 35            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + u_PLL                                                        | 0        | 0        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 1        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + u_SXT1_FIFO_to_DDR                                           | 92       | 112      | 0                   | 0       | 4        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 56            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + U_ipm2l_fifo_SXT1_FIFO                                     | 92       | 112      | 0                   | 0       | 4        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 56            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + U_ipm2l_fifo_ctrl                                        | 92       | 112      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 56            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + U_ipm2l_sdpram                                           | 0        | 0        | 0                   | 0       | 4        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + u_SXT1_FIFO_to_PCIe                                          | 93       | 110      | 0                   | 0       | 4        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 58            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + U_ipm2l_fifo_SXT1_FIFO                                     | 93       | 110      | 0                   | 0       | 4        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 58            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + U_ipm2l_fifo_ctrl                                        | 93       | 110      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 58            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + U_ipm2l_sdpram                                           | 0        | 0        | 0                   | 0       | 4        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + u_ddr3                                                       | 3119     | 3395     | 40                  | 0       | 0        | 0       | 0          | 0       | 1              | 2                    | 7           | 0                  | 2        | 0        | 0          | 48     | 0         | 0          | 353           | 0            | 22           | 1            | 1         | 0            | 2        | 2        | 0          | 0             | 2        
|   + u_ddrc_rstn_sync                                           | 1        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u_ddrphy_top                                               | 2082     | 1956     | 0                   | 0       | 0        | 0       | 0          | 0       | 1              | 2                    | 7           | 0                  | 2        | 0        | 0          | 48     | 0         | 0          | 276           | 0            | 0            | 0            | 1         | 0            | 2        | 2        | 0          | 0             | 2        
|     + ddrphy_calib_top                                         | 383      | 377      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 64            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ddrphy_calib_mux                                       | 33       | 23       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ddrphy_eyecal                                          | 38       | 33       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ddrphy_init                                            | 117      | 100      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 47            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ddrphy_main_ctrl                                       | 11       | 12       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ddrphy_rdcal                                           | 99       | 70       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ddrphy_wrcal                                           | 50       | 100      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 17            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ddrphy_wrlvl                                           | 33       | 38       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + ddrphy_cpd_ctrl                                          | 41       | 51       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 9             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + ddrphy_dfi                                               | 275      | 179      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 2             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + ddrphy_dll_update_ctrl                                   | 26       | 32       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 20            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + ddrphy_gpll                                              | 0        | 0        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 1        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + ddrphy_info                                              | 58       | 60       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + ddrphy_reset_ctrl                                        | 69       | 82       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 22            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ddrphy_pll_lock_debounce                               | 36       | 22       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 20            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + u_ddrphy_rstn_sync                                     | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + u_dll_rst_sync                                         | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + ddrphy_slice_top                                         | 1197     | 1119     | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 2                    | 7           | 0                  | 0        | 0        | 0          | 48     | 0         | 0          | 150           | 0            | 0            | 0            | 0         | 0            | 2        | 2        | 0          | 0             | 0        
|       + ddrphy_control_path_adj                                | 49       | 20       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ddrphy_slice_rddata_align                              | 1        | 130      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + i_dqs_bank[0].ddrphy_ppll                              | 0        | 0        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 1        | 0        | 0          | 0             | 0        
|       + i_dqs_bank[1].ddrphy_ppll                              | 0        | 0        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 1        | 0        | 0          | 0             | 0        
|       + i_dqs_group[0].ddrphy_data_slice                       | 556      | 495      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 2           | 0                  | 0        | 0        | 0          | 11     | 0         | 0          | 70            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_data_slice_dqs_gate_cal                       | 73       | 63       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 12            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + ddrphy_dqs_gate_coarse_cal                         | 30       | 34       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + ddrphy_gatecal                                     | 43       | 29       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 12            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_data_slice_wrcal                              | 72       | 82       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 18            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_data_slice_wrlvl                              | 49       | 52       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_dqs_rddata_align                              | 99       | 111      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_dqsi_rdel_cal                                 | 177      | 124      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 40            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_wdata_path_adj                                | 84       | 63       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + i_dqs_group[1].ddrphy_data_slice                       | 584      | 473      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 2           | 0                  | 0        | 0        | 0          | 11     | 0         | 0          | 80            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_data_slice_dqs_gate_cal                       | 108      | 55       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 22            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + ddrphy_dqs_gate_coarse_cal                         | 60       | 26       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + ddrphy_gatecal                                     | 48       | 29       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 22            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_data_slice_wrcal                              | 71       | 81       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 18            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_data_slice_wrlvl                              | 49       | 52       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_dqs_rddata_align                              | 99       | 108      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_dqsi_rdel_cal                                 | 171      | 121      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 40            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ddrphy_wdata_path_adj                                | 84       | 56       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + ddrphy_training_ctrl                                     | 4        | 8        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + rst_clk_gpll                                             | 0        | 0        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 1        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_ddrphy_cpd_rstn_sync                                   | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_ddrphy_rst_seq_rstn_sync                               | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_dll_freeze_sync                                        | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_dll_update_n_sync                                      | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_ips2l_ddrphy_cpd_lock                                  | 4        | 8        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_ips2l_ddrphy_rst_clk_phase_adj                         | 24       | 32       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 9             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u_ips_ddrc_top                                             | 1036     | 1437     | 40                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 77            | 0            | 22           | 1            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + mcdq_apb_cross_v1_2                                      | 0        | 0        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + mcdq_calib_delay                                         | 0        | 44       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + mcdq_cfg_apb                                             | 0        | 1        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + mcdq_dcd_top                                             | 128      | 145      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 12            | 0            | 2            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + mcdq_dcd_bm                                            | 92       | 75       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 12            | 0            | 1            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + mcdq_dcd_rowaddr                                     | 13       | 8        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 1            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + mcdq_dcd_sm                                            | 36       | 70       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 1            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + mcdq_dcp_top                                             | 549      | 577      | 38                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 28            | 0            | 5            | 1            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + mcdq_dcp_back_ctrl                                     | 359      | 382      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 5            | 1            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + PRE_PASS_LOOP[0].timing_pre_pass                     | 15       | 12       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + PRE_PASS_LOOP[1].timing_pre_pass                     | 15       | 12       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + PRE_PASS_LOOP[2].timing_pre_pass                     | 15       | 12       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + PRE_PASS_LOOP[3].timing_pre_pass                     | 15       | 12       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + PRE_PASS_LOOP[4].timing_pre_pass                     | 15       | 12       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + PRE_PASS_LOOP[5].timing_pre_pass                     | 15       | 12       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + PRE_PASS_LOOP[6].timing_pre_pass                     | 15       | 12       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + PRE_PASS_LOOP[7].timing_pre_pass                     | 14       | 12       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRC_LOOP[0].trc_timing                               | 3        | 4        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRC_LOOP[1].trc_timing                               | 3        | 4        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRC_LOOP[2].trc_timing                               | 3        | 4        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRC_LOOP[3].trc_timing                               | 3        | 4        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRC_LOOP[4].trc_timing                               | 3        | 4        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRC_LOOP[5].trc_timing                               | 3        | 4        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRC_LOOP[6].trc_timing                               | 3        | 4        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRC_LOOP[7].trc_timing                               | 3        | 4        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRDA2ACT_LOOP[0].trda2act_timing                     | 5        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRDA2ACT_LOOP[1].trda2act_timing                     | 5        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRDA2ACT_LOOP[2].trda2act_timing                     | 5        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRDA2ACT_LOOP[3].trda2act_timing                     | 5        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRDA2ACT_LOOP[4].trda2act_timing                     | 5        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRDA2ACT_LOOP[5].trda2act_timing                     | 5        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRDA2ACT_LOOP[6].trda2act_timing                     | 5        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TRDA2ACT_LOOP[7].trda2act_timing                     | 5        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TWRA2ACT_LOOP[0].twra2act_timing                     | 6        | 6        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TWRA2ACT_LOOP[1].twra2act_timing                     | 5        | 6        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TWRA2ACT_LOOP[2].twra2act_timing                     | 5        | 6        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TWRA2ACT_LOOP[3].twra2act_timing                     | 5        | 6        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TWRA2ACT_LOOP[4].twra2act_timing                     | 6        | 6        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TWRA2ACT_LOOP[5].twra2act_timing                     | 5        | 6        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TWRA2ACT_LOOP[6].twra2act_timing                     | 6        | 6        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + TWRA2ACT_LOOP[7].twra2act_timing                     | 6        | 6        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + mcdq_timing_rd_pass                                  | 8        | 7        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + tfaw_timing                                          | 17       | 18       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + TFAW_LOOP[0].mcdq_tfaw                             | 4        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + TFAW_LOOP[1].mcdq_tfaw                             | 5        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + TFAW_LOOP[2].mcdq_tfaw                             | 5        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + timing_act_pass                                      | 19       | 8        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + timing_prea_pass                                     | 9        | 11       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + timing_ref_pass                                      | 15       | 7        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + timing_wr_pass                                       | 5        | 5        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + mcdq_dcp_buf                                           | 159      | 144      | 38                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 28            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + A_ips2l_distributed_fifo                             | 51       | 15       | 19                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 14            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + u_ips2l_distributed_fifo_distributed_fifo_v1_0     | 51       | 15       | 19                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 14            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + ips2l_distributed_sdpram_distributed_fifo_v1_0   | 19       | 0        | 19                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + u_ips2l_distributed_fifo_ctr                     | 31       | 15       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 14            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + B_ips2l_distributed_fifo                             | 51       | 15       | 19                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 14            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + u_ips2l_distributed_fifo_distributed_fifo_v1_0     | 51       | 15       | 19                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 14            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + ips2l_distributed_sdpram_distributed_fifo_v1_0   | 19       | 0        | 19                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + u_ips2l_distributed_fifo_ctr                     | 31       | 15       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 14            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + mcdq_dcp_out                                           | 31       | 51       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + mcdq_dfi                                                 | 47       | 85       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + mcdq_rdatapath                                           | 29       | 18       | 1                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 3             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + mcdq_prefetch_fifo                                     | 28       | 18       | 1                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 3             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ips2l_distributed_fifo                               | 26       | 16       | 1                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 3             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + u_ips2l_distributed_fifo_distributed_fifo_v1_0     | 26       | 16       | 1                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 3             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + ips2l_distributed_sdpram_distributed_fifo_v1_0   | 1        | 0        | 1                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + u_ips2l_distributed_fifo_ctr                     | 25       | 16       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 3             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + mcdq_ui_axi                                              | 136      | 313      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 34            | 0            | 15           | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + mcdq_reg_fifo2                                         | 7        | 59       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + u_user_cmd_fifo                                        | 13       | 98       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + mcdq_wdatapath                                           | 147      | 254      | 1                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ips_distributed_fifo                                   | 16       | 14       | 1                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + u_ips2l_distributed_fifo_distributed_fifo_v1_0       | 16       | 14       | 1                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + ips2l_distributed_sdpram_distributed_fifo_v1_0     | 1        | 0        | 1                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + u_ips2l_distributed_fifo_ctr                       | 15       | 14       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + mc3q_wdp_dcp                                           | 0        | 4        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + mcdq_wdp_align                                         | 130      | 232      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + u_ips2l_pcie_dma                                             | 2909     | 3159     | 574                 | 0       | 32       | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 331           | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u_ips2l_pcie_dma_controller                                | 40       | 191      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 20            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u_ips2l_pcie_dma_rx_top                                    | 881      | 1488     | 8                   | 0       | 32       | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 40            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + ips2l_pcie_dma_bar0                                      | 132      | 2        | 0                   | 0       | 16       | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + U_ipm2l_sdpram_ips2l_pcie_dma_ram                      | 132      | 2        | 0                   | 0       | 16       | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + ips2l_pcie_dma_bar2                                      | 132      | 2        | 0                   | 0       | 16       | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + U_ipm2l_sdpram_ips2l_pcie_dma_ram                      | 132      | 2        | 0                   | 0       | 16       | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_cpld_wr_ctrl                                           | 226      | 482      | 8                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 30            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ips2l_pcie_dma_cpld_wr_ctrl                            | 195      | 451      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 22            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + u_ipm_distributed_sdpram_v1_2                          | 8        | 8        | 8                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_ips2l_pcie_dma_tlp_rcv                                 | 165      | 625      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_mwr_wr_ctrl                                            | 145      | 377      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 10            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + ips2l_pcie_dma_mwr_wr_ctrl                             | 145      | 377      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 10            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u_ips2l_pcie_dma_tx_top                                    | 1988     | 1480     | 566                 | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 271           | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_ips2l_pcie_dma_cpld_tx_ctrl                            | 249      | 275      | 54                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 55            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + u_cpld_req_fifo                                        | 73       | 75       | 54                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + genblk1.pgs_pciex4_fifo                              | 71       | 20       | 54                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + ipm_distributed_sdpram_distributed_fifo            | 54       | 0        | 54                  | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + pgs_pciex4_fifo_ctrl                               | 17       | 20       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_ips2l_pcie_dma_mrd_tx_ctrl                             | 324      | 256      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 77            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_ips2l_pcie_dma_mwr_tx_ctrl                             | 245      | 219      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 73            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_ips2l_pcie_dma_tx_cpld_rd_ctrl                         | 566      | 349      | 256                 | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 28            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + u_ips2l_pcie_dma_cpld_rd_ctrl                          | 566      | 349      | 256                 | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 28            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + u_mwr_data_rd_fifo                                   | 341      | 152      | 256                 | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + genblk1.pgs_pciex4_fifo                            | 340      | 23       | 256                 | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + ipm_distributed_sdpram_distributed_fifo          | 321      | 0        | 256                 | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + pgs_pciex4_fifo_ctrl                             | 19       | 23       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_ips2l_pcie_dma_tx_mwr_rd_ctrl                          | 604      | 381      | 256                 | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 38            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + u_ips2l_pcie_dma_mwr_rd_ctrl                           | 575      | 349      | 256                 | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 26            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + u_mwr_data_rd_fifo                                   | 346      | 152      | 256                 | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + genblk1.pgs_pciex4_fifo                            | 344      | 23       | 256                 | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + ipm_distributed_sdpram_distributed_fifo          | 321      | 0        | 256                 | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + pgs_pciex4_fifo_ctrl                             | 23       | 23       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + u_ips2l_pcie_expd_apb_mux                                    | 11       | 23       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 2             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u_pcie_expd_apb_cross                                      | 5        | 23       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + u_ips2l_pcie_wrap                                            | 602      | 714      | 0                   | 0       | 8.5      | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0.5        | 0      | 0         | 0          | 84            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 1        
|   + U_IPS2L_PCIE_TOP                                           | 602      | 714      | 0                   | 0       | 8.5      | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0.5        | 0      | 0         | 0          | 84            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 1        
|     + U_IPS2L_HSSTLP_PCIE_SOFT_PHY                             | 495      | 450      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0.5        | 0      | 0         | 0          | 84            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 1        
|       + button_rstn_sync                                       | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + genblk5.rdata_proc_1                                   | 25       | 39       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + hsst_ch_ready_sync[0].hsst_pciex4_sync_hsst_ch_ready   | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + hsst_ch_ready_sync[1].hsst_pciex4_sync_hsst_ch_ready   | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + hsst_pciex4_rst                                        | 331      | 250      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 84            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + ext_rstn_debounce                                    | 22       | 24       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 15            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + hsst_rx_rst_mcrsw                                    | 195      | 148      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 25            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + genblk1[0].hsst_rst4mcrsw_rx_init                  | 42       | 37       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + cdr_align_multi_sw_sync                          | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + loss_signal_multi_sw_sync                        | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + rx_rst_initfsm_multi_sw_lane                     | 42       | 31       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + word_align_multi_sw_sync                         | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + genblk1[1].hsst_rst4mcrsw_rx_init                  | 41       | 37       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + cdr_align_multi_sw_sync                          | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + loss_signal_multi_sw_sync                        | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + rx_rst_initfsm_multi_sw_lane                     | 41       | 31       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + word_align_multi_sw_sync                         | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + genblk1[2].hsst_rst4mcrsw_rx_init                  | 11       | 14       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + loss_signal_multi_sw_sync                        | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + rx_rst_initfsm_multi_sw_lane                     | 11       | 12       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + genblk1[3].hsst_rst4mcrsw_rx_init                  | 10       | 11       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|             + rx_rst_initfsm_multi_sw_lane                     | 10       | 11       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + rx_rst_fsm_multi_sw_lane                           | 84       | 49       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 25            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + hsst_tx_rst_mcrsw                                    | 114      | 76       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 44            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + pll_lock_multi_sw_deb                              | 22       | 15       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 11            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + pll_lock_multi_sw_sync                             | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + pll_lock_multi_sw_wtchdg                           | 21       | 21       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 18            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + tx_rst_fsm_multi_sw_lane                           | 71       | 38       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 15            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + rate_multi_sw_sync                                   | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + hsst_pciex4_sync_rate_done                             | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + phy_rstn_sync                                          | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + rdata_proc_0                                           | 25       | 39       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + x2.GTP_HSST_2LANE_TOP                                  | 6        | 0        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0.5        | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + U_GTP_HSSTLP_WRAPPER                                 | 6        | 0        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0.5        | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + U_APB_BRIDGE                                       | 6        | 0        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + U_IPS2L_PCIE_HARD_CTRL                                   | 52       | 149      | 0                   | 0       | 8.5      | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + U_APB2DBI                                              | 6        | 50       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + U_IPS2L_PCIE_CFG_SPACE_INIT                            | 16       | 16       | 0                   | 0       | 0.5      | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + mem_button_rstn_sync                                   | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + pcie2_iip_exrcvdata_rams                               | 0        | 0        | 0                   | 0       | 2        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + U_ipm2l_sdpram_rcv_data_ram                          | 0        | 0        | 0                   | 0       | 2        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + pcie2_iip_exrcvhdr_rams                                | 0        | 0        | 0                   | 0       | 2        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + U_ipm2l_sdpram_rcv_header_ram                        | 0        | 0        | 0                   | 0       | 2        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + pcie2_iip_exretry_rams                                 | 0        | 0        | 0                   | 0       | 4        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + U_ipml_spram_retry_data_ram                          | 0        | 0        | 0                   | 0       | 4        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + tx_rst_done_sync                                       | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + u_pcie_seio                                            | 4        | 8        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_core_rstn_sync                                         | 0        | 2        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_pcie_apb_mux                                           | 54       | 113      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + u_pcie_apb_cross                                       | 5        | 113      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + u_refclk_buttonrstn_debounce                                 | 21       | 24       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 15            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + u_refclk_perstn_debounce                                     | 21       | 24       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 15            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + u_rgb565_to_rgb888                                           | 8        | 0        | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
| + u_uart2apb_top                                               | 80       | 193      | 4                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 17            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u_apb_ctr                                                  | 26       | 129      | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 2             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_apb_mif                                                | 10       | 63       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_cmd_parser                                             | 16       | 66       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 2             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|   + u_uart_top                                                 | 54       | 64       | 4                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 15            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_pgr_clk_gen                                            | 20       | 17       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 15            | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_pgr_uart_rx                                            | 12       | 24       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|     + u_rx_fifo                                                | 22       | 23       | 4                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|       + FIFO_PG30.u_prefetch_fifo                              | 22       | 23       | 4                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|         + pgm_distributed_fifo_v1_0                            | 20       | 14       | 4                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + pgm_distributed_sdpram                             | 4        | 0        | 4                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
|           + u_pgm_distributed_fifo_ctr_v1_0                    | 16       | 14       | 0                   | 0       | 0        | 0       | 0          | 0       | 0              | 0                    | 0           | 0                  | 0        | 0        | 0          | 0      | 0         | 0          | 0             | 0            | 0            | 0            | 0         | 0            | 0        | 0        | 0          | 0             | 0        
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


Timing analysis mode : single corner

 Clock Summary:                                                                                                                                                                                                                                                                        
***************************************************************************************************************************************************************************************************************************************************************************************
                                                                                                      Clock   Non-clock                                                                                                                                                                
 Clock                                    Period       Waveform            Type                       Loads       Loads  Sources                                                                                                                                                       
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 pclk                                     4.0000       {0.0000 2.0000}     Declared                     137           3  {u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC} 
 pclk_div2                                8.0000       {0.0000 4.0000}     Declared                    3705           0  {u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC} 
 ref_clk                                  10.0000      {0.0000 5.0000}     Declared                     594           0  {u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT}                                                                            
 sys_clk                                  40.0000      {0.0000 20.0000}    Declared                      12           6  {sys_clk}                                                                                                                                                     
   rst_clk                                40.0000      {0.0000 20.0000}    Generated (sys_clk)          164           0  {u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0}                                                                                                             
   ddrphy_sysclk                          7.6190       {0.0000 3.8090}     Generated (sys_clk)         3471           1  {u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0}                                                                                                              
   phy_dq_clk_0                           0.9524       {0.0000 0.4760}     Generated (sys_clk)           35           1  {u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY}                                                                             
     phy_dq_sysclk_0                      7.6190       {1.9040 5.7140}     Generated (phy_dq_clk_0)      35           0  {u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT}                                                                              
   phy_dq_clk_1                           0.9524       {0.0000 0.4760}     Generated (sys_clk)           42           3  {u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/CLKOUTPHY}                                                                             
     phy_dq_sysclk_1                      7.6190       {1.9040 5.7140}     Generated (phy_dq_clk_1)      44           0  {u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT}                                                                              
   sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred  20.0000      {0.0000 10.0000}    Generated (sys_clk)           37           0  {u_PLL/u_gpll/CLKOUT1}                                                                                                                                        
   sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred  10.0000      {0.0000 5.0000}     Generated (sys_clk)          396           0  {u_PLL/u_gpll/CLKOUT0}                                                                                                                                        
 cmos1_pclk                               23.8100      {0.0000 11.9050}    Declared                      42           1  {cmos1_pclk}                                                                                                                                                  
   cmos1_pclk_16bit                       47.6200      {0.0000 23.8100}    Generated (cmos1_pclk)       222           1  {cmos1_8_16bit/pclk_div2/Q}                                                                                                                                   
 cmos2_pclk                               23.8100      {0.0000 11.9050}    Declared                       0           0  {cmos2_pclk}                                                                                                                                                  
   cmos2_pclk_16bit                       47.6200      {0.0000 23.8100}    Generated (cmos2_pclk)         0           0  {}                                                                                                                                                            
=======================================================================================================================================================================================================================================================================================

 Clock Groups:                                                                                      
****************************************************************************************************
 Clock Group                   Group Type                 Clocks                                    
----------------------------------------------------------------------------------------------------
 group_1                       asynchronous               pclk                                      
 group_2                       asynchronous               pclk_div2                                 
 group_3                       asynchronous               ref_clk                                   
 rst_clk                       asynchronous               rst_clk                                   
 phy_dq_clk_0                  asynchronous               phy_dq_clk_0                              
 phy_dq_clk_1                  asynchronous               phy_dq_clk_1                              
 ddrphy_sysclk                 asynchronous               ddrphy_sysclk                             
 cmos1_pclk                    asynchronous               cmos1_pclk                                
 cmos1_pclk_16bit              asynchronous               cmos1_pclk_16bit                          
 cmos2_pclk                    asynchronous               cmos2_pclk                                
 cmos2_pclk_16bit              asynchronous               cmos2_pclk_16bit                          
====================================================================================================

 Performance Summary:                                                                               
****************************************************************************************************
                              Requested       Estimated      Requested      Estimated               
 Clock                        Frequency       Frequency      Period         Period             Slack
----------------------------------------------------------------------------------------------------
 pclk                      250.0000 MHz    322.1649 MHz         4.0000         3.1040          0.896
 pclk_div2                 125.0000 MHz    132.2052 MHz         8.0000         7.5640          0.436
 ref_clk                   100.0000 MHz    244.3793 MHz        10.0000         4.0920          5.908
 sys_clk                    25.0000 MHz    388.1988 MHz        40.0000         2.5760         37.424
 cmos1_pclk                 41.9992 MHz    546.4481 MHz        23.8100         1.8300         21.980
 rst_clk                    25.0000 MHz    360.6203 MHz        40.0000         2.7730         37.227
 ddrphy_sysclk             131.2500 MHz    176.6773 MHz         7.6190         5.6600          1.959
 cmos1_pclk_16bit           20.9996 MHz    289.6032 MHz        47.6200         3.4530         44.167
 sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
                            50.0000 MHz    437.0629 MHz        20.0000         2.2880         17.712
 sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred
                           100.0000 MHz    239.6932 MHz        10.0000         4.1720          5.828
====================================================================================================

Design Summary : Some Constraints Violated.

Setup Summary(Slow Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 pclk                   pclk                         0.896       0.000              0           1052
 pclk_div2              pclk_div2                    0.436       0.000              0          11757
 ref_clk                ref_clk                      5.908       0.000              0            982
 sys_clk                sys_clk                     37.424       0.000              0             12
 sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
                        sys_clk                     16.654       0.000              0             12
 cmos1_pclk             cmos1_pclk                  21.980       0.000              0             60
 rst_clk                rst_clk                     37.227       0.000              0            225
 ddrphy_sysclk          ddrphy_sysclk                1.959       0.000              0           5071
 cmos1_pclk_16bit       cmos1_pclk_16bit            44.167       0.000              0            448
 sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
                        sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
                                                    17.712       0.000              0             89
 sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred
                        sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred
                                                     5.828       0.000              0           1684
====================================================================================================

Hold Summary(Slow Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 pclk                   pclk                         0.619       0.000              0           1052
 pclk_div2              pclk_div2                    0.324       0.000              0          11757
 ref_clk                ref_clk                      0.324       0.000              0            982
 sys_clk                sys_clk                      0.770       0.000              0             12
 sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
                        sys_clk                      2.994       0.000              0             12
 cmos1_pclk             cmos1_pclk                   0.419       0.000              0             60
 rst_clk                rst_clk                      0.507       0.000              0            225
 ddrphy_sysclk          ddrphy_sysclk               -0.004      -0.012              3           5071
 cmos1_pclk_16bit       cmos1_pclk_16bit             0.419       0.000              0            448
 sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
                        sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
                                                     0.706       0.000              0             89
 sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred
                        sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred
                                                     0.619       0.000              0           1684
====================================================================================================

Recovery Summary(Slow Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 pclk                   pclk                         1.993       0.000              0            129
 pclk_div2              pclk_div2                    3.610       0.000              0           3124
 ref_clk                ref_clk                      8.061       0.000              0            579
 cmos1_pclk             cmos1_pclk                  25.297       0.000              0              1
 rst_clk                rst_clk                     38.816       0.000              0            161
 ddrphy_sysclk          ddrphy_sysclk                4.283       0.000              0           3386
 cmos1_pclk_16bit       cmos1_pclk_16bit            45.465       0.000              0             49
====================================================================================================

Removal Summary(Slow Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 pclk                   pclk                         0.893       0.000              0            129
 pclk_div2              pclk_div2                    3.283       0.000              0           3124
 ref_clk                ref_clk                      0.652       0.000              0            579
 cmos1_pclk             cmos1_pclk                  -2.081      -2.081              1              1
 rst_clk                rst_clk                      0.864       0.000              0            161
 ddrphy_sysclk          ddrphy_sysclk                0.376       0.000              0           3386
 cmos1_pclk_16bit       cmos1_pclk_16bit             0.641       0.000              0             49
====================================================================================================

Minimum Pulse Width Summary(Slow Corner):
****************************************************************************************************
                                                                         WPWS Failing     WPWS Total
 Clock                                            WPWS(ns)    TPWS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 pclk                                                1.040       0.000              0            133
 pclk_div2                                           3.040       0.000              0           3700
 ref_clk                                             4.800       0.000              0            591
 sys_clk                                            19.800       0.000              0             12
 cmos1_pclk                                         11.705       0.000              0             42
 rst_clk                                            19.800       0.000              0            163
 ddrphy_sysclk                                       2.849       0.000              0           3470
 phy_dq_clk_0                                        0.011       0.000              0             35
 phy_dq_sysclk_0                                     1.659       0.000              0             35
 phy_dq_clk_1                                        0.011       0.000              0             42
 phy_dq_sysclk_1                                     2.209       0.000              0             44
 cmos1_pclk_16bit                                   22.850       0.000              0            222
 sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred               9.800       0.000              0             37
 sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred               4.040       0.000              0            396
====================================================================================================

Setup Summary(Fast Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
====================================================================================================

Hold Summary(Fast Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
====================================================================================================

Recovery Summary(Fast Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
====================================================================================================

Removal Summary(Fast Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
====================================================================================================

Minimum Pulse Width Summary(Fast Corner):
****************************************************************************************************
                                                                         WPWS Failing     WPWS Total
 Clock                                            WPWS(ns)    TPWS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
====================================================================================================

default
****************************************************************************************************
====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/MEM_CLK (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_data_in_r[0]/D (GTP_DFF_C)
Path Group  : pclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/MEM_CLK (GTP_PCIEGEN2)

                                   tco                   0.856       4.156 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/P_HDRQ_DATAIN[0] (GTP_PCIEGEN2)
                                   net (fanout=3)        2.062       6.218         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_datain [0]
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_data_in_r[0]/D (GTP_DFF_C)

 Data arrival time                                                   6.218         Logic Levels: 0  
                                                                                   Logic: 0.856ns(29.335%), Route: 2.062ns(70.665%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                4.000       4.000 r                        
                                                         0.000       4.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       7.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_data_in_r[0]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000       7.300                          
 clock uncertainty                                      -0.050       7.250                          

 Setup time                                             -0.136       7.114                          

 Data required time                                                  7.114                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  7.114                          
 Data arrival time                                                   6.218                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.896                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/MEM_CLK (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_data_in_r[1]/D (GTP_DFF_C)
Path Group  : pclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/MEM_CLK (GTP_PCIEGEN2)

                                   tco                   0.856       4.156 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/P_HDRQ_DATAIN[1] (GTP_PCIEGEN2)
                                   net (fanout=3)        2.062       6.218         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_datain [1]
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_data_in_r[1]/D (GTP_DFF_C)

 Data arrival time                                                   6.218         Logic Levels: 0  
                                                                                   Logic: 0.856ns(29.335%), Route: 2.062ns(70.665%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                4.000       4.000 r                        
                                                         0.000       4.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       7.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_data_in_r[1]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000       7.300                          
 clock uncertainty                                      -0.050       7.250                          

 Setup time                                             -0.136       7.114                          

 Data required time                                                  7.114                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  7.114                          
 Data arrival time                                                   6.218                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.896                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/MEM_CLK (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_data_in_r[2]/D (GTP_DFF_C)
Path Group  : pclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/MEM_CLK (GTP_PCIEGEN2)

                                   tco                   0.856       4.156 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/P_HDRQ_DATAIN[2] (GTP_PCIEGEN2)
                                   net (fanout=3)        2.062       6.218         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_datain [2]
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_data_in_r[2]/D (GTP_DFF_C)

 Data arrival time                                                   6.218         Logic Levels: 0  
                                                                                   Logic: 0.856ns(29.335%), Route: 2.062ns(70.665%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                4.000       4.000 r                        
                                                         0.000       4.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       7.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/p_hdrq_data_in_r[2]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000       7.300                          
 clock uncertainty                                      -0.050       7.250                          

 Setup time                                             -0.136       7.114                          

 Data required time                                                  7.114                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  7.114                          
 Data arrival time                                                   6.218                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.896                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem_r1/CLK (GTP_DFF_C)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/D (GTP_DFF_C)
Path Group  : pclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem_r1/CLK (GTP_DFF_C)

                                   tco                   0.185       3.485 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem_r1/Q (GTP_DFF_C)
                                   net (fanout=1)        0.385       3.870         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem_r1
                                                                           f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/D (GTP_DFF_C)

 Data arrival time                                                   3.870         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/CLK (GTP_DFF_C)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Hold time                                              -0.049       3.251                          

 Data required time                                                  3.251                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.251                          
 Data arrival time                                                   3.870                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.619                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_async_ff/CLK (GTP_DFF_C)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/D (GTP_DFF_C)
Path Group  : pclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_async_ff/CLK (GTP_DFF_C)

                                   tco                   0.185       3.485 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_async_ff/Q (GTP_DFF_C)
                                   net (fanout=1)        0.385       3.870         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_async_ff
                                                                           f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/D (GTP_DFF_C)

 Data arrival time                                                   3.870         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/CLK (GTP_DFF_C)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Hold time                                              -0.049       3.251                          

 Data required time                                                  3.251                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.251                          
 Data arrival time                                                   3.870                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.619                          
====================================================================================================

====================================================================================================

Startpoint  : pclk_led_cnt[3]/CLK (GTP_DFF_CE)
Endpoint    : pclk_led_cnt[3]/D (GTP_DFF_CE)
Path Group  : pclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       pclk_led_cnt[3]/CLK (GTP_DFF_CE)

                                   tco                   0.185       3.485 f       pclk_led_cnt[3]/Q (GTP_DFF_CE)
                                   net (fanout=2)        0.437       3.922         pclk_led_cnt[3]  
                                                                                   N460_0_3/I0 (GTP_LUT6CARRY)
                                   td                    0.096       4.018 r       N460_0_3/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       4.018         N460[3]          
                                                                           r       pclk_led_cnt[3]/D (GTP_DFF_CE)

 Data arrival time                                                   4.018         Logic Levels: 1  
                                                                                   Logic: 0.281ns(39.136%), Route: 0.437ns(60.864%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       pclk_led_cnt[3]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Hold time                                              -0.040       3.260                          

 Data required time                                                  3.260                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.260                          
 Data arrival time                                                   4.018                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.758                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/data_read_cnt[9]/D (GTP_DFF_CE)
Path Group  : pclk_div2
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)

                                   tco                   1.165       4.465 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/CFG_MAX_PAYLOAD_SIZE[0] (GTP_PCIEGEN2)
                                   net (fanout=15)       2.183       6.648         cfg_max_payload_size[0]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N216/I0 (GTP_LUT3)
                                   td                    0.210       6.858 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N216/Z (GTP_LUT3)
                                   net (fanout=15)       0.588       7.446         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/max_payload_size [5]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N369_4/I0 (GTP_LUT4)
                                   td                    0.183       7.629 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N369_4/Z (GTP_LUT4)
                                   net (fanout=9)        0.549       8.178         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/max_payload_size [2]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_0/I3 (GTP_LUT6CARRY)
                                   td                    0.159       8.337 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_0/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       8.337         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.co [2]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_2/CIN (GTP_LUT6CARRY)
                                   td                    0.022       8.359 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_2/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       8.359         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.co [4]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_3/CIN (GTP_LUT6CARRY)
                                   td                    0.022       8.381 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       8.381         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.co [6]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_4/CIN (GTP_LUT6CARRY)
                                   td                    0.022       8.403 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_4/COUT (GTP_LUT6CARRY)
                                   net (fanout=14)       0.582       8.985         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N93_6[0]/I0 (GTP_LUT6CARRY)
                                   td                    0.176       9.161 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N93_6[0]/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.161         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/cpld_rd_length[0]_co
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N93_6[0]_1/CIN (GTP_LUT6CARRY)
                                   td                    0.068       9.229 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N93_6[0]_1/Z (GTP_LUT6CARRY)
                                   net (fanout=2)        0.437       9.666         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/nb1 [0]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_1/I2 (GTP_LUT6CARRY)
                                   td                    0.159       9.825 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_1/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.825         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9424
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_2/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.847 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_2/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.847         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9425
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_3/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.869 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.869         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9426
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_4/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.891 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_4/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.891         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9427
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_5/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.913 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_5/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.913         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9428
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_6/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.935 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_6/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.935         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9429
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_7/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.957 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_7/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.957         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9430
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_8/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.979 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_8/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.979         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9431
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_9/CIN (GTP_LUT6CARRY)
                                   td                    0.022      10.001 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_9/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      10.001         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9432
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_10/CIN (GTP_LUT6CARRY)
                                   td                    0.068      10.069 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_10/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.385      10.454         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/nb0 [9]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_2[9]_1/I0 (GTP_LUT2)
                                   td                    0.224      10.678 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_2[9]_1/Z (GTP_LUT2)
                                   net (fanout=1)        0.000      10.678         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153 [9]
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/data_read_cnt[9]/D (GTP_DFF_CE)

 Data arrival time                                                  10.678         Logic Levels: 8  
                                                                                   Logic: 2.654ns(35.972%), Route: 4.724ns(64.028%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           8.000       8.000 r                        
                                                         0.000       8.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300      11.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/data_read_cnt[9]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      11.300                          
 clock uncertainty                                      -0.050      11.250                          

 Setup time                                             -0.136      11.114                          

 Data required time                                                 11.114                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.114                          
 Data arrival time                                                  10.678                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.436                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/data_read_cnt[9]/D (GTP_DFF_CE)
Path Group  : pclk_div2
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)

                                   tco                   1.165       4.465 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/CFG_MAX_PAYLOAD_SIZE[0] (GTP_PCIEGEN2)
                                   net (fanout=15)       2.183       6.648         cfg_max_payload_size[0]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N216/I0 (GTP_LUT3)
                                   td                    0.210       6.858 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N216/Z (GTP_LUT3)
                                   net (fanout=15)       0.588       7.446         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/max_payload_size [5]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N369_4/I0 (GTP_LUT4)
                                   td                    0.183       7.629 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N369_4/Z (GTP_LUT4)
                                   net (fanout=9)        0.549       8.178         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/max_payload_size [2]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29.lt_0/I3 (GTP_LUT6CARRY)
                                   td                    0.159       8.337 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29.lt_0/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       8.337         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29.co [2]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29.lt_2/CIN (GTP_LUT6CARRY)
                                   td                    0.022       8.359 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29.lt_2/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       8.359         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29.co [4]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29.lt_3/CIN (GTP_LUT6CARRY)
                                   td                    0.022       8.381 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29.lt_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       8.381         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29.co [6]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29.lt_4/CIN (GTP_LUT6CARRY)
                                   td                    0.022       8.403 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29.lt_4/COUT (GTP_LUT6CARRY)
                                   net (fanout=44)       0.670       9.073         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N29
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N52[5]/I1 (GTP_LUT3)
                                   td                    0.179       9.252 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/N52[5]/Z (GTP_LUT3)
                                   net (fanout=5)        0.505       9.757         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/mwr_rd_length [5]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_7_6/I2 (GTP_LUT6CARRY)
                                   td                    0.159       9.916 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_7_6/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.916         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/_N8554
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_7_7/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.938 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_7_7/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.938         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/_N8555
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_7_8/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.960 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_7_8/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.960         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/_N8556
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_7_9/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.982 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_7_9/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.982         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/_N8557
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_7_10/CIN (GTP_LUT6CARRY)
                                   td                    0.068      10.050 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_7_10/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.385      10.435         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/nb0 [9]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_2[9]_1/I0 (GTP_LUT2)
                                   td                    0.224      10.659 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153_2[9]_1/Z (GTP_LUT2)
                                   net (fanout=1)        0.000      10.659         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/N153 [9]
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/data_read_cnt[9]/D (GTP_DFF_CE)

 Data arrival time                                                  10.659         Logic Levels: 7  
                                                                                   Logic: 2.479ns(33.687%), Route: 4.880ns(66.313%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           8.000       8.000 r                        
                                                         0.000       8.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300      11.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_mwr_rd_ctrl/u_ips2l_pcie_dma_mwr_rd_ctrl/data_read_cnt[9]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      11.300                          
 clock uncertainty                                      -0.050      11.250                          

 Setup time                                             -0.136      11.114                          

 Data required time                                                 11.114                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.114                          
 Data arrival time                                                  10.659                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.455                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/data_read_cnt[8]/D (GTP_DFF_CE)
Path Group  : pclk_div2
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)

                                   tco                   1.165       4.465 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/CFG_MAX_PAYLOAD_SIZE[0] (GTP_PCIEGEN2)
                                   net (fanout=15)       2.183       6.648         cfg_max_payload_size[0]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N216/I0 (GTP_LUT3)
                                   td                    0.210       6.858 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N216/Z (GTP_LUT3)
                                   net (fanout=15)       0.588       7.446         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/max_payload_size [5]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N369_4/I0 (GTP_LUT4)
                                   td                    0.183       7.629 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N369_4/Z (GTP_LUT4)
                                   net (fanout=9)        0.549       8.178         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/max_payload_size [2]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_0/I3 (GTP_LUT6CARRY)
                                   td                    0.159       8.337 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_0/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       8.337         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.co [2]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_2/CIN (GTP_LUT6CARRY)
                                   td                    0.022       8.359 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_2/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       8.359         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.co [4]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_3/CIN (GTP_LUT6CARRY)
                                   td                    0.022       8.381 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       8.381         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.co [6]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_4/CIN (GTP_LUT6CARRY)
                                   td                    0.022       8.403 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83.lt_4/COUT (GTP_LUT6CARRY)
                                   net (fanout=14)       0.582       8.985         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N83
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N93_6[0]/I0 (GTP_LUT6CARRY)
                                   td                    0.176       9.161 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N93_6[0]/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.161         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/cpld_rd_length[0]_co
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N93_6[0]_1/CIN (GTP_LUT6CARRY)
                                   td                    0.068       9.229 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/N93_6[0]_1/Z (GTP_LUT6CARRY)
                                   net (fanout=2)        0.437       9.666         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/nb1 [0]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_1/I2 (GTP_LUT6CARRY)
                                   td                    0.159       9.825 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_1/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.825         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9424
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_2/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.847 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_2/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.847         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9425
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_3/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.869 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.869         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9426
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_4/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.891 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_4/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.891         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9427
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_5/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.913 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_5/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.913         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9428
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_6/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.935 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_6/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.935         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9429
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_7/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.957 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_7/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.957         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9430
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_8/CIN (GTP_LUT6CARRY)
                                   td                    0.022       9.979 f       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_8/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       9.979         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/_N9431
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_9/CIN (GTP_LUT6CARRY)
                                   td                    0.068      10.047 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_7_9/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.385      10.432         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/nb0 [8]
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_2[8]_1/I0 (GTP_LUT2)
                                   td                    0.224      10.656 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153_2[8]_1/Z (GTP_LUT2)
                                   net (fanout=1)        0.000      10.656         u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/N153 [8]
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/data_read_cnt[8]/D (GTP_DFF_CE)

 Data arrival time                                                  10.656         Logic Levels: 8  
                                                                                   Logic: 2.632ns(35.780%), Route: 4.724ns(64.220%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           8.000       8.000 r                        
                                                         0.000       8.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300      11.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_tx_cpld_rd_ctrl/u_ips2l_pcie_dma_cpld_rd_ctrl/data_read_cnt[8]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      11.300                          
 clock uncertainty                                      -0.050      11.250                          

 Setup time                                             -0.136      11.114                          

 Data required time                                                 11.114                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.114                          
 Data arrival time                                                  10.656                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.458                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next[2]/CLK (GTP_DFF_CE)
Endpoint    : u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/u_ipm_distributed_sdpram_v1_2/mem_2/DI (GTP_RAM64X1DP)
Path Group  : pclk_div2
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next[2]/CLK (GTP_DFF_CE)

                                   tco                   0.203       3.503 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next[2]/Q (GTP_DFF_CE)
                                   net (fanout=1)        0.385       3.888         u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next [2]
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/u_ipm_distributed_sdpram_v1_2/mem_2/DI (GTP_RAM64X1DP)

 Data arrival time                                                   3.888         Logic Levels: 0  
                                                                                   Logic: 0.203ns(34.524%), Route: 0.385ns(65.476%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/u_ipm_distributed_sdpram_v1_2/mem_2/WCLK (GTP_RAM64X1DP)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Hold time                                               0.264       3.564                          

 Data required time                                                  3.564                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.564                          
 Data arrival time                                                   3.888                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.324                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next[3]/CLK (GTP_DFF_CE)
Endpoint    : u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/u_ipm_distributed_sdpram_v1_2/mem_3/DI (GTP_RAM64X1DP)
Path Group  : pclk_div2
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next[3]/CLK (GTP_DFF_CE)

                                   tco                   0.203       3.503 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next[3]/Q (GTP_DFF_CE)
                                   net (fanout=1)        0.385       3.888         u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next [3]
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/u_ipm_distributed_sdpram_v1_2/mem_3/DI (GTP_RAM64X1DP)

 Data arrival time                                                   3.888         Logic Levels: 0  
                                                                                   Logic: 0.203ns(34.524%), Route: 0.385ns(65.476%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/u_ipm_distributed_sdpram_v1_2/mem_3/WCLK (GTP_RAM64X1DP)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Hold time                                               0.264       3.564                          

 Data required time                                                  3.564                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.564                          
 Data arrival time                                                   3.888                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.324                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next[4]/CLK (GTP_DFF_CE)
Endpoint    : u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/u_ipm_distributed_sdpram_v1_2/mem_4/DI (GTP_RAM64X1DP)
Path Group  : pclk_div2
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next[4]/CLK (GTP_DFF_CE)

                                   tco                   0.203       3.503 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next[4]/Q (GTP_DFF_CE)
                                   net (fanout=1)        0.385       3.888         u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/tag_addr_next [4]
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/u_ipm_distributed_sdpram_v1_2/mem_4/DI (GTP_RAM64X1DP)

 Data arrival time                                                   3.888         Logic Levels: 0  
                                                                                   Logic: 0.203ns(34.524%), Route: 0.385ns(65.476%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/u_ipm_distributed_sdpram_v1_2/mem_4/WCLK (GTP_RAM64X1DP)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Hold time                                               0.264       3.564                          

 Data required time                                                  3.564                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.564                          
 Data arrival time                                                   3.888                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.324                          
====================================================================================================

====================================================================================================

Startpoint  : u_uart2apb_top/u_apb_ctr/u_apb_mif/p_addr[12]/CLK (GTP_DFF_CE)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/PLL0_ENABLE.U_GTP_HSSTLP_PLL0/P_CFG_ENABLE_PLL (GTP_HSSTLP_PLL)
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_uart2apb_top/u_apb_ctr/u_apb_mif/p_addr[12]/CLK (GTP_DFF_CE)

                                   tco                   0.203       1.303 r       u_uart2apb_top/u_apb_ctr/u_apb_mif/p_addr[12]/Q (GTP_DFF_CE)
                                   net (fanout=58)       0.701       2.004         uart_p_addr[12]  
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/U_APB_BRIDGE/P_CFG_ENABLE_7/I1 (GTP_LUT6D)
                                   td                    0.280       2.284 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/U_APB_BRIDGE/P_CFG_ENABLE_7/Z5 (GTP_LUT6D)
                                   net (fanout=1)        1.980       4.264         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/P_CFG_ENABLE_PLL_0
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/PLL0_ENABLE.U_GTP_HSSTLP_PLL0/P_CFG_ENABLE_PLL (GTP_HSSTLP_PLL)

 Data arrival time                                                   4.264         Logic Levels: 1  
                                                                                   Logic: 0.483ns(15.265%), Route: 2.681ns(84.735%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            10.000      10.000 r                        
                                                         0.000      10.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100      11.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/PLL0_ENABLE.U_GTP_HSSTLP_PLL0/P_CFG_CLK_PLL (GTP_HSSTLP_PLL)
 clock pessimism                                         0.000      11.100                          
 clock uncertainty                                      -0.050      11.050                          

 Setup time                                             -0.878      10.172                          

 Data required time                                                 10.172                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.172                          
 Data arrival time                                                   4.264                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         5.908                          
====================================================================================================

====================================================================================================

Startpoint  : u_uart2apb_top/u_apb_ctr/u_apb_mif/p_addr[12]/CLK (GTP_DFF_CE)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/PLL0_ENABLE.U_GTP_HSSTLP_PLL0/P_CFG_PSEL_PLL (GTP_HSSTLP_PLL)
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_uart2apb_top/u_apb_ctr/u_apb_mif/p_addr[12]/CLK (GTP_DFF_CE)

                                   tco                   0.203       1.303 r       u_uart2apb_top/u_apb_ctr/u_apb_mif/p_addr[12]/Q (GTP_DFF_CE)
                                   net (fanout=58)       0.701       2.004         uart_p_addr[12]  
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/U_APB_BRIDGE/P_CFG_PSEL_7/I1 (GTP_LUT6D)
                                   td                    0.280       2.284 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/U_APB_BRIDGE/P_CFG_PSEL_7/Z5 (GTP_LUT6D)
                                   net (fanout=1)        1.980       4.264         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/P_CFG_PSEL_PLL_0
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/PLL0_ENABLE.U_GTP_HSSTLP_PLL0/P_CFG_PSEL_PLL (GTP_HSSTLP_PLL)

 Data arrival time                                                   4.264         Logic Levels: 1  
                                                                                   Logic: 0.483ns(15.265%), Route: 2.681ns(84.735%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            10.000      10.000 r                        
                                                         0.000      10.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100      11.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/PLL0_ENABLE.U_GTP_HSSTLP_PLL0/P_CFG_CLK_PLL (GTP_HSSTLP_PLL)
 clock pessimism                                         0.000      11.100                          
 clock uncertainty                                      -0.050      11.050                          

 Setup time                                             -0.871      10.179                          

 Data required time                                                 10.179                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.179                          
 Data arrival time                                                   4.264                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         5.915                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/cntr[1]/CLK (GTP_DFF_CE)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/cntr[3]/D (GTP_DFF_CE)
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/cntr[1]/CLK (GTP_DFF_CE)

                                   tco                   0.203       1.303 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/cntr[1]/Q (GTP_DFF_CE)
                                   net (fanout=9)        0.549       1.852         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/cntr [1]
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N282_2/I0 (GTP_LUT6CARRY)
                                   td                    0.150       2.002 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N282_2/Z (GTP_LUT6CARRY)
                                   net (fanout=14)       0.582       2.584         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/_N51412
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_fsm[3:0]_74/I5 (GTP_LUT6)
                                   td                    0.074       2.658 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_fsm[3:0]_74/Z (GTP_LUT6)
                                   net (fanout=3)        0.467       3.125         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/_N51506
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N463_23/I5 (GTP_LUT6)
                                   td                    0.074       3.199 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N463_23/Z (GTP_LUT6)
                                   net (fanout=2)        0.437       3.636         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N405
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N463_46/I2 (GTP_LUT6D)
                                   td                    0.096       3.732 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N463_46/Z (GTP_LUT6D)
                                   net (fanout=2)        0.437       4.169         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/_N11237
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N463_37_or[1]_4/I4 (GTP_LUT6D)
                                   td                    0.096       4.265 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N463_37_or[1]_4/Z (GTP_LUT6D)
                                   net (fanout=5)        0.505       4.770         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/_N51295
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N463_37_or[2]_1/I2 (GTP_LUT6D)
                                   td                    0.212       4.982 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N463_37_or[2]_1/Z5 (GTP_LUT6D)
                                   net (fanout=1)        0.000       4.982         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N463 [3]
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/cntr[3]/D (GTP_DFF_CE)

 Data arrival time                                                   4.982         Logic Levels: 6  
                                                                                   Logic: 0.905ns(23.313%), Route: 2.977ns(76.687%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            10.000      10.000 r                        
                                                         0.000      10.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100      11.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/cntr[3]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      11.100                          
 clock uncertainty                                      -0.050      11.050                          

 Setup time                                             -0.136      10.914                          

 Data required time                                                 10.914                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.914                          
 Data arrival time                                                   4.982                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         5.932                          
====================================================================================================

====================================================================================================

Startpoint  : u_uart2apb_top/u_uart_top/u_pgr_uart_rx/rx_data[1]/CLK (GTP_DFF_CE)
Endpoint    : u_uart2apb_top/u_uart_top/u_rx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/pgm_distributed_sdpram/mem_0/DI[0] (GTP_RAM32X2DP)
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_uart2apb_top/u_uart_top/u_pgr_uart_rx/rx_data[1]/CLK (GTP_DFF_CE)

                                   tco                   0.203       1.303 r       u_uart2apb_top/u_uart_top/u_pgr_uart_rx/rx_data[1]/Q (GTP_DFF_CE)
                                   net (fanout=1)        0.385       1.688         u_uart2apb_top/u_uart_top/rx_fifo_wr_data [0]
                                                                           r       u_uart2apb_top/u_uart_top/u_rx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/pgm_distributed_sdpram/mem_0/DI[0] (GTP_RAM32X2DP)

 Data arrival time                                                   1.688         Logic Levels: 0  
                                                                                   Logic: 0.203ns(34.524%), Route: 0.385ns(65.476%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_uart2apb_top/u_uart_top/u_rx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/pgm_distributed_sdpram/mem_0/WCLK (GTP_RAM32X2DP)
 clock pessimism                                         0.000       1.100                          
 clock uncertainty                                       0.000       1.100                          

 Hold time                                               0.264       1.364                          

 Data required time                                                  1.364                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  1.364                          
 Data arrival time                                                   1.688                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.324                          
====================================================================================================

====================================================================================================

Startpoint  : u_uart2apb_top/u_uart_top/u_pgr_uart_rx/rx_data[2]/CLK (GTP_DFF_CE)
Endpoint    : u_uart2apb_top/u_uart_top/u_rx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/pgm_distributed_sdpram/mem_0/DI[1] (GTP_RAM32X2DP)
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_uart2apb_top/u_uart_top/u_pgr_uart_rx/rx_data[2]/CLK (GTP_DFF_CE)

                                   tco                   0.203       1.303 r       u_uart2apb_top/u_uart_top/u_pgr_uart_rx/rx_data[2]/Q (GTP_DFF_CE)
                                   net (fanout=2)        0.437       1.740         u_uart2apb_top/u_uart_top/rx_fifo_wr_data [1]
                                                                           r       u_uart2apb_top/u_uart_top/u_rx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/pgm_distributed_sdpram/mem_0/DI[1] (GTP_RAM32X2DP)

 Data arrival time                                                   1.740         Logic Levels: 0  
                                                                                   Logic: 0.203ns(31.719%), Route: 0.437ns(68.281%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_uart2apb_top/u_uart_top/u_rx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/pgm_distributed_sdpram/mem_0/WCLK (GTP_RAM32X2DP)
 clock pessimism                                         0.000       1.100                          
 clock uncertainty                                       0.000       1.100                          

 Hold time                                               0.264       1.364                          

 Data required time                                                  1.364                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  1.364                          
 Data arrival time                                                   1.740                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.376                          
====================================================================================================

====================================================================================================

Startpoint  : u_uart2apb_top/u_uart_top/u_pgr_uart_rx/rx_data[3]/CLK (GTP_DFF_CE)
Endpoint    : u_uart2apb_top/u_uart_top/u_rx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/pgm_distributed_sdpram/mem_1/DI[0] (GTP_RAM32X2DP)
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_uart2apb_top/u_uart_top/u_pgr_uart_rx/rx_data[3]/CLK (GTP_DFF_CE)

                                   tco                   0.203       1.303 r       u_uart2apb_top/u_uart_top/u_pgr_uart_rx/rx_data[3]/Q (GTP_DFF_CE)
                                   net (fanout=2)        0.437       1.740         u_uart2apb_top/u_uart_top/rx_fifo_wr_data [2]
                                                                           r       u_uart2apb_top/u_uart_top/u_rx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/pgm_distributed_sdpram/mem_1/DI[0] (GTP_RAM32X2DP)

 Data arrival time                                                   1.740         Logic Levels: 0  
                                                                                   Logic: 0.203ns(31.719%), Route: 0.437ns(68.281%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_uart2apb_top/u_uart_top/u_rx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/pgm_distributed_sdpram/mem_1/WCLK (GTP_RAM32X2DP)
 clock pessimism                                         0.000       1.100                          
 clock uncertainty                                       0.000       1.100                          

 Hold time                                               0.264       1.364                          

 Data required time                                                  1.364                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  1.364                          
 Data arrival time                                                   1.740                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.376                          
====================================================================================================

====================================================================================================

Startpoint  : coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k_cnt[10]/D (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420       3.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R)

                                   tco                   0.203       3.583 r       coms1_reg_config/clock_20k_cnt[0]/Q (GTP_DFF_R)
                                   net (fanout=4)        0.489       4.072         coms1_reg_config/clock_20k_cnt [0]
                                                                                   coms1_reg_config/N8_mux4_5/I4 (GTP_LUT5)
                                   td                    0.157       4.229 r       coms1_reg_config/N8_mux4_5/Z (GTP_LUT5)
                                   net (fanout=4)        0.489       4.718         coms1_reg_config/_N7565
                                                                                   coms1_reg_config/N8_mux10/I4 (GTP_LUT5)
                                   td                    0.108       4.826 r       coms1_reg_config/N8_mux10/Z (GTP_LUT5)
                                   net (fanout=8)        0.541       5.367         coms1_reg_config/N8
                                                                                   coms1_reg_config/N11_2_1/I2 (GTP_LUT6CARRY)
                                   td                    0.159       5.526 f       coms1_reg_config/N11_2_1/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.526         coms1_reg_config/_N9930
                                                                                   coms1_reg_config/N11_2_2/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.548 f       coms1_reg_config/N11_2_2/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.548         coms1_reg_config/_N9931
                                                                                   coms1_reg_config/N11_2_3/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.570 f       coms1_reg_config/N11_2_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.570         coms1_reg_config/_N9932
                                                                                   coms1_reg_config/N11_2_4/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.592 f       coms1_reg_config/N11_2_4/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.592         coms1_reg_config/_N9933
                                                                                   coms1_reg_config/N11_2_5/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.614 f       coms1_reg_config/N11_2_5/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.614         coms1_reg_config/_N9934
                                                                                   coms1_reg_config/N11_2_6/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.636 f       coms1_reg_config/N11_2_6/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.636         coms1_reg_config/_N9935
                                                                                   coms1_reg_config/N11_2_7/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.658 f       coms1_reg_config/N11_2_7/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.658         coms1_reg_config/_N9936
                                                                                   coms1_reg_config/N11_2_8/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.680 f       coms1_reg_config/N11_2_8/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.680         coms1_reg_config/_N9937
                                                                                   coms1_reg_config/N11_2_9/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.702 f       coms1_reg_config/N11_2_9/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.702         coms1_reg_config/_N9938
                                                                                   coms1_reg_config/N11_2_10/CIN (GTP_LUT6CARRY)
                                   td                    0.068       5.770 r       coms1_reg_config/N11_2_10/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.770         coms1_reg_config/N1111 [10]
                                                                           r       coms1_reg_config/clock_20k_cnt[10]/D (GTP_DFF_R)

 Data arrival time                                                   5.770         Logic Levels: 5  
                                                                                   Logic: 0.871ns(36.444%), Route: 1.519ns(63.556%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420      43.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[10]/CLK (GTP_DFF_R)
 clock pessimism                                         0.000      43.380                          
 clock uncertainty                                      -0.050      43.330                          

 Setup time                                             -0.136      43.194                          

 Data required time                                                 43.194                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.194                          
 Data arrival time                                                   5.770                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.424                          
====================================================================================================

====================================================================================================

Startpoint  : coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k_cnt[9]/D (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420       3.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R)

                                   tco                   0.203       3.583 r       coms1_reg_config/clock_20k_cnt[0]/Q (GTP_DFF_R)
                                   net (fanout=4)        0.489       4.072         coms1_reg_config/clock_20k_cnt [0]
                                                                                   coms1_reg_config/N8_mux4_5/I4 (GTP_LUT5)
                                   td                    0.157       4.229 r       coms1_reg_config/N8_mux4_5/Z (GTP_LUT5)
                                   net (fanout=4)        0.489       4.718         coms1_reg_config/_N7565
                                                                                   coms1_reg_config/N8_mux10/I4 (GTP_LUT5)
                                   td                    0.108       4.826 r       coms1_reg_config/N8_mux10/Z (GTP_LUT5)
                                   net (fanout=8)        0.541       5.367         coms1_reg_config/N8
                                                                                   coms1_reg_config/N11_2_1/I2 (GTP_LUT6CARRY)
                                   td                    0.159       5.526 f       coms1_reg_config/N11_2_1/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.526         coms1_reg_config/_N9930
                                                                                   coms1_reg_config/N11_2_2/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.548 f       coms1_reg_config/N11_2_2/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.548         coms1_reg_config/_N9931
                                                                                   coms1_reg_config/N11_2_3/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.570 f       coms1_reg_config/N11_2_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.570         coms1_reg_config/_N9932
                                                                                   coms1_reg_config/N11_2_4/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.592 f       coms1_reg_config/N11_2_4/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.592         coms1_reg_config/_N9933
                                                                                   coms1_reg_config/N11_2_5/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.614 f       coms1_reg_config/N11_2_5/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.614         coms1_reg_config/_N9934
                                                                                   coms1_reg_config/N11_2_6/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.636 f       coms1_reg_config/N11_2_6/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.636         coms1_reg_config/_N9935
                                                                                   coms1_reg_config/N11_2_7/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.658 f       coms1_reg_config/N11_2_7/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.658         coms1_reg_config/_N9936
                                                                                   coms1_reg_config/N11_2_8/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.680 f       coms1_reg_config/N11_2_8/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.680         coms1_reg_config/_N9937
                                                                                   coms1_reg_config/N11_2_9/CIN (GTP_LUT6CARRY)
                                   td                    0.068       5.748 r       coms1_reg_config/N11_2_9/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.748         coms1_reg_config/N1111 [9]
                                                                           r       coms1_reg_config/clock_20k_cnt[9]/D (GTP_DFF_R)

 Data arrival time                                                   5.748         Logic Levels: 5  
                                                                                   Logic: 0.849ns(35.853%), Route: 1.519ns(64.147%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420      43.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[9]/CLK (GTP_DFF_R)
 clock pessimism                                         0.000      43.380                          
 clock uncertainty                                      -0.050      43.330                          

 Setup time                                             -0.136      43.194                          

 Data required time                                                 43.194                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.194                          
 Data arrival time                                                   5.748                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.446                          
====================================================================================================

====================================================================================================

Startpoint  : coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k_cnt[8]/D (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420       3.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R)

                                   tco                   0.203       3.583 r       coms1_reg_config/clock_20k_cnt[0]/Q (GTP_DFF_R)
                                   net (fanout=4)        0.489       4.072         coms1_reg_config/clock_20k_cnt [0]
                                                                                   coms1_reg_config/N8_mux4_5/I4 (GTP_LUT5)
                                   td                    0.157       4.229 r       coms1_reg_config/N8_mux4_5/Z (GTP_LUT5)
                                   net (fanout=4)        0.489       4.718         coms1_reg_config/_N7565
                                                                                   coms1_reg_config/N8_mux10/I4 (GTP_LUT5)
                                   td                    0.108       4.826 r       coms1_reg_config/N8_mux10/Z (GTP_LUT5)
                                   net (fanout=8)        0.541       5.367         coms1_reg_config/N8
                                                                                   coms1_reg_config/N11_2_1/I2 (GTP_LUT6CARRY)
                                   td                    0.159       5.526 f       coms1_reg_config/N11_2_1/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.526         coms1_reg_config/_N9930
                                                                                   coms1_reg_config/N11_2_2/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.548 f       coms1_reg_config/N11_2_2/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.548         coms1_reg_config/_N9931
                                                                                   coms1_reg_config/N11_2_3/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.570 f       coms1_reg_config/N11_2_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.570         coms1_reg_config/_N9932
                                                                                   coms1_reg_config/N11_2_4/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.592 f       coms1_reg_config/N11_2_4/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.592         coms1_reg_config/_N9933
                                                                                   coms1_reg_config/N11_2_5/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.614 f       coms1_reg_config/N11_2_5/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.614         coms1_reg_config/_N9934
                                                                                   coms1_reg_config/N11_2_6/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.636 f       coms1_reg_config/N11_2_6/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.636         coms1_reg_config/_N9935
                                                                                   coms1_reg_config/N11_2_7/CIN (GTP_LUT6CARRY)
                                   td                    0.022       5.658 f       coms1_reg_config/N11_2_7/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.658         coms1_reg_config/_N9936
                                                                                   coms1_reg_config/N11_2_8/CIN (GTP_LUT6CARRY)
                                   td                    0.068       5.726 r       coms1_reg_config/N11_2_8/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.726         coms1_reg_config/N1111 [8]
                                                                           r       coms1_reg_config/clock_20k_cnt[8]/D (GTP_DFF_R)

 Data arrival time                                                   5.726         Logic Levels: 4  
                                                                                   Logic: 0.827ns(35.251%), Route: 1.519ns(64.749%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420      43.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[8]/CLK (GTP_DFF_R)
 clock pessimism                                         0.000      43.380                          
 clock uncertainty                                      -0.050      43.330                          

 Setup time                                             -0.136      43.194                          

 Data required time                                                 43.194                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.194                          
 Data arrival time                                                   5.726                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.468                          
====================================================================================================

====================================================================================================

Startpoint  : coms1_reg_config/clock_20k_cnt[3]/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k_cnt[3]/D (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420       3.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[3]/CLK (GTP_DFF_R)

                                   tco                   0.185       3.565 f       coms1_reg_config/clock_20k_cnt[3]/Q (GTP_DFF_R)
                                   net (fanout=2)        0.437       4.002         coms1_reg_config/clock_20k_cnt [3]
                                                                                   coms1_reg_config/N11_2_3/I0 (GTP_LUT6CARRY)
                                   td                    0.108       4.110 r       coms1_reg_config/N11_2_3/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       4.110         coms1_reg_config/N1111 [3]
                                                                           r       coms1_reg_config/clock_20k_cnt[3]/D (GTP_DFF_R)

 Data arrival time                                                   4.110         Logic Levels: 1  
                                                                                   Logic: 0.293ns(40.137%), Route: 0.437ns(59.863%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420       3.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[3]/CLK (GTP_DFF_R)
 clock pessimism                                         0.000       3.380                          
 clock uncertainty                                       0.000       3.380                          

 Hold time                                              -0.040       3.340                          

 Data required time                                                  3.340                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.340                          
 Data arrival time                                                   4.110                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.770                          
====================================================================================================

====================================================================================================

Startpoint  : coms1_reg_config/clock_20k_cnt[4]/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k_cnt[4]/D (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420       3.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[4]/CLK (GTP_DFF_R)

                                   tco                   0.185       3.565 f       coms1_reg_config/clock_20k_cnt[4]/Q (GTP_DFF_R)
                                   net (fanout=2)        0.437       4.002         coms1_reg_config/clock_20k_cnt [4]
                                                                                   coms1_reg_config/N11_2_4/I0 (GTP_LUT6CARRY)
                                   td                    0.108       4.110 r       coms1_reg_config/N11_2_4/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       4.110         coms1_reg_config/N1111 [4]
                                                                           r       coms1_reg_config/clock_20k_cnt[4]/D (GTP_DFF_R)

 Data arrival time                                                   4.110         Logic Levels: 1  
                                                                                   Logic: 0.293ns(40.137%), Route: 0.437ns(59.863%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420       3.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[4]/CLK (GTP_DFF_R)
 clock pessimism                                         0.000       3.380                          
 clock uncertainty                                       0.000       3.380                          

 Hold time                                              -0.040       3.340                          

 Data required time                                                  3.340                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.340                          
 Data arrival time                                                   4.110                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.770                          
====================================================================================================

====================================================================================================

Startpoint  : coms1_reg_config/clock_20k_cnt[5]/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k_cnt[5]/D (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420       3.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[5]/CLK (GTP_DFF_R)

                                   tco                   0.185       3.565 f       coms1_reg_config/clock_20k_cnt[5]/Q (GTP_DFF_R)
                                   net (fanout=2)        0.437       4.002         coms1_reg_config/clock_20k_cnt [5]
                                                                                   coms1_reg_config/N11_2_5/I0 (GTP_LUT6CARRY)
                                   td                    0.108       4.110 r       coms1_reg_config/N11_2_5/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       4.110         coms1_reg_config/N1111 [5]
                                                                           r       coms1_reg_config/clock_20k_cnt[5]/D (GTP_DFF_R)

 Data arrival time                                                   4.110         Logic Levels: 1  
                                                                                   Logic: 0.293ns(40.137%), Route: 0.437ns(59.863%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420       3.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[5]/CLK (GTP_DFF_R)
 clock pessimism                                         0.000       3.380                          
 clock uncertainty                                       0.000       3.380                          

 Hold time                                              -0.040       3.340                          

 Data required time                                                  3.340                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.340                          
 Data arrival time                                                   4.110                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.770                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k/R (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.532  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                        20.000      20.000 r                        
 sys_clk                                                 0.000      20.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      20.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      20.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      22.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066      22.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420      24.912         clk_50M          
                                                                           r       power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)

                                   tco                   0.203      25.115 r       power_on_delay_inst/camera_rstn_reg/Q (GTP_DFF_R)
                                   net (fanout=5)        0.505      25.620         nt_cmos2_reset   
                                                                                   coms1_reg_config/N4/I0 (GTP_LUT3)
                                   td                    0.224      25.844 r       coms1_reg_config/N4/Z (GTP_LUT3)
                                   net (fanout=58)       0.588      26.432         coms1_reg_config/N4
                                                                           r       coms1_reg_config/clock_20k/R (GTP_DFF_R)

 Data arrival time                                                  26.432         Logic Levels: 1  
                                                                                   Logic: 0.427ns(28.092%), Route: 1.093ns(71.908%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420      43.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k/CLK (GTP_DFF_R)
 clock pessimism                                         0.000      43.380                          
 clock uncertainty                                      -0.050      43.330                          

 Setup time                                             -0.244      43.086                          

 Data required time                                                 43.086                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.086                          
 Data arrival time                                                  26.432                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        16.654                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k_cnt[0]/R (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.532  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                        20.000      20.000 r                        
 sys_clk                                                 0.000      20.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      20.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      20.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      22.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066      22.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420      24.912         clk_50M          
                                                                           r       power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)

                                   tco                   0.203      25.115 r       power_on_delay_inst/camera_rstn_reg/Q (GTP_DFF_R)
                                   net (fanout=5)        0.505      25.620         nt_cmos2_reset   
                                                                                   coms1_reg_config/N4/I0 (GTP_LUT3)
                                   td                    0.224      25.844 r       coms1_reg_config/N4/Z (GTP_LUT3)
                                   net (fanout=58)       0.588      26.432         coms1_reg_config/N4
                                                                           r       coms1_reg_config/clock_20k_cnt[0]/R (GTP_DFF_R)

 Data arrival time                                                  26.432         Logic Levels: 1  
                                                                                   Logic: 0.427ns(28.092%), Route: 1.093ns(71.908%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420      43.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R)
 clock pessimism                                         0.000      43.380                          
 clock uncertainty                                      -0.050      43.330                          

 Setup time                                             -0.244      43.086                          

 Data required time                                                 43.086                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.086                          
 Data arrival time                                                  26.432                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        16.654                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k_cnt[1]/R (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.532  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                        20.000      20.000 r                        
 sys_clk                                                 0.000      20.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      20.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      20.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      22.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066      22.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420      24.912         clk_50M          
                                                                           r       power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)

                                   tco                   0.203      25.115 r       power_on_delay_inst/camera_rstn_reg/Q (GTP_DFF_R)
                                   net (fanout=5)        0.505      25.620         nt_cmos2_reset   
                                                                                   coms1_reg_config/N4/I0 (GTP_LUT3)
                                   td                    0.224      25.844 r       coms1_reg_config/N4/Z (GTP_LUT3)
                                   net (fanout=58)       0.588      26.432         coms1_reg_config/N4
                                                                           r       coms1_reg_config/clock_20k_cnt[1]/R (GTP_DFF_R)

 Data arrival time                                                  26.432         Logic Levels: 1  
                                                                                   Logic: 0.427ns(28.092%), Route: 1.093ns(71.908%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420      43.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[1]/CLK (GTP_DFF_R)
 clock pessimism                                         0.000      43.380                          
 clock uncertainty                                      -0.050      43.330                          

 Setup time                                             -0.244      43.086                          

 Data required time                                                 43.086                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.086                          
 Data arrival time                                                  26.432                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        16.654                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k/R (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.532  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                        40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      42.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066      42.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420      44.912         clk_50M          
                                                                           r       power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)

                                   tco                   0.185      45.097 f       power_on_delay_inst/camera_rstn_reg/Q (GTP_DFF_R)
                                   net (fanout=5)        0.505      45.602         nt_cmos2_reset   
                                                                                   coms1_reg_config/N4/I0 (GTP_LUT3)
                                   td                    0.191      45.793 f       coms1_reg_config/N4/Z (GTP_LUT3)
                                   net (fanout=58)       0.588      46.381         coms1_reg_config/N4
                                                                           f       coms1_reg_config/clock_20k/R (GTP_DFF_R)

 Data arrival time                                                  46.381         Logic Levels: 1  
                                                                                   Logic: 0.376ns(25.596%), Route: 1.093ns(74.404%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420      43.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k/CLK (GTP_DFF_R)
 clock pessimism                                         0.000      43.380                          
 clock uncertainty                                       0.050      43.430                          

 Hold time                                              -0.043      43.387                          

 Data required time                                                 43.387                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.387                          
 Data arrival time                                                  46.381                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         2.994                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k_cnt[0]/R (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.532  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                        40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      42.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066      42.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420      44.912         clk_50M          
                                                                           r       power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)

                                   tco                   0.185      45.097 f       power_on_delay_inst/camera_rstn_reg/Q (GTP_DFF_R)
                                   net (fanout=5)        0.505      45.602         nt_cmos2_reset   
                                                                                   coms1_reg_config/N4/I0 (GTP_LUT3)
                                   td                    0.191      45.793 f       coms1_reg_config/N4/Z (GTP_LUT3)
                                   net (fanout=58)       0.588      46.381         coms1_reg_config/N4
                                                                           f       coms1_reg_config/clock_20k_cnt[0]/R (GTP_DFF_R)

 Data arrival time                                                  46.381         Logic Levels: 1  
                                                                                   Logic: 0.376ns(25.596%), Route: 1.093ns(74.404%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420      43.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R)
 clock pessimism                                         0.000      43.380                          
 clock uncertainty                                       0.050      43.430                          

 Hold time                                              -0.043      43.387                          

 Data required time                                                 43.387                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.387                          
 Data arrival time                                                  46.381                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         2.994                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)
Endpoint    : coms1_reg_config/clock_20k_cnt[1]/R (GTP_DFF_R)
Path Group  : sys_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.532  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                        40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      42.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066      42.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420      44.912         clk_50M          
                                                                           r       power_on_delay_inst/camera_rstn_reg/CLK (GTP_DFF_R)

                                   tco                   0.185      45.097 f       power_on_delay_inst/camera_rstn_reg/Q (GTP_DFF_R)
                                   net (fanout=5)        0.505      45.602         nt_cmos2_reset   
                                                                                   coms1_reg_config/N4/I0 (GTP_LUT3)
                                   td                    0.191      45.793 f       coms1_reg_config/N4/Z (GTP_LUT3)
                                   net (fanout=58)       0.588      46.381         coms1_reg_config/N4
                                                                           f       coms1_reg_config/clock_20k_cnt[1]/R (GTP_DFF_R)

 Data arrival time                                                  46.381         Logic Levels: 1  
                                                                                   Logic: 0.376ns(25.596%), Route: 1.093ns(74.404%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420      43.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k_cnt[1]/CLK (GTP_DFF_R)
 clock pessimism                                         0.000      43.380                          
 clock uncertainty                                       0.050      43.430                          

 Hold time                                              -0.043      43.387                          

 Data required time                                                 43.387                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.387                          
 Data arrival time                                                  46.381                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         2.994                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_href_d0/CLK (GTP_DFF)
Endpoint    : cmos1_8_16bit/cnt[0]/R (GTP_DFF_RE)
Path Group  : cmos1_pclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420       3.380         nt_cmos1_pclk    
                                                                           r       cmos1_href_d0/CLK (GTP_DFF)

                                   tco                   0.203       3.583 r       cmos1_href_d0/Q (GTP_DFF)
                                   net (fanout=12)       0.505       4.088         cmos1_href_d0    
                                                                                   cmos1_8_16bit/N14_3/I0 (GTP_LUT6CARRY)
                                   td                    0.175       4.263 f       cmos1_8_16bit/N14_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       4.263         cmos1_8_16bit/N14_co
                                                                                   cmos1_8_16bit/N14_4/CIN (GTP_LUT6CARRY)
                                   td                    0.068       4.331 r       cmos1_8_16bit/N14_4/Z (GTP_LUT6CARRY)
                                   net (fanout=2)        0.385       4.716         cmos1_8_16bit/N51
                                                                           r       cmos1_8_16bit/cnt[0]/R (GTP_DFF_RE)

 Data arrival time                                                   4.716         Logic Levels: 1  
                                                                                   Logic: 0.446ns(33.383%), Route: 0.890ns(66.617%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                         23.810      23.810 r                        
 cmos1_pclk                                              0.000      23.810 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000      23.810         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960      24.770 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420      27.190         nt_cmos1_pclk    
                                                                           r       cmos1_8_16bit/cnt[0]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000      27.190                          
 clock uncertainty                                      -0.250      26.940                          

 Setup time                                             -0.244      26.696                          

 Data required time                                                 26.696                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 26.696                          
 Data arrival time                                                   4.716                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        21.980                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_href_d0/CLK (GTP_DFF)
Endpoint    : cmos1_8_16bit/cnt[1]/R (GTP_DFF_RE)
Path Group  : cmos1_pclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420       3.380         nt_cmos1_pclk    
                                                                           r       cmos1_href_d0/CLK (GTP_DFF)

                                   tco                   0.203       3.583 r       cmos1_href_d0/Q (GTP_DFF)
                                   net (fanout=12)       0.505       4.088         cmos1_href_d0    
                                                                                   cmos1_8_16bit/N14_3/I0 (GTP_LUT6CARRY)
                                   td                    0.175       4.263 f       cmos1_8_16bit/N14_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       4.263         cmos1_8_16bit/N14_co
                                                                                   cmos1_8_16bit/N14_4/CIN (GTP_LUT6CARRY)
                                   td                    0.068       4.331 r       cmos1_8_16bit/N14_4/Z (GTP_LUT6CARRY)
                                   net (fanout=2)        0.385       4.716         cmos1_8_16bit/N51
                                                                           r       cmos1_8_16bit/cnt[1]/R (GTP_DFF_RE)

 Data arrival time                                                   4.716         Logic Levels: 1  
                                                                                   Logic: 0.446ns(33.383%), Route: 0.890ns(66.617%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                         23.810      23.810 r                        
 cmos1_pclk                                              0.000      23.810 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000      23.810         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960      24.770 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420      27.190         nt_cmos1_pclk    
                                                                           r       cmos1_8_16bit/cnt[1]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000      27.190                          
 clock uncertainty                                      -0.250      26.940                          

 Setup time                                             -0.244      26.696                          

 Data required time                                                 26.696                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 26.696                          
 Data arrival time                                                   4.716                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        21.980                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_href_d0/CLK (GTP_DFF)
Endpoint    : cmos1_8_16bit/pdata_out1[0]/CE (GTP_DFF_RE)
Path Group  : cmos1_pclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420       3.380         nt_cmos1_pclk    
                                                                           r       cmos1_href_d0/CLK (GTP_DFF)

                                   tco                   0.203       3.583 r       cmos1_href_d0/Q (GTP_DFF)
                                   net (fanout=12)       0.505       4.088         cmos1_href_d0    
                                                                                   cmos1_8_16bit/N14_3/I0 (GTP_LUT6CARRY)
                                   td                    0.116       4.204 r       cmos1_8_16bit/N14_3/Z (GTP_LUT6CARRY)
                                   net (fanout=16)       0.489       4.693         cmos1_8_16bit/N14
                                                                           r       cmos1_8_16bit/pdata_out1[0]/CE (GTP_DFF_RE)

 Data arrival time                                                   4.693         Logic Levels: 1  
                                                                                   Logic: 0.319ns(24.296%), Route: 0.994ns(75.704%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                         23.810      23.810 r                        
 cmos1_pclk                                              0.000      23.810 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000      23.810         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960      24.770 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420      27.190         nt_cmos1_pclk    
                                                                           r       cmos1_8_16bit/pdata_out1[0]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000      27.190                          
 clock uncertainty                                      -0.250      26.940                          

 Setup time                                             -0.226      26.714                          

 Data required time                                                 26.714                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 26.714                          
 Data arrival time                                                   4.693                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        22.021                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_8_16bit/pdata_i_reg[0]/CLK (GTP_DFF_RE)
Endpoint    : cmos1_8_16bit/pdata_out1[8]/D (GTP_DFF_RE)
Path Group  : cmos1_pclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420       3.380         nt_cmos1_pclk    
                                                                           r       cmos1_8_16bit/pdata_i_reg[0]/CLK (GTP_DFF_RE)

                                   tco                   0.185       3.565 f       cmos1_8_16bit/pdata_i_reg[0]/Q (GTP_DFF_RE)
                                   net (fanout=1)        0.385       3.950         cmos1_8_16bit/pdata_i_reg [0]
                                                                           f       cmos1_8_16bit/pdata_out1[8]/D (GTP_DFF_RE)

 Data arrival time                                                   3.950         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420       3.380         nt_cmos1_pclk    
                                                                           r       cmos1_8_16bit/pdata_out1[8]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000       3.380                          
 clock uncertainty                                       0.200       3.580                          

 Hold time                                              -0.049       3.531                          

 Data required time                                                  3.531                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.531                          
 Data arrival time                                                   3.950                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.419                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_8_16bit/pdata_i_reg[1]/CLK (GTP_DFF_RE)
Endpoint    : cmos1_8_16bit/pdata_out1[9]/D (GTP_DFF_RE)
Path Group  : cmos1_pclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420       3.380         nt_cmos1_pclk    
                                                                           r       cmos1_8_16bit/pdata_i_reg[1]/CLK (GTP_DFF_RE)

                                   tco                   0.185       3.565 f       cmos1_8_16bit/pdata_i_reg[1]/Q (GTP_DFF_RE)
                                   net (fanout=1)        0.385       3.950         cmos1_8_16bit/pdata_i_reg [1]
                                                                           f       cmos1_8_16bit/pdata_out1[9]/D (GTP_DFF_RE)

 Data arrival time                                                   3.950         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420       3.380         nt_cmos1_pclk    
                                                                           r       cmos1_8_16bit/pdata_out1[9]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000       3.380                          
 clock uncertainty                                       0.200       3.580                          

 Hold time                                              -0.049       3.531                          

 Data required time                                                  3.531                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.531                          
 Data arrival time                                                   3.950                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.419                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_8_16bit/pdata_i_reg[2]/CLK (GTP_DFF_RE)
Endpoint    : cmos1_8_16bit/pdata_out1[10]/D (GTP_DFF_RE)
Path Group  : cmos1_pclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.380
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420       3.380         nt_cmos1_pclk    
                                                                           r       cmos1_8_16bit/pdata_i_reg[2]/CLK (GTP_DFF_RE)

                                   tco                   0.185       3.565 f       cmos1_8_16bit/pdata_i_reg[2]/Q (GTP_DFF_RE)
                                   net (fanout=1)        0.385       3.950         cmos1_8_16bit/pdata_i_reg [2]
                                                                           f       cmos1_8_16bit/pdata_out1[10]/D (GTP_DFF_RE)

 Data arrival time                                                   3.950         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420       3.380         nt_cmos1_pclk    
                                                                           r       cmos1_8_16bit/pdata_out1[10]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000       3.380                          
 clock uncertainty                                       0.200       3.580                          

 Hold time                                              -0.049       3.531                          

 Data required time                                                  3.531                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.531                          
 Data arrival time                                                   3.950                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.419                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out[0]/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[0]/CE (GTP_DFF_PE)
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out[0]/CLK (GTP_DFF_C)

                                   tco                   0.203       5.281 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out[0]/Q (GTP_DFF_C)
                                   net (fanout=6)        0.519       5.800         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N225_6/I0 (GTP_LUT6)
                                   td                    0.143       5.943 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N225_6/Z (GTP_LUT6)
                                   net (fanout=3)        0.467       6.410         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N225
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N320_1_3/I1 (GTP_LUT6)
                                   td                    0.117       6.527 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N320_1_3/Z (GTP_LUT6)
                                   net (fanout=1)        0.385       6.912         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/_N57360
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N325/I4 (GTP_LUT5)
                                   td                    0.096       7.008 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N325/Z (GTP_LUT5)
                                   net (fanout=10)       0.467       7.475         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N325
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[0]/CE (GTP_DFF_PE)

 Data arrival time                                                   7.475         Logic Levels: 3  
                                                                                   Logic: 0.559ns(23.321%), Route: 1.838ns(76.679%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      42.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064      42.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      43.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      43.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100      45.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[0]/CLK (GTP_DFF_PE)
 clock pessimism                                         0.000      45.078                          
 clock uncertainty                                      -0.150      44.928                          

 Setup time                                             -0.226      44.702                          

 Data required time                                                 44.702                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.702                          
 Data arrival time                                                   7.475                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.227                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out[0]/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[1]/CE (GTP_DFF_CE)
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out[0]/CLK (GTP_DFF_C)

                                   tco                   0.203       5.281 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out[0]/Q (GTP_DFF_C)
                                   net (fanout=6)        0.519       5.800         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N225_6/I0 (GTP_LUT6)
                                   td                    0.143       5.943 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N225_6/Z (GTP_LUT6)
                                   net (fanout=3)        0.467       6.410         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N225
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N320_1_3/I1 (GTP_LUT6)
                                   td                    0.117       6.527 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N320_1_3/Z (GTP_LUT6)
                                   net (fanout=1)        0.385       6.912         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/_N57360
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N325/I4 (GTP_LUT5)
                                   td                    0.096       7.008 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N325/Z (GTP_LUT5)
                                   net (fanout=10)       0.467       7.475         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N325
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[1]/CE (GTP_DFF_CE)

 Data arrival time                                                   7.475         Logic Levels: 3  
                                                                                   Logic: 0.559ns(23.321%), Route: 1.838ns(76.679%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      42.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064      42.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      43.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      43.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100      45.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[1]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      45.078                          
 clock uncertainty                                      -0.150      44.928                          

 Setup time                                             -0.226      44.702                          

 Data required time                                                 44.702                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.702                          
 Data arrival time                                                   7.475                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.227                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out[0]/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/CE (GTP_DFF_CE)
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out[0]/CLK (GTP_DFF_C)

                                   tco                   0.203       5.281 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out[0]/Q (GTP_DFF_C)
                                   net (fanout=6)        0.519       5.800         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/time_out [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N225_6/I0 (GTP_LUT6)
                                   td                    0.143       5.943 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N225_6/Z (GTP_LUT6)
                                   net (fanout=3)        0.467       6.410         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N225
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N320_1_3/I1 (GTP_LUT6)
                                   td                    0.117       6.527 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N320_1_3/Z (GTP_LUT6)
                                   net (fanout=1)        0.385       6.912         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/_N57360
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N325/I4 (GTP_LUT5)
                                   td                    0.096       7.008 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N325/Z (GTP_LUT5)
                                   net (fanout=10)       0.467       7.475         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N325
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/CE (GTP_DFF_CE)

 Data arrival time                                                   7.475         Logic Levels: 3  
                                                                                   Logic: 0.559ns(23.321%), Route: 1.838ns(76.679%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      42.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064      42.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      43.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      43.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100      45.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      45.078                          
 clock uncertainty                                      -0.150      44.928                          

 Setup time                                             -0.226      44.702                          

 Data required time                                                 44.702                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.702                          
 Data arrival time                                                   7.475                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.227                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/DPS_EN (GTP_GPLL)
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/CLK (GTP_DFF_C)

                                   tco                   0.185       5.263 f       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/Q (GTP_DFF_C)
                                   net (fanout=1)        0.385       5.648         u_ddr3/u_ddrphy_top/gpll_dps_en
                                                                           f       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/DPS_EN (GTP_GPLL)

 Data arrival time                                                   5.648         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/DPS_CLK (GTP_GPLL)
 clock pessimism                                         0.000       5.078                          
 clock uncertainty                                       0.000       5.078                          

 Hold time                                               0.063       5.141                          

 Data required time                                                  5.141                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.141                          
 Data arrival time                                                   5.648                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.507                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_dir/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/DPS_DIR (GTP_GPLL)
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_dir/CLK (GTP_DFF_C)

                                   tco                   0.185       5.263 f       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_dir/Q (GTP_DFF_C)
                                   net (fanout=2)        0.437       5.700         u_ddr3/u_ddrphy_top/gpll_dps_dir
                                                                           f       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/DPS_DIR (GTP_GPLL)

 Data arrival time                                                   5.700         Logic Levels: 0  
                                                                                   Logic: 0.185ns(29.743%), Route: 0.437ns(70.257%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/DPS_CLK (GTP_GPLL)
 clock pessimism                                         0.000       5.078                          
 clock uncertainty                                       0.000       5.078                          

 Hold time                                               0.063       5.141                          

 Data required time                                                  5.141                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.141                          
 Data arrival time                                                   5.700                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.559                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[1]/D (GTP_DFF_C)
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/CLK (GTP_DFF_C)

                                   tco                   0.185       5.263 f       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/Q (GTP_DFF_C)
                                   net (fanout=1)        0.385       5.648         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d [0]
                                                                           f       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[1]/D (GTP_DFF_C)

 Data arrival time                                                   5.648         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[1]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000       5.078                          
 clock uncertainty                                       0.000       5.078                          

 Hold time                                              -0.049       5.029                          

 Data required time                                                  5.029                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.029                          
 Data arrival time                                                   5.648                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.619                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/D (GTP_DFF_C)
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.896
  Launch Clock Delay      :  10.224
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C)

                                   tco                   0.203      10.427 r       u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/Q (GTP_DFF_C)
                                   net (fanout=283)      1.196      11.623         u_ddr3/u_ddrphy_top/calib_done
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_1/I2 (GTP_LUT6CARRY)
                                   td                    0.159      11.782 f       u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_1/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.782         u_ddr3/u_ddrphy_top/ddrphy_dfi/w_phy_cke[0]_co
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_2/CIN (GTP_LUT6CARRY)
                                   td                    0.068      11.850 r       u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_2/Z (GTP_LUT6CARRY)
                                   net (fanout=2)        0.437      12.287         u_ddr3/u_ddrphy_top/_N58357
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/N11[0]/I3 (GTP_LUT4)
                                   td                    0.108      12.395 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/N11[0]/Z (GTP_LUT4)
                                   net (fanout=9)        0.549      12.944         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_13[0]/I3 (GTP_LUT6)
                                   td                    0.074      13.018 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_13[0]/Z (GTP_LUT6)
                                   net (fanout=1)        0.385      13.403         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/_N14606
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_14[0]/I5 (GTP_LUT6)
                                   td                    0.074      13.477 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_14[0]/Z (GTP_LUT6)
                                   net (fanout=7)        0.531      14.008         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src_4[0]/I1 (GTP_LUT2)
                                   td                    0.224      14.232 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src_4[0]/Z (GTP_LUT2)
                                   net (fanout=5)        0.505      14.737         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[4]/I3 (GTP_LUT6)
                                   td                    0.074      14.811 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[4]/Z (GTP_LUT6)
                                   net (fanout=1)        0.385      15.196         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/_N14538
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[4]/I5 (GTP_LUT6)
                                   td                    0.074      15.270 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[4]/Z (GTP_LUT6)
                                   net (fanout=1)        0.000      15.270         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj [0]
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/D (GTP_DFF_C)

 Data arrival time                                                  15.270         Logic Levels: 7  
                                                                                   Logic: 1.058ns(20.967%), Route: 3.988ns(79.033%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 sys_clk                                                 0.000       7.619 r       sys_clk (port)   
                                   net (fanout=1)        0.000       7.619         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       8.579 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       9.899         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148      10.047 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200      12.247         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177      12.424 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385      12.809         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037      12.846 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653      13.499         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123      13.622 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420      16.042         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115      14.927 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      16.247         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      16.415 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      17.515         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      17.515                          
 clock uncertainty                                      -0.150      17.365                          

 Setup time                                             -0.136      17.229                          

 Data required time                                                 17.229                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 17.229                          
 Data arrival time                                                  15.270                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.959                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/D (GTP_DFF_C)
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.896
  Launch Clock Delay      :  10.224
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C)

                                   tco                   0.203      10.427 r       u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/Q (GTP_DFF_C)
                                   net (fanout=283)      1.196      11.623         u_ddr3/u_ddrphy_top/calib_done
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_1/I2 (GTP_LUT6CARRY)
                                   td                    0.159      11.782 f       u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_1/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.782         u_ddr3/u_ddrphy_top/ddrphy_dfi/w_phy_cke[0]_co
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_2/CIN (GTP_LUT6CARRY)
                                   td                    0.068      11.850 r       u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_2/Z (GTP_LUT6CARRY)
                                   net (fanout=2)        0.437      12.287         u_ddr3/u_ddrphy_top/_N58357
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/N11[0]/I3 (GTP_LUT4)
                                   td                    0.108      12.395 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/N11[0]/Z (GTP_LUT4)
                                   net (fanout=9)        0.549      12.944         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_13[0]/I3 (GTP_LUT6)
                                   td                    0.074      13.018 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_13[0]/Z (GTP_LUT6)
                                   net (fanout=1)        0.385      13.403         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/_N14606
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_14[0]/I5 (GTP_LUT6)
                                   td                    0.074      13.477 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_14[0]/Z (GTP_LUT6)
                                   net (fanout=7)        0.531      14.008         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src_4[0]/I1 (GTP_LUT2)
                                   td                    0.224      14.232 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src_4[0]/Z (GTP_LUT2)
                                   net (fanout=5)        0.505      14.737         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[5]/I3 (GTP_LUT6)
                                   td                    0.074      14.811 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[5]/Z (GTP_LUT6)
                                   net (fanout=1)        0.385      15.196         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/_N14539
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[5]/I5 (GTP_LUT6)
                                   td                    0.074      15.270 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[5]/Z (GTP_LUT6)
                                   net (fanout=1)        0.000      15.270         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj [1]
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/D (GTP_DFF_C)

 Data arrival time                                                  15.270         Logic Levels: 7  
                                                                                   Logic: 1.058ns(20.967%), Route: 3.988ns(79.033%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 sys_clk                                                 0.000       7.619 r       sys_clk (port)   
                                   net (fanout=1)        0.000       7.619         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       8.579 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       9.899         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148      10.047 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200      12.247         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177      12.424 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385      12.809         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037      12.846 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653      13.499         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123      13.622 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420      16.042         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115      14.927 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      16.247         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      16.415 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      17.515         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      17.515                          
 clock uncertainty                                      -0.150      17.365                          

 Setup time                                             -0.136      17.229                          

 Data required time                                                 17.229                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 17.229                          
 Data arrival time                                                  15.270                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.959                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/D (GTP_DFF_C)
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.896
  Launch Clock Delay      :  10.224
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C)

                                   tco                   0.203      10.427 r       u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/Q (GTP_DFF_C)
                                   net (fanout=283)      1.196      11.623         u_ddr3/u_ddrphy_top/calib_done
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_1/I2 (GTP_LUT6CARRY)
                                   td                    0.159      11.782 f       u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_1/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.782         u_ddr3/u_ddrphy_top/ddrphy_dfi/w_phy_cke[0]_co
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_2/CIN (GTP_LUT6CARRY)
                                   td                    0.068      11.850 r       u_ddr3/u_ddrphy_top/ddrphy_dfi/N16_2/Z (GTP_LUT6CARRY)
                                   net (fanout=2)        0.437      12.287         u_ddr3/u_ddrphy_top/_N58357
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/N11[0]/I3 (GTP_LUT4)
                                   td                    0.108      12.395 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/N11[0]/Z (GTP_LUT4)
                                   net (fanout=9)        0.549      12.944         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_13[0]/I3 (GTP_LUT6)
                                   td                    0.074      13.018 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_13[0]/Z (GTP_LUT6)
                                   net (fanout=1)        0.385      13.403         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/_N14606
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_14[0]/I5 (GTP_LUT6)
                                   td                    0.074      13.477 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped_14[0]/Z (GTP_LUT6)
                                   net (fanout=7)        0.531      14.008         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_en_slipped [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src_4[0]/I1 (GTP_LUT2)
                                   td                    0.224      14.232 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src_4[0]/Z (GTP_LUT2)
                                   net (fanout=5)        0.505      14.737         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_163[6]/I3 (GTP_LUT6)
                                   td                    0.074      14.811 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_163[6]/Z (GTP_LUT6)
                                   net (fanout=1)        0.385      15.196         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/_N14484
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[6]/I4 (GTP_LUT6)
                                   td                    0.074      15.270 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[6]/Z (GTP_LUT6)
                                   net (fanout=1)        0.000      15.270         u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_adj [2]
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/D (GTP_DFF_C)

 Data arrival time                                                  15.270         Logic Levels: 7  
                                                                                   Logic: 1.058ns(20.967%), Route: 3.988ns(79.033%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 sys_clk                                                 0.000       7.619 r       sys_clk (port)   
                                   net (fanout=1)        0.000       7.619         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       8.579 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       9.899         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148      10.047 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200      12.247         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177      12.424 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385      12.809         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037      12.846 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653      13.499         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123      13.622 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420      16.042         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115      14.927 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      16.247         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      16.415 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      17.515         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      17.515                          
 clock uncertainty                                      -0.150      17.365                          

 Setup time                                             -0.136      17.229                          

 Data required time                                                 17.229                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 17.229                          
 Data arrival time                                                  15.270                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.959                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rlast/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0/mem/DI (GTP_RAM32X1DP)
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  10.224
  Launch Clock Delay      :  9.896
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115       7.308 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.628         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       8.796 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100       9.896         ddr_core_clk     
                                                                           r       u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rlast/CLK (GTP_DFF_C)

                                   tco                   0.203      10.099 r       u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rlast/Q (GTP_DFF_C)
                                   net (fanout=1)        0.385      10.484         u_ddr3/u_ips_ddrc_top/rlast
                                                                           r       u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0/mem/DI (GTP_RAM32X1DP)

 Data arrival time                                                  10.484         Logic Levels: 0  
                                                                                   Logic: 0.203ns(34.524%), Route: 0.385ns(65.476%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0/mem/WCLK (GTP_RAM32X1DP)
 clock pessimism                                         0.000      10.224                          
 clock uncertainty                                       0.000      10.224                          

 Hold time                                               0.264      10.488                          

 Data required time                                                 10.488                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.488                          
 Data arrival time                                                  10.484                          
----------------------------------------------------------------------------------------------------
 Slack (VIOLATED)                                                   -0.004                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0/mem/WADDR[4] (GTP_RAM32X1DP)
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  10.224
  Launch Clock Delay      :  9.896
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115       7.308 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.628         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       8.796 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100       9.896         ddr_core_clk     
                                                                           r       u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (GTP_DFF_C)

                                   tco                   0.203      10.099 r       u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.waddr_msb/Q (GTP_DFF_C)
                                   net (fanout=1)        0.385      10.484         u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/wr_addr [4]
                                                                           r       u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0/mem/WADDR[4] (GTP_RAM32X1DP)

 Data arrival time                                                  10.484         Logic Levels: 0  
                                                                                   Logic: 0.203ns(34.524%), Route: 0.385ns(65.476%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0/mem/WCLK (GTP_RAM32X1DP)
 clock pessimism                                         0.000      10.224                          
 clock uncertainty                                       0.000      10.224                          

 Hold time                                               0.264      10.488                          

 Data required time                                                 10.488                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.488                          
 Data arrival time                                                  10.484                          
----------------------------------------------------------------------------------------------------
 Slack (VIOLATED)                                                   -0.004                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0/mem/WADDR[3] (GTP_RAM32X2DP)
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  10.224
  Launch Clock Delay      :  9.896
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115       7.308 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.628         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       8.796 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100       9.896         ddr_core_clk     
                                                                           r       u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (GTP_DFF_C)

                                   tco                   0.203      10.099 r       u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.waddr_msb/Q (GTP_DFF_C)
                                   net (fanout=1)        0.385      10.484         u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/wr_addr [3]
                                                                           r       u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0/mem/WADDR[3] (GTP_RAM32X2DP)

 Data arrival time                                                  10.484         Logic Levels: 0  
                                                                                   Logic: 0.203ns(34.524%), Route: 0.385ns(65.476%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0/mem/WCLK (GTP_RAM32X2DP)
 clock pessimism                                         0.000      10.224                          
 clock uncertainty                                       0.000      10.224                          

 Hold time                                               0.264      10.488                          

 Data required time                                                 10.488                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.488                          
 Data arrival time                                                  10.484                          
----------------------------------------------------------------------------------------------------
 Slack (VIOLATED)                                                   -0.004                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_vsync_pos/CLK (GTP_DFF_C)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C)
Path Group  : cmos1_pclk_16bit
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       cmos1_vsync_pos/CLK (GTP_DFF_C)

                                   tco                   0.203       9.701 r       cmos1_vsync_pos/Q (GTP_DFF_C)
                                   net (fanout=51)       0.686      10.387         cmos1_vsync_pos  
                                                                                   N716_0/I2 (GTP_LUT6CARRY)
                                   td                    0.125      10.512 r       N716_0/Z (GTP_LUT6CARRY)
                                   net (fanout=6)        0.519      11.031         fifo_wr_en       
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_1/I0 (GTP_LUT6CARRY)
                                   td                    0.159      11.190 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_1/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.190         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9958
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_2/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.212 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_2/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.212         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9959
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_3/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.234 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.234         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9960
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_4/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.256 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_4/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.256         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9961
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_5/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.278 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_5/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.278         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9962
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_6/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.300 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_6/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.300         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9963
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_7/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.322 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_7/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.322         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9964
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_8/CIN (GTP_LUT6CARRY)
                                   td                    0.068      11.390 r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_8/Z (GTP_LUT6CARRY)
                                   net (fanout=3)        0.467      11.857         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2 [7]
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N3[7]/I4 (GTP_LUT6D)
                                   td                    0.096      11.953 r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N3[7]/Z (GTP_LUT6D)
                                   net (fanout=1)        0.385      12.338         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/wwptr [7]
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N157.eq_3/I2 (GTP_LUT6CARRY)
                                   td                    0.159      12.497 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N157.eq_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      12.497         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N157.co [6]
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N157.eq_4/CIN (GTP_LUT6CARRY)
                                   td                    0.068      12.565 r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N157.eq_4/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      12.565         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N158
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C)

 Data arrival time                                                  12.565         Logic Levels: 5  
                                                                                   Logic: 1.010ns(32.931%), Route: 2.057ns(67.069%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                        47.620      47.620 r                        
 cmos1_pclk                                              0.000      47.620 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000      47.620         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960      48.580 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506      50.086         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229      50.315 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300      53.615         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203      53.818 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300      57.118         cmos1_pclk_16bit 
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      57.118                          
 clock uncertainty                                      -0.250      56.868                          

 Setup time                                             -0.136      56.732                          

 Data required time                                                 56.732                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 56.732                          
 Data arrival time                                                  12.565                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        44.167                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_vsync_pos/CLK (GTP_DFF_C)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wptr[9]/D (GTP_DFF_C)
Path Group  : cmos1_pclk_16bit
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       cmos1_vsync_pos/CLK (GTP_DFF_C)

                                   tco                   0.203       9.701 r       cmos1_vsync_pos/Q (GTP_DFF_C)
                                   net (fanout=51)       0.686      10.387         cmos1_vsync_pos  
                                                                                   N716_0/I2 (GTP_LUT6CARRY)
                                   td                    0.125      10.512 r       N716_0/Z (GTP_LUT6CARRY)
                                   net (fanout=6)        0.519      11.031         fifo_wr_en       
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_1/I0 (GTP_LUT6CARRY)
                                   td                    0.159      11.190 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_1/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.190         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9958
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_2/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.212 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_2/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.212         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9959
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_3/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.234 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.234         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9960
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_4/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.256 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_4/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.256         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9961
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_5/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.278 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_5/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.278         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9962
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_6/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.300 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_6/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.300         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9963
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_7/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.322 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_7/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.322         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9964
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_8/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.344 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_8/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.344         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9965
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_9/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.366 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_9/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.366         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9966
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_10/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.388 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_10/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.388         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9967
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_11/CIN (GTP_LUT6CARRY)
                                   td                    0.068      11.456 r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_11/Z (GTP_LUT6CARRY)
                                   net (fanout=3)        0.467      11.923         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2 [10]
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N3[9]/I2 (GTP_LUT6D)
                                   td                    0.212      12.135 r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N3[9]/Z5 (GTP_LUT6D)
                                   net (fanout=1)        0.000      12.135         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/wgnext [9]
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wptr[9]/D (GTP_DFF_C)

 Data arrival time                                                  12.135         Logic Levels: 5  
                                                                                   Logic: 0.965ns(36.595%), Route: 1.672ns(63.405%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                        47.620      47.620 r                        
 cmos1_pclk                                              0.000      47.620 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000      47.620         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960      48.580 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506      50.086         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229      50.315 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300      53.615         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203      53.818 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300      57.118         cmos1_pclk_16bit 
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      57.118                          
 clock uncertainty                                      -0.250      56.868                          

 Setup time                                             -0.136      56.732                          

 Data required time                                                 56.732                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 56.732                          
 Data arrival time                                                  12.135                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        44.597                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_vsync_pos/CLK (GTP_DFF_C)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wptr[10]/D (GTP_DFF_C)
Path Group  : cmos1_pclk_16bit
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       cmos1_vsync_pos/CLK (GTP_DFF_C)

                                   tco                   0.203       9.701 r       cmos1_vsync_pos/Q (GTP_DFF_C)
                                   net (fanout=51)       0.686      10.387         cmos1_vsync_pos  
                                                                                   N716_0/I2 (GTP_LUT6CARRY)
                                   td                    0.125      10.512 r       N716_0/Z (GTP_LUT6CARRY)
                                   net (fanout=6)        0.519      11.031         fifo_wr_en       
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_1/I0 (GTP_LUT6CARRY)
                                   td                    0.159      11.190 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_1/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.190         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9958
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_2/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.212 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_2/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.212         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9959
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_3/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.234 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_3/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.234         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9960
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_4/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.256 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_4/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.256         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9961
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_5/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.278 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_5/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.278         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9962
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_6/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.300 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_6/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.300         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9963
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_7/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.322 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_7/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.322         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9964
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_8/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.344 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_8/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.344         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9965
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_9/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.366 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_9/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.366         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9966
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_10/CIN (GTP_LUT6CARRY)
                                   td                    0.022      11.388 f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_10/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000      11.388         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/_N9967
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_11/CIN (GTP_LUT6CARRY)
                                   td                    0.068      11.456 r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2_11/Z (GTP_LUT6CARRY)
                                   net (fanout=3)        0.467      11.923         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N2 [10]
                                                                                   u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N155_eq0/I1 (GTP_LUT6D)
                                   td                    0.212      12.135 r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/N155_eq0/Z5 (GTP_LUT6D)
                                   net (fanout=1)        0.000      12.135         u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/wwptr [10]
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wptr[10]/D (GTP_DFF_C)

 Data arrival time                                                  12.135         Logic Levels: 5  
                                                                                   Logic: 0.965ns(36.595%), Route: 1.672ns(63.405%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                        47.620      47.620 r                        
 cmos1_pclk                                              0.000      47.620 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000      47.620         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960      48.580 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506      50.086         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229      50.315 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300      53.615         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203      53.818 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300      57.118         cmos1_pclk_16bit 
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      57.118                          
 clock uncertainty                                      -0.250      56.868                          

 Setup time                                             -0.136      56.732                          

 Data required time                                                 56.732                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 56.732                          
 Data arrival time                                                  12.135                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        44.597                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_8_16bit/de_out3/CLK (GTP_DFF)
Endpoint    : cmos1_8_16bit/de_o/D (GTP_DFF)
Path Group  : cmos1_pclk_16bit
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       cmos1_8_16bit/de_out3/CLK (GTP_DFF)

                                   tco                   0.185       9.683 f       cmos1_8_16bit/de_out3/Q (GTP_DFF)
                                   net (fanout=1)        0.385      10.068         cmos1_8_16bit/de_out3
                                                                           f       cmos1_8_16bit/de_o/D (GTP_DFF)

 Data arrival time                                                  10.068         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       cmos1_8_16bit/de_o/CLK (GTP_DFF)
 clock pessimism                                         0.000       9.498                          
 clock uncertainty                                       0.200       9.698                          

 Hold time                                              -0.049       9.649                          

 Data required time                                                  9.649                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  9.649                          
 Data arrival time                                                  10.068                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.419                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_8_16bit/de_out2/CLK (GTP_DFF)
Endpoint    : cmos1_8_16bit/de_out3/D (GTP_DFF)
Path Group  : cmos1_pclk_16bit
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       cmos1_8_16bit/de_out2/CLK (GTP_DFF)

                                   tco                   0.185       9.683 f       cmos1_8_16bit/de_out2/Q (GTP_DFF)
                                   net (fanout=1)        0.385      10.068         cmos1_8_16bit/de_out2
                                                                           f       cmos1_8_16bit/de_out3/D (GTP_DFF)

 Data arrival time                                                  10.068         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       cmos1_8_16bit/de_out3/CLK (GTP_DFF)
 clock pessimism                                         0.000       9.498                          
 clock uncertainty                                       0.200       9.698                          

 Hold time                                              -0.049       9.649                          

 Data required time                                                  9.649                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  9.649                          
 Data arrival time                                                  10.068                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.419                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_8_16bit/pdata_out3[0]/CLK (GTP_DFF)
Endpoint    : cmos1_8_16bit/pdata_o[0]/D (GTP_DFF)
Path Group  : cmos1_pclk_16bit
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       cmos1_8_16bit/pdata_out3[0]/CLK (GTP_DFF)

                                   tco                   0.185       9.683 f       cmos1_8_16bit/pdata_out3[0]/Q (GTP_DFF)
                                   net (fanout=1)        0.385      10.068         cmos1_8_16bit/pdata_out3 [0]
                                                                           f       cmos1_8_16bit/pdata_o[0]/D (GTP_DFF)

 Data arrival time                                                  10.068         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       cmos1_8_16bit/pdata_o[0]/CLK (GTP_DFF)
 clock pessimism                                         0.000       9.498                          
 clock uncertainty                                       0.200       9.698                          

 Hold time                                              -0.049       9.649                          

 Data required time                                                  9.649                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  9.649                          
 Data arrival time                                                  10.068                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.419                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/cnt2[5]/CLK (GTP_DFF_RE)
Endpoint    : power_on_delay_inst/cnt2[0]/CE (GTP_DFF_RE)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.912
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066       2.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420       4.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt2[5]/CLK (GTP_DFF_RE)

                                   tco                   0.203       5.115 r       power_on_delay_inst/cnt2[5]/Q (GTP_DFF_RE)
                                   net (fanout=2)        0.437       5.552         power_on_delay_inst/cnt2 [5]
                                                                                   power_on_delay_inst/N15_mux15_11/I0 (GTP_LUT6CARRY)
                                   td                    0.204       5.756 r       power_on_delay_inst/N15_mux15_11/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.756         power_on_delay_inst/_N59023_co
                                                                                   power_on_delay_inst/N15_mux15_17/CIN (GTP_LUT6CARRY)
                                   td                    0.068       5.824 r       power_on_delay_inst/N15_mux15_17/Z (GTP_LUT6CARRY)
                                   net (fanout=2)        0.437       6.261         power_on_delay_inst/_N59026
                                                                                   power_on_delay_inst/N15_inv/I5 (GTP_LUT6)
                                   td                    0.074       6.335 r       power_on_delay_inst/N15_inv/Z (GTP_LUT6)
                                   net (fanout=16)       0.489       6.824         power_on_delay_inst/N15
                                                                           r       power_on_delay_inst/cnt2[0]/CE (GTP_DFF_RE)

 Data arrival time                                                   6.824         Logic Levels: 2  
                                                                                   Logic: 0.549ns(28.713%), Route: 1.363ns(71.287%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                        20.000      20.000 r                        
 sys_clk                                                 0.000      20.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      20.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      20.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      22.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066      22.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420      24.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt2[0]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000      24.912                          
 clock uncertainty                                      -0.150      24.762                          

 Setup time                                             -0.226      24.536                          

 Data required time                                                 24.536                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 24.536                          
 Data arrival time                                                   6.824                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        17.712                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/cnt2[5]/CLK (GTP_DFF_RE)
Endpoint    : power_on_delay_inst/cnt2[1]/CE (GTP_DFF_RE)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.912
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066       2.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420       4.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt2[5]/CLK (GTP_DFF_RE)

                                   tco                   0.203       5.115 r       power_on_delay_inst/cnt2[5]/Q (GTP_DFF_RE)
                                   net (fanout=2)        0.437       5.552         power_on_delay_inst/cnt2 [5]
                                                                                   power_on_delay_inst/N15_mux15_11/I0 (GTP_LUT6CARRY)
                                   td                    0.204       5.756 r       power_on_delay_inst/N15_mux15_11/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.756         power_on_delay_inst/_N59023_co
                                                                                   power_on_delay_inst/N15_mux15_17/CIN (GTP_LUT6CARRY)
                                   td                    0.068       5.824 r       power_on_delay_inst/N15_mux15_17/Z (GTP_LUT6CARRY)
                                   net (fanout=2)        0.437       6.261         power_on_delay_inst/_N59026
                                                                                   power_on_delay_inst/N15_inv/I5 (GTP_LUT6)
                                   td                    0.074       6.335 r       power_on_delay_inst/N15_inv/Z (GTP_LUT6)
                                   net (fanout=16)       0.489       6.824         power_on_delay_inst/N15
                                                                           r       power_on_delay_inst/cnt2[1]/CE (GTP_DFF_RE)

 Data arrival time                                                   6.824         Logic Levels: 2  
                                                                                   Logic: 0.549ns(28.713%), Route: 1.363ns(71.287%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                        20.000      20.000 r                        
 sys_clk                                                 0.000      20.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      20.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      20.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      22.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066      22.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420      24.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt2[1]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000      24.912                          
 clock uncertainty                                      -0.150      24.762                          

 Setup time                                             -0.226      24.536                          

 Data required time                                                 24.536                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 24.536                          
 Data arrival time                                                   6.824                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        17.712                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/cnt2[5]/CLK (GTP_DFF_RE)
Endpoint    : power_on_delay_inst/cnt2[2]/CE (GTP_DFF_RE)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.912
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066       2.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420       4.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt2[5]/CLK (GTP_DFF_RE)

                                   tco                   0.203       5.115 r       power_on_delay_inst/cnt2[5]/Q (GTP_DFF_RE)
                                   net (fanout=2)        0.437       5.552         power_on_delay_inst/cnt2 [5]
                                                                                   power_on_delay_inst/N15_mux15_11/I0 (GTP_LUT6CARRY)
                                   td                    0.204       5.756 r       power_on_delay_inst/N15_mux15_11/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.756         power_on_delay_inst/_N59023_co
                                                                                   power_on_delay_inst/N15_mux15_17/CIN (GTP_LUT6CARRY)
                                   td                    0.068       5.824 r       power_on_delay_inst/N15_mux15_17/Z (GTP_LUT6CARRY)
                                   net (fanout=2)        0.437       6.261         power_on_delay_inst/_N59026
                                                                                   power_on_delay_inst/N15_inv/I5 (GTP_LUT6)
                                   td                    0.074       6.335 r       power_on_delay_inst/N15_inv/Z (GTP_LUT6)
                                   net (fanout=16)       0.489       6.824         power_on_delay_inst/N15
                                                                           r       power_on_delay_inst/cnt2[2]/CE (GTP_DFF_RE)

 Data arrival time                                                   6.824         Logic Levels: 2  
                                                                                   Logic: 0.549ns(28.713%), Route: 1.363ns(71.287%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                        20.000      20.000 r                        
 sys_clk                                                 0.000      20.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      20.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      20.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      22.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066      22.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420      24.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt2[2]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000      24.912                          
 clock uncertainty                                      -0.150      24.762                          

 Setup time                                             -0.226      24.536                          

 Data required time                                                 24.536                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 24.536                          
 Data arrival time                                                   6.824                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        17.712                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/cnt1[3]/CLK (GTP_DFF_RE)
Endpoint    : power_on_delay_inst/cnt1[3]/D (GTP_DFF_RE)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.912
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066       2.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420       4.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt1[3]/CLK (GTP_DFF_RE)

                                   tco                   0.185       5.097 f       power_on_delay_inst/cnt1[3]/Q (GTP_DFF_RE)
                                   net (fanout=1)        0.385       5.482         power_on_delay_inst/cnt1 [3]
                                                                                   power_on_delay_inst/N5_1_3/I0 (GTP_LUT6CARRY)
                                   td                    0.096       5.578 r       power_on_delay_inst/N5_1_3/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.578         power_on_delay_inst/N5 [3]
                                                                           r       power_on_delay_inst/cnt1[3]/D (GTP_DFF_RE)

 Data arrival time                                                   5.578         Logic Levels: 1  
                                                                                   Logic: 0.281ns(42.192%), Route: 0.385ns(57.808%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066       2.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420       4.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt1[3]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000       4.912                          
 clock uncertainty                                       0.000       4.912                          

 Hold time                                              -0.040       4.872                          

 Data required time                                                  4.872                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.872                          
 Data arrival time                                                   5.578                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.706                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/cnt1[4]/CLK (GTP_DFF_RE)
Endpoint    : power_on_delay_inst/cnt1[4]/D (GTP_DFF_RE)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.912
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066       2.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420       4.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt1[4]/CLK (GTP_DFF_RE)

                                   tco                   0.185       5.097 f       power_on_delay_inst/cnt1[4]/Q (GTP_DFF_RE)
                                   net (fanout=1)        0.385       5.482         power_on_delay_inst/cnt1 [4]
                                                                                   power_on_delay_inst/N5_1_4/I0 (GTP_LUT6CARRY)
                                   td                    0.096       5.578 r       power_on_delay_inst/N5_1_4/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.578         power_on_delay_inst/N5 [4]
                                                                           r       power_on_delay_inst/cnt1[4]/D (GTP_DFF_RE)

 Data arrival time                                                   5.578         Logic Levels: 1  
                                                                                   Logic: 0.281ns(42.192%), Route: 0.385ns(57.808%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066       2.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420       4.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt1[4]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000       4.912                          
 clock uncertainty                                       0.000       4.912                          

 Hold time                                              -0.040       4.872                          

 Data required time                                                  4.872                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.872                          
 Data arrival time                                                   5.578                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.706                          
====================================================================================================

====================================================================================================

Startpoint  : power_on_delay_inst/cnt1[5]/CLK (GTP_DFF_RE)
Endpoint    : power_on_delay_inst/cnt1[5]/D (GTP_DFF_RE)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.912
  Launch Clock Delay      :  4.912
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066       2.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420       4.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt1[5]/CLK (GTP_DFF_RE)

                                   tco                   0.185       5.097 f       power_on_delay_inst/cnt1[5]/Q (GTP_DFF_RE)
                                   net (fanout=1)        0.385       5.482         power_on_delay_inst/cnt1 [5]
                                                                                   power_on_delay_inst/N5_1_5/I0 (GTP_LUT6CARRY)
                                   td                    0.096       5.578 r       power_on_delay_inst/N5_1_5/Z (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.578         power_on_delay_inst/N5 [5]
                                                                           r       power_on_delay_inst/cnt1[5]/D (GTP_DFF_RE)

 Data arrival time                                                   5.578         Logic Levels: 1  
                                                                                   Logic: 0.281ns(42.192%), Route: 0.385ns(57.808%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.066       2.492 r       u_PLL/u_gpll/CLKOUT1 (GTP_GPLL)
                                   net (fanout=37)       2.420       4.912         clk_50M          
                                                                           r       power_on_delay_inst/cnt1[5]/CLK (GTP_DFF_RE)
 clock pessimism                                         0.000       4.912                          
 clock uncertainty                                       0.000       4.912                          

 Hold time                                              -0.040       4.872                          

 Data required time                                                  4.872                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.872                          
 Data arrival time                                                   5.578                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.706                          
====================================================================================================

====================================================================================================

Startpoint  : u_SXT1_FIFO_to_PCIe/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/CLKB (GTP_DRM36K_E1)
Endpoint    : cmos1_vsync_pos_1/D (GTP_DFF_C)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.910
  Launch Clock Delay      :  4.910
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420       4.910         clk_100m         
                                                                           r       u_SXT1_FIFO_to_PCIe/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/CLKB (GTP_DRM36K_E1)

                                   tco                   1.565       6.475 r       u_SXT1_FIFO_to_PCIe/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/DOB[28] (GTP_DRM36K_E1)
                                   net (fanout=2)        1.152       7.627         ddr_fifo_rd_data[25]
                                                                                   N1071_8/I0 (GTP_LUT6)
                                   td                    0.114       7.741 r       N1071_8/Z (GTP_LUT6)
                                   net (fanout=1)        0.385       8.126         _N58684          
                                                                                   N1077_1/I5 (GTP_LUT6)
                                   td                    0.189       8.315 r       N1077_1/Z (GTP_LUT6)
                                   net (fanout=1)        0.385       8.700         _N59169          
                                                                                   cmos1_vsync_pos_1_ce_mux_1/I4 (GTP_LUT5)
                                   td                    0.096       8.796 r       cmos1_vsync_pos_1_ce_mux_1/Z (GTP_LUT5)
                                   net (fanout=1)        0.000       8.796         _N55717          
                                                                           r       cmos1_vsync_pos_1/D (GTP_DFF_C)

 Data arrival time                                                   8.796         Logic Levels: 3  
                                                                                   Logic: 1.964ns(50.540%), Route: 1.922ns(49.460%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                        10.000      10.000 r                        
 sys_clk                                                 0.000      10.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      10.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      10.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      12.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064      12.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420      14.910         clk_100m         
                                                                           r       cmos1_vsync_pos_1/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      14.910                          
 clock uncertainty                                      -0.150      14.760                          

 Setup time                                             -0.136      14.624                          

 Data required time                                                 14.624                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 14.624                          
 Data arrival time                                                   8.796                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         5.828                          
====================================================================================================

====================================================================================================

Startpoint  : bar0_wr_addr[2]/CLK (GTP_DFF_CE)
Endpoint    : bar0_wr_data[0]/CE (GTP_DFF_CE)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.910
  Launch Clock Delay      :  4.910
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420       4.910         clk_100m         
                                                                           r       bar0_wr_addr[2]/CLK (GTP_DFF_CE)

                                   tco                   0.203       5.113 r       bar0_wr_addr[2]/Q (GTP_DFF_CE)
                                   net (fanout=33)       0.646       5.759         bar0_wr_addr[2]  
                                                                                   N764_8/I0 (GTP_LUT6CARRY)
                                   td                    0.204       5.963 r       N764_8/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.963         _N57069          
                                                                                   N764_9/CIN (GTP_LUT6CARRY)
                                   td                    0.068       6.031 r       N764_9/Z (GTP_LUT6CARRY)
                                   net (fanout=4)        0.489       6.520         N1308[1]         
                                                                                   N135_4/I1 (GTP_LUT6)
                                   td                    0.074       6.594 r       N135_4/Z (GTP_LUT6)
                                   net (fanout=4)        0.489       7.083         _N50573          
                                                                                   N921_1/I3 (GTP_LUT6D)
                                   td                    0.108       7.191 r       N921_1/Z (GTP_LUT6D)
                                   net (fanout=128)      0.644       7.835         N921             
                                                                           r       bar0_wr_data[0]/CE (GTP_DFF_CE)

 Data arrival time                                                   7.835         Logic Levels: 3  
                                                                                   Logic: 0.657ns(22.462%), Route: 2.268ns(77.538%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                        10.000      10.000 r                        
 sys_clk                                                 0.000      10.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      10.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      10.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      12.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064      12.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420      14.910         clk_100m         
                                                                           r       bar0_wr_data[0]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      14.910                          
 clock uncertainty                                      -0.150      14.760                          

 Setup time                                             -0.226      14.534                          

 Data required time                                                 14.534                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 14.534                          
 Data arrival time                                                   7.835                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         6.699                          
====================================================================================================

====================================================================================================

Startpoint  : bar0_wr_addr[2]/CLK (GTP_DFF_CE)
Endpoint    : bar0_wr_data[1]/CE (GTP_DFF_CE)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.910
  Launch Clock Delay      :  4.910
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420       4.910         clk_100m         
                                                                           r       bar0_wr_addr[2]/CLK (GTP_DFF_CE)

                                   tco                   0.203       5.113 r       bar0_wr_addr[2]/Q (GTP_DFF_CE)
                                   net (fanout=33)       0.646       5.759         bar0_wr_addr[2]  
                                                                                   N764_8/I0 (GTP_LUT6CARRY)
                                   td                    0.204       5.963 r       N764_8/COUT (GTP_LUT6CARRY)
                                   net (fanout=1)        0.000       5.963         _N57069          
                                                                                   N764_9/CIN (GTP_LUT6CARRY)
                                   td                    0.068       6.031 r       N764_9/Z (GTP_LUT6CARRY)
                                   net (fanout=4)        0.489       6.520         N1308[1]         
                                                                                   N135_4/I1 (GTP_LUT6)
                                   td                    0.074       6.594 r       N135_4/Z (GTP_LUT6)
                                   net (fanout=4)        0.489       7.083         _N50573          
                                                                                   N921_1/I3 (GTP_LUT6D)
                                   td                    0.108       7.191 r       N921_1/Z (GTP_LUT6D)
                                   net (fanout=128)      0.644       7.835         N921             
                                                                           r       bar0_wr_data[1]/CE (GTP_DFF_CE)

 Data arrival time                                                   7.835         Logic Levels: 3  
                                                                                   Logic: 0.657ns(22.462%), Route: 2.268ns(77.538%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                        10.000      10.000 r                        
 sys_clk                                                 0.000      10.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      10.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      10.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      12.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064      12.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420      14.910         clk_100m         
                                                                           r       bar0_wr_data[1]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      14.910                          
 clock uncertainty                                      -0.150      14.760                          

 Setup time                                             -0.226      14.534                          

 Data required time                                                 14.534                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 14.534                          
 Data arrival time                                                   7.835                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         6.699                          
====================================================================================================

====================================================================================================

Startpoint  : blk_state_reg[3]/CLK (GTP_DFF_CE)
Endpoint    : blk_state_reg[0]/D (GTP_DFF_PE)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.910
  Launch Clock Delay      :  4.910
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420       4.910         clk_100m         
                                                                           r       blk_state_reg[3]/CLK (GTP_DFF_CE)

                                   tco                   0.185       5.095 f       blk_state_reg[3]/Q (GTP_DFF_CE)
                                   net (fanout=1)        0.385       5.480         blk_state_reg[3] 
                                                                           f       blk_state_reg[0]/D (GTP_DFF_PE)

 Data arrival time                                                   5.480         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420       4.910         clk_100m         
                                                                           r       blk_state_reg[0]/CLK (GTP_DFF_PE)
 clock pessimism                                         0.000       4.910                          
 clock uncertainty                                       0.000       4.910                          

 Hold time                                              -0.049       4.861                          

 Data required time                                                  4.861                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.861                          
 Data arrival time                                                   5.480                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.619                          
====================================================================================================

====================================================================================================

Startpoint  : i2cSlave_u/rstPipe[0]/CLK (GTP_DFF)
Endpoint    : i2cSlave_u/rstPipe[1]/D (GTP_DFF_S)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.910
  Launch Clock Delay      :  4.910
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420       4.910         clk_100m         
                                                                           r       i2cSlave_u/rstPipe[0]/CLK (GTP_DFF)

                                   tco                   0.185       5.095 f       i2cSlave_u/rstPipe[0]/Q (GTP_DFF)
                                   net (fanout=1)        0.385       5.480         i2cSlave_u/rstPipe [0]
                                                                           f       i2cSlave_u/rstPipe[1]/D (GTP_DFF_S)

 Data arrival time                                                   5.480         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420       4.910         clk_100m         
                                                                           r       i2cSlave_u/rstPipe[1]/CLK (GTP_DFF_S)
 clock pessimism                                         0.000       4.910                          
 clock uncertainty                                       0.000       4.910                          

 Hold time                                              -0.049       4.861                          

 Data required time                                                  4.861                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.861                          
 Data arrival time                                                   5.480                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.619                          
====================================================================================================

====================================================================================================

Startpoint  : i2cSlave_u/sclDelayed[0]/CLK (GTP_DFF_S)
Endpoint    : i2cSlave_u/sclDelayed[1]/D (GTP_DFF_S)
Path Group  : sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.910
  Launch Clock Delay      :  4.910
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420       4.910         clk_100m         
                                                                           r       i2cSlave_u/sclDelayed[0]/CLK (GTP_DFF_S)

                                   tco                   0.185       5.095 f       i2cSlave_u/sclDelayed[0]/Q (GTP_DFF_S)
                                   net (fanout=1)        0.385       5.480         i2cSlave_u/sclDelayed [0]
                                                                           f       i2cSlave_u/sclDelayed[1]/D (GTP_DFF_S)

 Data arrival time                                                   5.480         Logic Levels: 0  
                                                                                   Logic: 0.185ns(32.456%), Route: 0.385ns(67.544%)
----------------------------------------------------------------------------------------------------

 Clock sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred (rising edge)
                                                         0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_PLL/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_PLL/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=396)      2.420       4.910         clk_100m         
                                                                           r       i2cSlave_u/sclDelayed[1]/CLK (GTP_DFF_S)
 clock pessimism                                         0.000       4.910                          
 clock uncertainty                                       0.000       4.910                          

 Hold time                                              -0.049       4.861                          

 Data required time                                                  4.861                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.861                          
 Data arrival time                                                   5.480                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.619                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/CLK (GTP_DFF_C)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K_E1/RSTA (GTP_DRM18K_E1)
Path Group  : pclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/CLK (GTP_DFF_C)

                                   tco                   0.203       3.503 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       3.503         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/s_mem_rst_n
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/N13/I (GTP_INV)
                                   td                    0.000       3.503 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/N13/Z (GTP_INV)
                                   net (fanout=32)       1.359       4.862         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/N13
                                                                           f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K_E1/RSTA (GTP_DRM18K_E1)

 Data arrival time                                                   4.862         Logic Levels: 1  
                                                                                   Logic: 0.203ns(12.996%), Route: 1.359ns(87.004%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                4.000       4.000 r                        
                                                         0.000       4.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       7.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K_E1/CLKA (GTP_DRM18K_E1)
 clock pessimism                                         0.000       7.300                          
 clock uncertainty                                      -0.050       7.250                          

 Recovery time                                          -0.395       6.855                          

 Data required time                                                  6.855                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  6.855                          
 Data arrival time                                                   4.862                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.993                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/CLK (GTP_DFF_C)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K_E1/RSTB (GTP_DRM18K_E1)
Path Group  : pclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/CLK (GTP_DFF_C)

                                   tco                   0.203       3.503 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       3.503         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/s_mem_rst_n
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/N13/I (GTP_INV)
                                   td                    0.000       3.503 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/N13/Z (GTP_INV)
                                   net (fanout=32)       1.359       4.862         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/N13
                                                                           f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K_E1/RSTB (GTP_DRM18K_E1)

 Data arrival time                                                   4.862         Logic Levels: 1  
                                                                                   Logic: 0.203ns(12.996%), Route: 1.359ns(87.004%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                4.000       4.000 r                        
                                                         0.000       4.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       7.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K_E1/CLKB (GTP_DRM18K_E1)
 clock pessimism                                         0.000       7.300                          
 clock uncertainty                                      -0.050       7.250                          

 Recovery time                                          -0.395       6.855                          

 Data required time                                                  6.855                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  6.855                          
 Data arrival time                                                   4.862                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.993                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/CLK (GTP_DFF_C)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K_E1/RSTA (GTP_DRM18K_E1)
Path Group  : pclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/CLK (GTP_DFF_C)

                                   tco                   0.203       3.503 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/mem_button_rstn_sync/sig_synced/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       3.503         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/s_mem_rst_n
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/N13/I (GTP_INV)
                                   td                    0.000       3.503 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/N13/Z (GTP_INV)
                                   net (fanout=32)       1.359       4.862         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/N13
                                                                           f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K_E1/RSTA (GTP_DRM18K_E1)

 Data arrival time                                                   4.862         Logic Levels: 1  
                                                                                   Logic: 0.203ns(12.996%), Route: 1.359ns(87.004%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                4.000       4.000 r                        
                                                         0.000       4.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       7.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K_E1/CLKA (GTP_DRM18K_E1)
 clock pessimism                                         0.000       7.300                          
 clock uncertainty                                      -0.050       7.250                          

 Recovery time                                          -0.395       6.855                          

 Data required time                                                  6.855                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  6.855                          
 Data arrival time                                                   4.862                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.993                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/CLK (GTP_DFF_C)
Endpoint    : pclk_led/P (GTP_DFF_PE)
Path Group  : pclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/CLK (GTP_DFF_C)

                                   tco                   0.203       3.503 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       3.503         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem_rnmt
                                                                                   N456/I (GTP_INV) 
                                   td                    0.000       3.503 f       N456/Z (GTP_INV) 
                                   net (fanout=97)       0.626       4.129         N456             
                                                                           f       pclk_led/P (GTP_DFF_PE)

 Data arrival time                                                   4.129         Logic Levels: 1  
                                                                                   Logic: 0.203ns(24.487%), Route: 0.626ns(75.513%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       pclk_led/CLK (GTP_DFF_PE)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Removal time                                           -0.064       3.236                          

 Data required time                                                  3.236                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.236                          
 Data arrival time                                                   4.129                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.893                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/CLK (GTP_DFF_C)
Endpoint    : pclk_led_cnt[0]/C (GTP_DFF_CE)
Path Group  : pclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/CLK (GTP_DFF_C)

                                   tco                   0.203       3.503 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       3.503         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem_rnmt
                                                                                   N456/I (GTP_INV) 
                                   td                    0.000       3.503 f       N456/Z (GTP_INV) 
                                   net (fanout=97)       0.626       4.129         N456             
                                                                           f       pclk_led_cnt[0]/C (GTP_DFF_CE)

 Data arrival time                                                   4.129         Logic Levels: 1  
                                                                                   Logic: 0.203ns(24.487%), Route: 0.626ns(75.513%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       pclk_led_cnt[0]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Removal time                                           -0.064       3.236                          

 Data required time                                                  3.236                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.236                          
 Data arrival time                                                   4.129                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.893                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/CLK (GTP_DFF_C)
Endpoint    : pclk_led_cnt[1]/C (GTP_DFF_CE)
Path Group  : pclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/CLK (GTP_DFF_C)

                                   tco                   0.203       3.503 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       3.503         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem_rnmt
                                                                                   N456/I (GTP_INV) 
                                   td                    0.000       3.503 f       N456/Z (GTP_INV) 
                                   net (fanout=97)       0.626       4.129         N456             
                                                                           f       pclk_led_cnt[1]/C (GTP_DFF_CE)

 Data arrival time                                                   4.129         Logic Levels: 1  
                                                                                   Logic: 0.203ns(24.487%), Route: 0.626ns(75.513%)
----------------------------------------------------------------------------------------------------

 Clock pclk (rising edge)                                0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL1_ENABLE.U_GTP_HSSTLP_LANE1/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=137)      3.300       3.300         pclk             
                                                                           r       pclk_led_cnt[1]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Removal time                                           -0.064       3.236                          

 Data required time                                                  3.236                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.236                          
 Data arrival time                                                   4.129                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.893                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/dma_cmd_h_addr[0]/C (GTP_DFF_CE)
Path Group  : pclk_div2
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)

                                   tco                   1.174       4.474 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/CORE_RST_N (GTP_PCIEGEN2)
                                   net (fanout=1)        0.000       4.474         core_rst_n       
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/N3/I (GTP_INV)
                                   td                    0.000       4.474 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/N3/Z (GTP_INV)
                                   net (fanout=2935)     2.940       7.414         u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/N3
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/dma_cmd_h_addr[0]/C (GTP_DFF_CE)

 Data arrival time                                                   7.414         Logic Levels: 1  
                                                                                   Logic: 1.174ns(28.537%), Route: 2.940ns(71.463%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           8.000       8.000 r                        
                                                         0.000       8.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300      11.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/dma_cmd_h_addr[0]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      11.300                          
 clock uncertainty                                      -0.050      11.250                          

 Recovery time                                          -0.226      11.024                          

 Data required time                                                 11.024                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.024                          
 Data arrival time                                                   7.414                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.610                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/dma_cmd_h_addr[1]/C (GTP_DFF_CE)
Path Group  : pclk_div2
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)

                                   tco                   1.174       4.474 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/CORE_RST_N (GTP_PCIEGEN2)
                                   net (fanout=1)        0.000       4.474         core_rst_n       
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/N3/I (GTP_INV)
                                   td                    0.000       4.474 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/N3/Z (GTP_INV)
                                   net (fanout=2935)     2.940       7.414         u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/N3
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/dma_cmd_h_addr[1]/C (GTP_DFF_CE)

 Data arrival time                                                   7.414         Logic Levels: 1  
                                                                                   Logic: 1.174ns(28.537%), Route: 2.940ns(71.463%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           8.000       8.000 r                        
                                                         0.000       8.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300      11.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/dma_cmd_h_addr[1]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      11.300                          
 clock uncertainty                                      -0.050      11.250                          

 Recovery time                                          -0.226      11.024                          

 Data required time                                                 11.024                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.024                          
 Data arrival time                                                   7.414                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.610                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/dma_cmd_h_addr[2]/C (GTP_DFF_CE)
Path Group  : pclk_div2
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)

                                   tco                   1.174       4.474 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/CORE_RST_N (GTP_PCIEGEN2)
                                   net (fanout=1)        0.000       4.474         core_rst_n       
                                                                                   u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/N3/I (GTP_INV)
                                   td                    0.000       4.474 r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/N3/Z (GTP_INV)
                                   net (fanout=2935)     2.940       7.414         u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/N3
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/dma_cmd_h_addr[2]/C (GTP_DFF_CE)

 Data arrival time                                                   7.414         Logic Levels: 1  
                                                                                   Logic: 1.174ns(28.537%), Route: 2.940ns(71.463%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           8.000       8.000 r                        
                                                         0.000       8.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300      11.300         pclk_div2        
                                                                           r       u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/dma_cmd_h_addr[2]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      11.300                          
 clock uncertainty                                      -0.050      11.250                          

 Recovery time                                          -0.226      11.024                          

 Data required time                                                 11.024                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.024                          
 Data arrival time                                                   7.414                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.610                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[0]/C (GTP_DFF_C)
Path Group  : pclk_div2
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)

                                   tco                   0.943       4.243 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PHY_RST_N (GTP_PCIEGEN2)
                                   net (fanout=1)        0.000       4.243         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/phy_rst_n
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N37/I (GTP_INV)
                                   td                    0.000       4.243 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N37/Z (GTP_INV)
                                   net (fanout=195)      2.276       6.519         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N37
                                                                           f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[0]/C (GTP_DFF_C)

 Data arrival time                                                   6.519         Logic Levels: 1  
                                                                                   Logic: 0.943ns(29.295%), Route: 2.276ns(70.705%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[0]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Removal time                                           -0.064       3.236                          

 Data required time                                                  3.236                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.236                          
 Data arrival time                                                   6.519                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.283                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[1]/C (GTP_DFF_C)
Path Group  : pclk_div2
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)

                                   tco                   0.943       4.243 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PHY_RST_N (GTP_PCIEGEN2)
                                   net (fanout=1)        0.000       4.243         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/phy_rst_n
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N37/I (GTP_INV)
                                   td                    0.000       4.243 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N37/Z (GTP_INV)
                                   net (fanout=195)      2.276       6.519         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N37
                                                                           f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[1]/C (GTP_DFF_C)

 Data arrival time                                                   6.519         Logic Levels: 1  
                                                                                   Logic: 0.943ns(29.295%), Route: 2.276ns(70.705%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[1]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Removal time                                           -0.064       3.236                          

 Data required time                                                  3.236                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.236                          
 Data arrival time                                                   6.519                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.283                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[2]/C (GTP_DFF_C)
Path Group  : pclk_div2
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.300
  Launch Clock Delay      :  3.300
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PCLK_DIV2 (GTP_PCIEGEN2)

                                   tco                   0.943       4.243 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_gtp_pcie/PHY_RST_N (GTP_PCIEGEN2)
                                   net (fanout=1)        0.000       4.243         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/phy_rst_n
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N37/I (GTP_INV)
                                   td                    0.000       4.243 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N37/Z (GTP_INV)
                                   net (fanout=195)      2.276       6.519         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N37
                                                                           f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[2]/C (GTP_DFF_C)

 Data arrival time                                                   6.519         Logic Levels: 1  
                                                                                   Logic: 0.943ns(29.295%), Route: 2.276ns(70.705%)
----------------------------------------------------------------------------------------------------

 Clock pclk_div2 (rising edge)                           0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/x2.GTP_HSST_2LANE_TOP/U_GTP_HSSTLP_WRAPPER/CHANNEL0_ENABLE.U_GTP_HSSTLP_LANE0/P_TCLK2FABRIC (GTP_HSSTLP_LANE)
                                   net (fanout=3705)     3.300       3.300         pclk_div2        
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[2]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000       3.300                          
 clock uncertainty                                       0.000       3.300                          

 Removal time                                           -0.064       3.236                          

 Data required time                                                  3.236                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.236                          
 Data arrival time                                                   6.519                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.283                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rstn_out/CLK (GTP_DFF_C)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_LANE_SYNC/C (GTP_DFF_C)
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rstn_out/CLK (GTP_DFF_C)

                                   tco                   0.203       1.303 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rstn_out/Q (GTP_DFF_C)
                                   net (fanout=2)        0.679       1.982         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rst_n_sync
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N0/I1 (GTP_LUT2)
                                   td                    0.224       2.206 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N0/Z (GTP_LUT2)
                                   net (fanout=38)       0.557       2.763         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N0
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_LANE_SYNC/C (GTP_DFF_C)

 Data arrival time                                                   2.763         Logic Levels: 1  
                                                                                   Logic: 0.427ns(25.676%), Route: 1.236ns(74.324%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            10.000      10.000 r                        
                                                         0.000      10.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100      11.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_LANE_SYNC/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      11.100                          
 clock uncertainty                                      -0.050      11.050                          

 Recovery time                                          -0.226      10.824                          

 Data required time                                                 10.824                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.824                          
 Data arrival time                                                   2.763                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         8.061                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rstn_out/CLK (GTP_DFF_C)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_PCS_TX_RST/P (GTP_DFF_P)
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rstn_out/CLK (GTP_DFF_C)

                                   tco                   0.203       1.303 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rstn_out/Q (GTP_DFF_C)
                                   net (fanout=2)        0.679       1.982         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rst_n_sync
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N0/I1 (GTP_LUT2)
                                   td                    0.224       2.206 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N0/Z (GTP_LUT2)
                                   net (fanout=38)       0.557       2.763         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N0
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_PCS_TX_RST/P (GTP_DFF_P)

 Data arrival time                                                   2.763         Logic Levels: 1  
                                                                                   Logic: 0.427ns(25.676%), Route: 1.236ns(74.324%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            10.000      10.000 r                        
                                                         0.000      10.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100      11.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_PCS_TX_RST/CLK (GTP_DFF_P)
 clock pessimism                                         0.000      11.100                          
 clock uncertainty                                      -0.050      11.050                          

 Recovery time                                          -0.226      10.824                          

 Data required time                                                 10.824                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.824                          
 Data arrival time                                                   2.763                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         8.061                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rstn_out/CLK (GTP_DFF_C)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_PLLPOWERDOWN/P (GTP_DFF_P)
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rstn_out/CLK (GTP_DFF_C)

                                   tco                   0.203       1.303 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rstn_out/Q (GTP_DFF_C)
                                   net (fanout=2)        0.679       1.982         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rst_n_sync
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N0/I1 (GTP_LUT2)
                                   td                    0.224       2.206 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N0/Z (GTP_LUT2)
                                   net (fanout=38)       0.557       2.763         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/N0
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_PLLPOWERDOWN/P (GTP_DFF_P)

 Data arrival time                                                   2.763         Logic Levels: 1  
                                                                                   Logic: 0.427ns(25.676%), Route: 1.236ns(74.324%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            10.000      10.000 r                        
                                                         0.000      10.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100      11.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_PLLPOWERDOWN/CLK (GTP_DFF_P)
 clock pessimism                                         0.000      11.100                          
 clock uncertainty                                      -0.050      11.050                          

 Recovery time                                          -0.226      10.824                          

 Data required time                                                 10.824                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.824                          
 Data arrival time                                                   2.763                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         8.061                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_rstn_sync/sig_synced/CLK (GTP_DFF_C)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/tx_rst_done_ref/C (GTP_DFF_CE)
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_rstn_sync/sig_synced/CLK (GTP_DFF_C)

                                   tco                   0.203       1.303 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_rstn_sync/sig_synced/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       1.303         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/ref_rst_n
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N158/I (GTP_INV)
                                   td                    0.000       1.303 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N158/Z (GTP_INV)
                                   net (fanout=1)        0.385       1.688         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/N158
                                                                           f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/tx_rst_done_ref/C (GTP_DFF_CE)

 Data arrival time                                                   1.688         Logic Levels: 1  
                                                                                   Logic: 0.203ns(34.524%), Route: 0.385ns(65.476%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/tx_rst_done_ref/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000       1.100                          
 clock uncertainty                                       0.000       1.100                          

 Removal time                                           -0.064       1.036                          

 Data required time                                                  1.036                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  1.036                          
 Data arrival time                                                   1.688                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.652                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rs2/CLK (GTP_DFF_C)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/cnt_rst[0]/P (GTP_DFF_PE)
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rs2/CLK (GTP_DFF_C)

                                   tco                   0.203       1.303 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rs2/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       1.303         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rstn_inner
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/N3/I (GTP_INV)
                                   td                    0.000       1.303 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/N3/Z (GTP_INV)
                                   net (fanout=22)       0.519       1.822         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/N3
                                                                           f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/cnt_rst[0]/P (GTP_DFF_PE)

 Data arrival time                                                   1.822         Logic Levels: 1  
                                                                                   Logic: 0.203ns(28.116%), Route: 0.519ns(71.884%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/cnt_rst[0]/CLK (GTP_DFF_PE)
 clock pessimism                                         0.000       1.100                          
 clock uncertainty                                       0.000       1.100                          

 Removal time                                           -0.064       1.036                          

 Data required time                                                  1.036                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  1.036                          
 Data arrival time                                                   1.822                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.786                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rs2/CLK (GTP_DFF_C)
Endpoint    : u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/cnt_rst[1]/P (GTP_DFF_PE)
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.100
  Launch Clock Delay      :  1.100
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rs2/CLK (GTP_DFF_C)

                                   tco                   0.203       1.303 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rs2/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       1.303         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/rstn_inner
                                                                                   u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/N3/I (GTP_INV)
                                   td                    0.000       1.303 f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/N3/Z (GTP_INV)
                                   net (fanout=22)       0.519       1.822         u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/N3
                                                                           f       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/cnt_rst[1]/P (GTP_DFF_PE)

 Data arrival time                                                   1.822         Logic Levels: 1  
                                                                                   Logic: 0.203ns(28.116%), Route: 0.519ns(71.884%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
                                                         0.000       0.000 r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/u_clkbufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=594)      1.100       1.100         ref_clk          
                                                                           r       u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/ext_rstn_debounce/cnt_rst[1]/CLK (GTP_DFF_PE)
 clock pessimism                                         0.000       1.100                          
 clock uncertainty                                       0.000       1.100                          

 Removal time                                           -0.064       1.036                          

 Data required time                                                  1.036                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  1.036                          
 Data arrival time                                                   1.822                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.786                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_8_16bit/enble/CLK (GTP_DFF)
Endpoint    : cmos1_8_16bit/pclk_div2/C (GTP_DFF_C)
Path Group  : cmos1_pclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    2.615  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.995
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420       3.380         nt_cmos1_pclk    
                                                                           r       cmos1_8_16bit/enble/CLK (GTP_DFF)

                                   tco                   0.185       3.565 f       cmos1_8_16bit/enble/Q (GTP_DFF)
                                   net (fanout=3)        0.000       3.565         cmos1_8_16bit/enble
                                                                                   cmos1_8_16bit/N7/I (GTP_INV)
                                   td                    0.000       3.565 r       cmos1_8_16bit/N7/Z (GTP_INV)
                                   net (fanout=1)        0.467       4.032         cmos1_8_16bit/N7 
                                                                           r       cmos1_8_16bit/pclk_div2/C (GTP_DFF_C)

 Data arrival time                                                   4.032         Logic Levels: 1  
                                                                                   Logic: 0.185ns(28.374%), Route: 0.467ns(71.626%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                         23.810      23.810 r                        
 cmos1_pclk                                              0.000      23.810 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000      23.810         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960      24.770 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506      26.276         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229      26.505 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300      29.805         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      29.805                          
 clock uncertainty                                      -0.250      29.555                          

 Recovery time                                          -0.226      29.329                          

 Data required time                                                 29.329                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 29.329                          
 Data arrival time                                                   4.032                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        25.297                          
====================================================================================================

====================================================================================================

Startpoint  : cmos1_8_16bit/enble/CLK (GTP_DFF)
Endpoint    : cmos1_8_16bit/pclk_div2/C (GTP_DFF_C)
Path Group  : cmos1_pclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    2.615  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.995
  Launch Clock Delay      :  3.380
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       2.420       3.380         nt_cmos1_pclk    
                                                                           r       cmos1_8_16bit/enble/CLK (GTP_DFF)

                                   tco                   0.203       3.583 r       cmos1_8_16bit/enble/Q (GTP_DFF)
                                   net (fanout=3)        0.000       3.583         cmos1_8_16bit/enble
                                                                                   cmos1_8_16bit/N7/I (GTP_INV)
                                   td                    0.000       3.583 f       cmos1_8_16bit/N7/Z (GTP_INV)
                                   net (fanout=1)        0.467       4.050         cmos1_8_16bit/N7 
                                                                           f       cmos1_8_16bit/pclk_div2/C (GTP_DFF_C)

 Data arrival time                                                   4.050         Logic Levels: 1  
                                                                                   Logic: 0.203ns(30.299%), Route: 0.467ns(69.701%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk (rising edge)                          0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
 clock pessimism                                         0.000       5.995                          
 clock uncertainty                                       0.200       6.195                          

 Removal time                                           -0.064       6.131                          

 Data required time                                                  6.131                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  6.131                          
 Data arrival time                                                   4.050                          
----------------------------------------------------------------------------------------------------
 Slack (VIOLATED)                                                   -2.081                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/C (GTP_DFF_C)
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK (GTP_DFF_C)

                                   tco                   0.185       5.263 f       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       5.263         u_ddr3/u_ddrphy_top/logic_rstn
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N0/I (GTP_INV)
                                   td                    0.000       5.263 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N0/Z (GTP_INV)
                                   net (fanout=95)       0.623       5.886         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N0
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/C (GTP_DFF_C)

 Data arrival time                                                   5.886         Logic Levels: 1  
                                                                                   Logic: 0.185ns(22.896%), Route: 0.623ns(77.104%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      42.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064      42.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      43.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      43.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100      45.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      45.078                          
 clock uncertainty                                      -0.150      44.928                          

 Recovery time                                          -0.226      44.702                          

 Data required time                                                 44.702                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.702                          
 Data arrival time                                                   5.886                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.816                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[1]/C (GTP_DFF_C)
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK (GTP_DFF_C)

                                   tco                   0.185       5.263 f       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       5.263         u_ddr3/u_ddrphy_top/logic_rstn
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N0/I (GTP_INV)
                                   td                    0.000       5.263 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N0/Z (GTP_INV)
                                   net (fanout=95)       0.623       5.886         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N0
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[1]/C (GTP_DFF_C)

 Data arrival time                                                   5.886         Logic Levels: 1  
                                                                                   Logic: 0.185ns(22.896%), Route: 0.623ns(77.104%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      42.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064      42.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      43.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      43.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100      45.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[1]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      45.078                          
 clock uncertainty                                      -0.150      44.928                          

 Recovery time                                          -0.226      44.702                          

 Data required time                                                 44.702                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.702                          
 Data arrival time                                                   5.886                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.816                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[0]/C (GTP_DFF_CE)
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK (GTP_DFF_C)

                                   tco                   0.185       5.263 f       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       5.263         u_ddr3/u_ddrphy_top/logic_rstn
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N0/I (GTP_INV)
                                   td                    0.000       5.263 r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N0/Z (GTP_INV)
                                   net (fanout=95)       0.623       5.886         u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/N0
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[0]/C (GTP_DFF_CE)

 Data arrival time                                                   5.886         Logic Levels: 1  
                                                                                   Logic: 0.185ns(22.896%), Route: 0.623ns(77.104%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 sys_clk                                                 0.000      40.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000      40.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960      40.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466      42.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064      42.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      43.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      43.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100      45.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[0]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000      45.078                          
 clock uncertainty                                      -0.150      44.928                          

 Recovery time                                          -0.226      44.702                          

 Data required time                                                 44.702                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.702                          
 Data arrival time                                                   5.886                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.816                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/C (GTP_DFF_CE)
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)

                                   tco                   0.203       5.281 r       u_ddr3/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       5.281         u_ddr3/u_ddrphy_top/rst_seq_rstn
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/N32/I (GTP_INV)
                                   td                    0.000       5.281 f       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/N32/Z (GTP_INV)
                                   net (fanout=66)       0.597       5.878         u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/N32
                                                                           f       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/C (GTP_DFF_CE)

 Data arrival time                                                   5.878         Logic Levels: 1  
                                                                                   Logic: 0.203ns(25.375%), Route: 0.597ns(74.625%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000       5.078                          
 clock uncertainty                                       0.000       5.078                          

 Removal time                                           -0.064       5.014                          

 Data required time                                                  5.014                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.014                          
 Data arrival time                                                   5.878                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.864                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/C (GTP_DFF_CE)
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)

                                   tco                   0.203       5.281 r       u_ddr3/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       5.281         u_ddr3/u_ddrphy_top/rst_seq_rstn
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/N32/I (GTP_INV)
                                   td                    0.000       5.281 f       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/N32/Z (GTP_INV)
                                   net (fanout=66)       0.597       5.878         u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/N32
                                                                           f       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/C (GTP_DFF_CE)

 Data arrival time                                                   5.878         Logic Levels: 1  
                                                                                   Logic: 0.203ns(25.375%), Route: 0.597ns(74.625%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000       5.078                          
 clock uncertainty                                       0.000       5.078                          

 Removal time                                           -0.064       5.014                          

 Data required time                                                  5.014                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.014                          
 Data arrival time                                                   5.878                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.864                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/C (GTP_DFF_CE)
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.078
  Launch Clock Delay      :  5.078
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)

                                   tco                   0.203       5.281 r       u_ddr3/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000       5.281         u_ddr3/u_ddrphy_top/rst_seq_rstn
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/N32/I (GTP_INV)
                                   td                    0.000       5.281 f       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/N32/Z (GTP_INV)
                                   net (fanout=66)       0.597       5.878         u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/N32
                                                                           f       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/C (GTP_DFF_CE)

 Data arrival time                                                   5.878         Logic Levels: 1  
                                                                                   Logic: 0.203ns(25.375%), Route: 0.597ns(74.625%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.466       2.426         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKIN1 (GTP_GPLL)
                                   td                    0.064       2.490 r       u_ddr3/u_ddrphy_top/rst_clk_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       3.810         u_ddr3/u_ddrphy_top/rst_gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       3.978 r       u_ddr3/u_ddrphy_top/u_rst_clk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=164)      1.100       5.078         u_ddr3/u_ddrphy_top/rst_clk
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000       5.078                          
 clock uncertainty                                       0.000       5.078                          

 Removal time                                           -0.064       5.014                          

 Data required time                                                  5.014                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.014                          
 Data arrival time                                                   5.878                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.864                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/CLK (GTP_DFF_C)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/RSTB (GTP_DRM36K_E1)
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.896
  Launch Clock Delay      :  10.224
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/CLK (GTP_DFF_C)

                                   tco                   0.203      10.427 r       u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/Q (GTP_DFF_C)
                                   net (fanout=21)       0.613      11.040         ddr_init_done    
                                                                                   N70/I0 (GTP_LUT2)
                                   td                    0.224      11.264 r       N70/Z (GTP_LUT2) 
                                   net (fanout=219)      1.423      12.687         N70              
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/RSTB (GTP_DRM36K_E1)

 Data arrival time                                                  12.687         Logic Levels: 1  
                                                                                   Logic: 0.427ns(17.337%), Route: 2.036ns(82.663%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 sys_clk                                                 0.000       7.619 r       sys_clk (port)   
                                   net (fanout=1)        0.000       7.619         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       8.579 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       9.899         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148      10.047 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200      12.247         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177      12.424 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385      12.809         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037      12.846 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653      13.499         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123      13.622 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420      16.042         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115      14.927 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      16.247         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      16.415 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      17.515         ddr_core_clk     
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/CLKB (GTP_DRM36K_E1)
 clock pessimism                                         0.000      17.515                          
 clock uncertainty                                      -0.150      17.365                          

 Recovery time                                          -0.395      16.970                          

 Data required time                                                 16.970                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 16.970                          
 Data arrival time                                                  12.687                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.283                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/CLK (GTP_DFF_C)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM36K_E1/RSTB (GTP_DRM36K_E1)
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.896
  Launch Clock Delay      :  10.224
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/CLK (GTP_DFF_C)

                                   tco                   0.203      10.427 r       u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/Q (GTP_DFF_C)
                                   net (fanout=21)       0.613      11.040         ddr_init_done    
                                                                                   N70/I0 (GTP_LUT2)
                                   td                    0.224      11.264 r       N70/Z (GTP_LUT2) 
                                   net (fanout=219)      1.423      12.687         N70              
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM36K_E1/RSTB (GTP_DRM36K_E1)

 Data arrival time                                                  12.687         Logic Levels: 1  
                                                                                   Logic: 0.427ns(17.337%), Route: 2.036ns(82.663%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 sys_clk                                                 0.000       7.619 r       sys_clk (port)   
                                   net (fanout=1)        0.000       7.619         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       8.579 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       9.899         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148      10.047 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200      12.247         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177      12.424 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385      12.809         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037      12.846 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653      13.499         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123      13.622 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420      16.042         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115      14.927 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      16.247         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      16.415 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      17.515         ddr_core_clk     
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM36K_E1/CLKB (GTP_DRM36K_E1)
 clock pessimism                                         0.000      17.515                          
 clock uncertainty                                      -0.150      17.365                          

 Recovery time                                          -0.395      16.970                          

 Data required time                                                 16.970                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 16.970                          
 Data arrival time                                                  12.687                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.283                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/CLK (GTP_DFF_C)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM36K_E1/RSTB (GTP_DRM36K_E1)
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.896
  Launch Clock Delay      :  10.224
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/CLK (GTP_DFF_C)

                                   tco                   0.203      10.427 r       u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/Q (GTP_DFF_C)
                                   net (fanout=21)       0.613      11.040         ddr_init_done    
                                                                                   N70/I0 (GTP_LUT2)
                                   td                    0.224      11.264 r       N70/Z (GTP_LUT2) 
                                   net (fanout=219)      1.423      12.687         N70              
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM36K_E1/RSTB (GTP_DRM36K_E1)

 Data arrival time                                                  12.687         Logic Levels: 1  
                                                                                   Logic: 0.427ns(17.337%), Route: 2.036ns(82.663%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 sys_clk                                                 0.000       7.619 r       sys_clk (port)   
                                   net (fanout=1)        0.000       7.619         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       8.579 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       9.899         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148      10.047 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200      12.247         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177      12.424 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385      12.809         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037      12.846 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653      13.499         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123      13.622 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420      16.042         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115      14.927 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320      16.247         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168      16.415 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      17.515         ddr_core_clk     
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM36K_E1/CLKB (GTP_DRM36K_E1)
 clock pessimism                                         0.000      17.515                          
 clock uncertainty                                      -0.150      17.365                          

 Recovery time                                          -0.395      16.970                          

 Data required time                                                 16.970                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 16.970                          
 Data arrival time                                                  12.687                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.283                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_lock/C (GTP_DFF_C)
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  10.224
  Launch Clock Delay      :  9.896
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115       7.308 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.628         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       8.796 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100       9.896         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)

                                   tco                   0.203      10.099 r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000      10.099         u_ddr3/u_ddrphy_top/ddrphy_cpd_rstn_synced
                                                                                   u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/N0/I (GTP_INV)
                                   td                    0.000      10.099 f       u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/N0/Z (GTP_INV)
                                   net (fanout=8)        0.437      10.536         u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/N0
                                                                           f       u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_lock/C (GTP_DFF_C)

 Data arrival time                                                  10.536         Logic Levels: 1  
                                                                                   Logic: 0.203ns(31.719%), Route: 0.437ns(68.281%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_lock/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      10.224                          
 clock uncertainty                                       0.000      10.224                          

 Removal time                                           -0.064      10.160                          

 Data required time                                                 10.160                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.160                          
 Data arrival time                                                  10.536                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.376                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/C (GTP_DFF_C)
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  10.224
  Launch Clock Delay      :  9.896
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115       7.308 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.628         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       8.796 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100       9.896         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)

                                   tco                   0.203      10.099 r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000      10.099         u_ddr3/u_ddrphy_top/ddrphy_cpd_rstn_synced
                                                                                   u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/N0/I (GTP_INV)
                                   td                    0.000      10.099 f       u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/N0/Z (GTP_INV)
                                   net (fanout=8)        0.437      10.536         u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/N0
                                                                           f       u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/C (GTP_DFF_C)

 Data arrival time                                                  10.536         Logic Levels: 1  
                                                                                   Logic: 0.203ns(31.719%), Route: 0.437ns(68.281%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      10.224                          
 clock uncertainty                                       0.000      10.224                          

 Removal time                                           -0.064      10.160                          

 Data required time                                                 10.160                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.160                          
 Data arrival time                                                  10.536                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.376                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)
Endpoint    : u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[1]/C (GTP_DFF_C)
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.328  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  10.224
  Launch Clock Delay      :  9.896
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -1.115       7.308 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.628         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       8.796 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100       9.896         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C)

                                   tco                   0.203      10.099 r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C)
                                   net (fanout=1)        0.000      10.099         u_ddr3/u_ddrphy_top/ddrphy_cpd_rstn_synced
                                                                                   u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/N0/I (GTP_INV)
                                   td                    0.000      10.099 f       u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/N0/Z (GTP_INV)
                                   net (fanout=8)        0.437      10.536         u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/N0
                                                                           f       u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[1]/C (GTP_DFF_C)

 Data arrival time                                                  10.536         Logic Levels: 1  
                                                                                   Logic: 0.203ns(31.719%), Route: 0.437ns(68.281%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[1]/CLK (GTP_DFF_C)
 clock pessimism                                         0.000      10.224                          
 clock uncertainty                                       0.000      10.224                          

 Removal time                                           -0.064      10.160                          

 Data required time                                                 10.160                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.160                          
 Data arrival time                                                  10.536                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.376                          
====================================================================================================

====================================================================================================

Startpoint  : wr_rst_sync[1]/CLK (GTP_DFF_P)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/RSTA (GTP_DRM36K_E1)
Path Group  : cmos1_pclk_16bit
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       wr_rst_sync[1]/CLK (GTP_DFF_P)

                                   tco                   0.203       9.701 r       wr_rst_sync[1]/Q (GTP_DFF_P)
                                   net (fanout=49)       1.307      11.008         wr_rst_sync[1]   
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/RSTA (GTP_DRM36K_E1)

 Data arrival time                                                  11.008         Logic Levels: 0  
                                                                                   Logic: 0.203ns(13.444%), Route: 1.307ns(86.556%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                        47.620      47.620 r                        
 cmos1_pclk                                              0.000      47.620 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000      47.620         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960      48.580 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506      50.086         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229      50.315 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300      53.615         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203      53.818 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300      57.118         cmos1_pclk_16bit 
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/CLKA (GTP_DRM36K_E1)
 clock pessimism                                         0.000      57.118                          
 clock uncertainty                                      -0.250      56.868                          

 Recovery time                                          -0.395      56.473                          

 Data required time                                                 56.473                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 56.473                          
 Data arrival time                                                  11.008                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        45.465                          
====================================================================================================

====================================================================================================

Startpoint  : wr_rst_sync[1]/CLK (GTP_DFF_P)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM36K_E1/RSTA (GTP_DRM36K_E1)
Path Group  : cmos1_pclk_16bit
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       wr_rst_sync[1]/CLK (GTP_DFF_P)

                                   tco                   0.203       9.701 r       wr_rst_sync[1]/Q (GTP_DFF_P)
                                   net (fanout=49)       1.307      11.008         wr_rst_sync[1]   
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM36K_E1/RSTA (GTP_DRM36K_E1)

 Data arrival time                                                  11.008         Logic Levels: 0  
                                                                                   Logic: 0.203ns(13.444%), Route: 1.307ns(86.556%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                        47.620      47.620 r                        
 cmos1_pclk                                              0.000      47.620 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000      47.620         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960      48.580 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506      50.086         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229      50.315 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300      53.615         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203      53.818 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300      57.118         cmos1_pclk_16bit 
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM36K_E1/CLKA (GTP_DRM36K_E1)
 clock pessimism                                         0.000      57.118                          
 clock uncertainty                                      -0.250      56.868                          

 Recovery time                                          -0.395      56.473                          

 Data required time                                                 56.473                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 56.473                          
 Data arrival time                                                  11.008                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        45.465                          
====================================================================================================

====================================================================================================

Startpoint  : wr_rst_sync[1]/CLK (GTP_DFF_P)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM36K_E1/RSTA (GTP_DRM36K_E1)
Path Group  : cmos1_pclk_16bit
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       wr_rst_sync[1]/CLK (GTP_DFF_P)

                                   tco                   0.203       9.701 r       wr_rst_sync[1]/Q (GTP_DFF_P)
                                   net (fanout=49)       1.307      11.008         wr_rst_sync[1]   
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM36K_E1/RSTA (GTP_DRM36K_E1)

 Data arrival time                                                  11.008         Logic Levels: 0  
                                                                                   Logic: 0.203ns(13.444%), Route: 1.307ns(86.556%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                        47.620      47.620 r                        
 cmos1_pclk                                              0.000      47.620 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000      47.620         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960      48.580 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506      50.086         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229      50.315 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300      53.615         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203      53.818 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300      57.118         cmos1_pclk_16bit 
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM36K_E1/CLKA (GTP_DRM36K_E1)
 clock pessimism                                         0.000      57.118                          
 clock uncertainty                                      -0.250      56.868                          

 Recovery time                                          -0.395      56.473                          

 Data required time                                                 56.473                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 56.473                          
 Data arrival time                                                  11.008                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        45.465                          
====================================================================================================

====================================================================================================

Startpoint  : wr_rst_sync[1]/CLK (GTP_DFF_P)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.asyn_wfull/C (GTP_DFF_C)
Path Group  : cmos1_pclk_16bit
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       wr_rst_sync[1]/CLK (GTP_DFF_P)

                                   tco                   0.185       9.683 f       wr_rst_sync[1]/Q (GTP_DFF_P)
                                   net (fanout=49)       0.592      10.275         wr_rst_sync[1]   
                                                                           f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.asyn_wfull/C (GTP_DFF_C)

 Data arrival time                                                  10.275         Logic Levels: 0  
                                                                                   Logic: 0.185ns(23.810%), Route: 0.592ns(76.190%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C)
 clock pessimism                                         0.000       9.498                          
 clock uncertainty                                       0.200       9.698                          

 Removal time                                           -0.064       9.634                          

 Data required time                                                  9.634                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  9.634                          
 Data arrival time                                                  10.275                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.641                          
====================================================================================================

====================================================================================================

Startpoint  : wr_rst_sync[1]/CLK (GTP_DFF_P)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wbin[0]/C (GTP_DFF_CE)
Path Group  : cmos1_pclk_16bit
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       wr_rst_sync[1]/CLK (GTP_DFF_P)

                                   tco                   0.185       9.683 f       wr_rst_sync[1]/Q (GTP_DFF_P)
                                   net (fanout=49)       0.592      10.275         wr_rst_sync[1]   
                                                                           f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wbin[0]/C (GTP_DFF_CE)

 Data arrival time                                                  10.275         Logic Levels: 0  
                                                                                   Logic: 0.185ns(23.810%), Route: 0.592ns(76.190%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000       9.498                          
 clock uncertainty                                       0.200       9.698                          

 Removal time                                           -0.064       9.634                          

 Data required time                                                  9.634                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  9.634                          
 Data arrival time                                                  10.275                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.641                          
====================================================================================================

====================================================================================================

Startpoint  : wr_rst_sync[1]/CLK (GTP_DFF_P)
Endpoint    : u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wbin[1]/C (GTP_DFF_CE)
Path Group  : cmos1_pclk_16bit
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  9.498
  Launch Clock Delay      :  9.498
  Clock Pessimism Removal :  0.000

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       wr_rst_sync[1]/CLK (GTP_DFF_P)

                                   tco                   0.185       9.683 f       wr_rst_sync[1]/Q (GTP_DFF_P)
                                   net (fanout=49)       0.592      10.275         wr_rst_sync[1]   
                                                                           f       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wbin[1]/C (GTP_DFF_CE)

 Data arrival time                                                  10.275         Logic Levels: 0  
                                                                                   Logic: 0.185ns(23.810%), Route: 0.592ns(76.190%)
----------------------------------------------------------------------------------------------------

 Clock cmos1_pclk_16bit (rising edge)
                                                         0.000       0.000 r                        
 cmos1_pclk                                              0.000       0.000 r       cmos1_pclk (port)
                                   net (fanout=1)        0.000       0.000         cmos1_pclk       
                                                                                   cmos1_pclk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       cmos1_pclk_ibuf/O (GTP_INBUF)
                                   net (fanout=42)       1.506       2.466         nt_cmos1_pclk    
                                                                                   cmos1_8_16bit/N6/I0 (GTP_LUT2)
                                   td                    0.229       2.695 r       cmos1_8_16bit/N6/Z (GTP_LUT2)
                                   net (fanout=1)        3.300       5.995         cmos1_8_16bit/pclk_IOCLKBUF
                                                                           r       cmos1_8_16bit/pclk_div2/CLK (GTP_DFF_C)
                                   tco                   0.203       6.198 r       cmos1_8_16bit/pclk_div2/Q (GTP_DFF_C)
                                   net (fanout=223)      3.300       9.498         cmos1_pclk_16bit 
                                                                           r       u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (GTP_DFF_CE)
 clock pessimism                                         0.000       9.498                          
 clock uncertainty                                       0.200       9.698                          

 Removal time                                           -0.064       9.634                          

 Data required time                                                  9.634                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  9.634                          
 Data arrival time                                                  10.275                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.641                          
====================================================================================================

====================================================================================================

Startpoint  : u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C)
Endpoint    : ddr_mem_rst_n (port)
Path Group  : **default**
Path Type   : max (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       1.320       2.280         nt_sys_clk       
                                                                                   u_ddr3/u_ddrphy_top/u_clkbufm/CLKIN (GTP_CLKBUFM)
                                   td                    0.148       2.428 r       u_ddr3/u_ddrphy_top/u_clkbufm/CLKOUT (GTP_CLKBUFM)
                                   net (fanout=2)        2.200       4.628         u_ddr3/u_ddrphy_top/pll_refclk
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKIN (GTP_CLKBUFR)
                                   td                    0.177       4.805 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/CLKOUT (GTP_CLKBUFR)
                                   net (fanout=1)        0.385       5.190         u_ddr3/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKIN1 (GTP_PPLL)
                                   td                    0.037       5.227 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/CLKOUTPHY (GTP_PPLL)
                                   net (fanout=36)       0.653       5.880         u_ddr3/u_ddrphy_top/phy_ioclk_fb
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKIN (GTP_IOCLKDIV_E3)
                                   td                    0.123       6.003 r       u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT (GTP_IOCLKDIV_E3)
                                   net (fanout=35)       2.420       8.423         u_ddr3/u_ddrphy_top/phy_sysclk_fb
                                                                           r       u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY (GTP_CLKPD)
                                                        -0.787       7.636 r       u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll/CLKOUT0 (GTP_GPLL)
                                   net (fanout=1)        1.320       8.956         u_ddr3/u_ddrphy_top/gpll_clkout0
                                                                                   u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKIN (GTP_CLKBUFG)
                                   td                    0.168       9.124 r       u_ddr3/u_ddrphy_top/u_sysclk_bufg/CLKOUT (GTP_CLKBUFG)
                                   net (fanout=3472)     1.100      10.224         ddr_core_clk     
                                                                           r       u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C)

                                   tco                   0.203      10.427 r       u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/Q (GTP_DFF_C)
                                   net (fanout=283)      1.196      11.623         u_ddr3/u_ddrphy_top/calib_done
                                                                                   u_ddr3/u_ddrphy_top/ddrphy_dfi/N93[21]/I0 (GTP_LUT6D)
                                   td                    0.212      11.835 r       u_ddr3/u_ddrphy_top/ddrphy_dfi/N93[21]/Z5 (GTP_LUT6D)
                                   net (fanout=1)        1.320      13.155         nt_ddr_mem_rst_n 
                                                                                   ddr_mem_rst_n_obuf/I (GTP_OUTBUF)
                                   td                    3.553      16.708 r       ddr_mem_rst_n_obuf/O (GTP_OUTBUF)
                                   net (fanout=1)        0.000      16.708         ddr_mem_rst_n    
 ddr_mem_rst_n                                                             r       ddr_mem_rst_n (port)

 Data arrival time                                                  16.708         Logic Levels: 2  
                                                                                   Logic: 3.968ns(61.197%), Route: 2.516ns(38.803%)
====================================================================================================

====================================================================================================

Startpoint  : coms1_reg_config/clock_20k/CLK (GTP_DFF_R)
Endpoint    : cmos1_scl (port)
Path Group  : **default**
Path Type   : max (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420       3.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k/CLK (GTP_DFF_R)

                                   tco                   0.203       3.583 r       coms1_reg_config/clock_20k/Q (GTP_DFF_R)
                                   net (fanout=53)       0.605       4.188         coms1_reg_config/clock_20k
                                                                                   coms1_reg_config/u1/N23[0]/I0 (GTP_LUT6)
                                   td                    0.074       4.262 r       coms1_reg_config/u1/N23[0]/Z (GTP_LUT6)
                                   net (fanout=1)        1.320       5.582         nt_cmos1_scl     
                                                                                   cmos1_scl_iobuf/I (GTP_OUTBUFT)
                                   td                    3.553       9.135 r       cmos1_scl_iobuf/O (GTP_OUTBUFT)
                                   net (fanout=1)        0.000       9.135         cmos1_scl        
 cmos1_scl                                                                 r       cmos1_scl (port) 

 Data arrival time                                                   9.135         Logic Levels: 2  
                                                                                   Logic: 3.830ns(66.551%), Route: 1.925ns(33.449%)
====================================================================================================

====================================================================================================

Startpoint  : coms1_reg_config/clock_20k/CLK (GTP_DFF_R)
Endpoint    : cmos2_scl (port)
Path Group  : **default**
Path Type   : max (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock sys_clk (rising edge)                             0.000       0.000 r                        
 sys_clk                                                 0.000       0.000 r       sys_clk (port)   
                                   net (fanout=1)        0.000       0.000         sys_clk          
                                                                                   sys_clk_ibuf/I (GTP_INBUF)
                                   td                    0.960       0.960 r       sys_clk_ibuf/O (GTP_INBUF)
                                   net (fanout=16)       2.420       3.380         nt_sys_clk       
                                                                           r       coms1_reg_config/clock_20k/CLK (GTP_DFF_R)

                                   tco                   0.203       3.583 r       coms1_reg_config/clock_20k/Q (GTP_DFF_R)
                                   net (fanout=53)       0.605       4.188         coms1_reg_config/clock_20k
                                                                                   coms2_reg_config/u1/N23[0]/I0 (GTP_LUT6)
                                   td                    0.074       4.262 r       coms2_reg_config/u1/N23[0]/Z (GTP_LUT6)
                                   net (fanout=1)        1.320       5.582         nt_cmos2_scl     
                                                                                   cmos2_scl_iobuf/I (GTP_OUTBUFT)
                                   td                    3.553       9.135 r       cmos2_scl_iobuf/O (GTP_OUTBUFT)
                                   net (fanout=1)        0.000       9.135         cmos2_scl        
 cmos2_scl                                                                 r       cmos2_scl (port) 

 Data arrival time                                                   9.135         Logic Levels: 2  
                                                                                   Logic: 3.830ns(66.551%), Route: 1.925ns(33.449%)
====================================================================================================

====================================================================================================

Startpoint  : cmos1_data[0] (port)
Endpoint    : cmos1_d_d0[0]/D (GTP_DFF)
Path Group  : **default**
Path Type   : min (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 cmos1_data[0]                                           0.000       0.000 f       cmos1_data[0] (port)
                                   net (fanout=1)        0.000       0.000         cmos1_data[0]    
                                                                                   cmos1_data_ibuf[0]/I (GTP_INBUF)
                                   td                    0.861       0.861 f       cmos1_data_ibuf[0]/O (GTP_INBUF)
                                   net (fanout=1)        0.000       0.861         nt_cmos1_data[0] 
                                                                           f       cmos1_d_d0[0]/D (GTP_DFF)

 Data arrival time                                                   0.861         Logic Levels: 1  
                                                                                   Logic: 0.861ns(100.000%), Route: 0.000ns(0.000%)
====================================================================================================

====================================================================================================

Startpoint  : cmos1_data[1] (port)
Endpoint    : cmos1_d_d0[1]/D (GTP_DFF)
Path Group  : **default**
Path Type   : min (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 cmos1_data[1]                                           0.000       0.000 f       cmos1_data[1] (port)
                                   net (fanout=1)        0.000       0.000         cmos1_data[1]    
                                                                                   cmos1_data_ibuf[1]/I (GTP_INBUF)
                                   td                    0.861       0.861 f       cmos1_data_ibuf[1]/O (GTP_INBUF)
                                   net (fanout=1)        0.000       0.861         nt_cmos1_data[1] 
                                                                           f       cmos1_d_d0[1]/D (GTP_DFF)

 Data arrival time                                                   0.861         Logic Levels: 1  
                                                                                   Logic: 0.861ns(100.000%), Route: 0.000ns(0.000%)
====================================================================================================

====================================================================================================

Startpoint  : cmos1_data[2] (port)
Endpoint    : cmos1_d_d0[2]/D (GTP_DFF)
Path Group  : **default**
Path Type   : min (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 cmos1_data[2]                                           0.000       0.000 f       cmos1_data[2] (port)
                                   net (fanout=1)        0.000       0.000         cmos1_data[2]    
                                                                                   cmos1_data_ibuf[2]/I (GTP_INBUF)
                                   td                    0.861       0.861 f       cmos1_data_ibuf[2]/O (GTP_INBUF)
                                   net (fanout=1)        0.000       0.861         nt_cmos1_data[2] 
                                                                           f       cmos1_d_d0[2]/D (GTP_DFF)

 Data arrival time                                                   0.861         Logic Levels: 1  
                                                                                   Logic: 0.861ns(100.000%), Route: 0.000ns(0.000%)
====================================================================================================

{pclk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 1.040       2.000           0.960           High Pulse Width                          u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K_E1/CLKA
 1.040       2.000           0.960           Low Pulse Width                           u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K_E1/CLKA
 1.040       2.000           0.960           High Pulse Width                          u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/pcie2_iip_exrcvdata_rams/U_ipm2l_sdpram_rcv_data_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K_E1/CLKB
====================================================================================================

{pclk_div2} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 3.040       4.000           0.960           High Pulse Width                          u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/ips2l_pcie_dma_bar0/U_ipm2l_sdpram_ips2l_pcie_dma_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K_E1/CLKB
 3.040       4.000           0.960           Low Pulse Width                           u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/ips2l_pcie_dma_bar0/U_ipm2l_sdpram_ips2l_pcie_dma_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K_E1/CLKB
 3.040       4.000           0.960           High Pulse Width                          u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/ips2l_pcie_dma_bar0/U_ipm2l_sdpram_ips2l_pcie_dma_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K_E1/CLKB
====================================================================================================

{ref_clk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 4.800       5.000           0.200           High Pulse Width                          ref_led/CLK  
 4.800       5.000           0.200           Low Pulse Width                           ref_led/CLK  
 4.800       5.000           0.200           High Pulse Width                          ref_led_cnt[0]/CLK
====================================================================================================

{sys_clk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 19.800      20.000          0.200           High Pulse Width                          coms1_reg_config/clock_20k/CLK
 19.800      20.000          0.200           Low Pulse Width                           coms1_reg_config/clock_20k/CLK
 19.800      20.000          0.200           High Pulse Width                          coms1_reg_config/clock_20k_cnt[0]/CLK
====================================================================================================

{cmos1_pclk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 11.705      11.905          0.200           High Pulse Width                          cmos1_8_16bit/cnt[0]/CLK
 11.705      11.905          0.200           Low Pulse Width                           cmos1_8_16bit/cnt[0]/CLK
 11.705      11.905          0.200           High Pulse Width                          cmos1_8_16bit/cnt[1]/CLK
====================================================================================================

{rst_clk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 19.800      20.000          0.200           High Pulse Width                          u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/CLK
 19.800      20.000          0.200           Low Pulse Width                           u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/CLK
 19.800      20.000          0.200           High Pulse Width                          u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[1]/CLK
====================================================================================================

{ddrphy_sysclk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 2.849       3.809           0.960           High Pulse Width                          u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/CLKB
 2.849       3.809           0.960           High Pulse Width                          u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM36K_E1/CLKB
 2.849       3.809           0.960           High Pulse Width                          u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM36K_E1/CLKB
====================================================================================================

{phy_dq_clk_0} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 0.011       0.476           0.465           High Pulse Width                          u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/CLKA
 0.011       0.476           0.465           Low Pulse Width                           u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/CLKA
 0.011       0.476           0.465           High Pulse Width                          u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/CLKA
====================================================================================================

{phy_dq_sysclk_0} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 1.659       3.809           2.150           Low Pulse Width                           u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY
 1.660       3.810           2.150           High Pulse Width                          u_ddr3/u_ddrphy_top/u_ddrphy_cpd/CLK_PHY
 2.209       3.809           1.600           Low Pulse Width                           u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_tserdes_ca0/OCLKDIV
====================================================================================================

{phy_dq_clk_1} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 0.011       0.476           0.465           Low Pulse Width                           u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/CLKA
 0.011       0.476           0.465           High Pulse Width                          u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/CLKA
 0.011       0.476           0.465           High Pulse Width                          u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_ddc_dq/CLKA
====================================================================================================

{phy_dq_sysclk_1} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 2.209       3.809           1.600           Low Pulse Width                           u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_iserdes_dq/ICLKDIV
 2.209       3.809           1.600           Low Pulse Width                           u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_oserdes_dq/OCLKDIV
 2.209       3.809           1.600           Low Pulse Width                           u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iserdes_dq/ICLKDIV
====================================================================================================

{cmos1_pclk_16bit} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 22.850      23.810          0.960           High Pulse Width                          u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/CLKA
 22.850      23.810          0.960           Low Pulse Width                           u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/CLKA
 22.850      23.810          0.960           Low Pulse Width                           u_SXT1_FIFO_to_DDR/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM36K_E1/CLKA
====================================================================================================

{sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 9.800       10.000          0.200           High Pulse Width                          power_on_delay_inst/camera_pwnd_reg/CLK
 9.800       10.000          0.200           Low Pulse Width                           power_on_delay_inst/camera_pwnd_reg/CLK
 9.800       10.000          0.200           High Pulse Width                          power_on_delay_inst/camera_rstn_reg/CLK
====================================================================================================

{sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 4.040       5.000           0.960           High Pulse Width                          u_SXT1_FIFO_to_PCIe/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/CLKB
 4.040       5.000           0.960           Low Pulse Width                           u_SXT1_FIFO_to_PCIe/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM36K_E1/CLKB
 4.040       5.000           0.960           High Pulse Width                          u_SXT1_FIFO_to_PCIe/U_ipm2l_fifo_SXT1_FIFO/U_ipm2l_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM36K_E1/CLKB
====================================================================================================

====================================================================================================

Inputs and Outputs :
+--------------------------------------------------------------------------------------------------------------------------+
| Type       | File Name                                                                                                  
+--------------------------------------------------------------------------------------------------------------------------+
| Input      | F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/compile/pcie_dma_test_comp.adf               
|            | F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc                        
| Output     | F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/synthesize/pcie_dma_test_syn.adf             
|            | F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/synthesize/pcie_dma_test_syn.vm              
|            | F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/synthesize/pcie_dma_test_controlsets.txt     
|            | F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/synthesize/snr.db                            
|            | F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/synthesize/pcie_dma_test.snr                 
+--------------------------------------------------------------------------------------------------------------------------+


Flow Command: synthesize -selected_syn_tool_opt 2 
Peak memory: 693 MB
Total CPU time to synthesize completion : 0h:1m:22s
Process Total CPU time to synthesize completion : 0h:1m:29s
Total real time to synthesize completion : 0h:1m:47s
