#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: E:\PDS_FPGA\PDS_2022.2-SP6.4\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.26100
#Hostname: 傻额宁儿
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Fri Nov  7 01:34:13 2025
#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: E:\PDS_FPGA\PDS_2022.2-SP6.4\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.26100
#Hostname: 傻额宁儿
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Fri Nov  7 01:33:39 2025
# pvf -action compile

pvf_reg_constant coms2_reg_config/clock_20k_cnt[15] 0

pvf_reg_constant coms2_reg_config/clock_20k_cnt[14] 0

pvf_reg_constant coms2_reg_config/clock_20k_cnt[13] 0

pvf_reg_constant coms2_reg_config/clock_20k_cnt[12] 0

pvf_reg_constant coms2_reg_config/clock_20k_cnt[11] 0

pvf_reg_constant coms1_reg_config/clock_20k_cnt[15] 0

pvf_reg_constant coms1_reg_config/clock_20k_cnt[14] 0

pvf_reg_constant coms1_reg_config/clock_20k_cnt[13] 0

pvf_reg_constant coms1_reg_config/clock_20k_cnt[12] 0

pvf_reg_constant coms1_reg_config/clock_20k_cnt[11] 0

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_gate_update_ctrl/update_start -deleted u_ddr3/u_ddrphy_top/ddrphy_gate_update_ctrl/ddrphy_update_req

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/cnt[6] 0

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cs_n

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_we_n

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/genblk2.init_cas_n -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/genblk2.init_ras_n

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[2] 0

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dqs_gate_comp_done -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dqs_gate_comp_en_r

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dqs_gate_comp_done -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dqs_gate_comp_en_r

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/o_user_define_data_flag 0

pvf_reg_constant u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/rst_clk_adj_dir 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_gate_update_ctrl/update_start 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/o_axis_slave0_tuser 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tuser 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/o_axis_slave2_tuser 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[0] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN 0

pvf_reg_merging  -survived bar0_wr_en -deleted ddr_fifo_rd_en_pcie

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_cs_n -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_ras_n

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cs_n[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_ras_n[1]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cs_n[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_ras_n[0]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tlast -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tvld

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_PMA_LANE_PD -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_PMA_TX_PD

# pvf -action synthesize

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[1]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[2]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[3]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[4]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[5]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[6]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[7]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[8]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[9]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[10]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[11]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[12]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[13]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[14]

pvf_reg_merging  -survived bar0_wr_byte_en[0] -deleted bar0_wr_byte_en[15]

pvf_reg_merging  -survived data_buf_128[0] -deleted data_buf_128[1]

pvf_reg_merging  -survived data_buf_128[0] -deleted data_buf_128[2]

pvf_reg_merging  -survived data_buf_128[0] -deleted data_buf_128[8]

pvf_reg_merging  -survived data_buf_128[0] -deleted data_buf_128[9]

pvf_reg_merging  -survived data_buf_128[0] -deleted data_buf_128[16]

pvf_reg_merging  -survived data_buf_128[0] -deleted data_buf_128[17]

pvf_reg_merging  -survived data_buf_128[0] -deleted data_buf_128[18]

pvf_reg_merging  -survived data_buf_128[32] -deleted data_buf_128[33]

pvf_reg_merging  -survived data_buf_128[32] -deleted data_buf_128[34]

pvf_reg_merging  -survived data_buf_128[32] -deleted data_buf_128[40]

pvf_reg_merging  -survived data_buf_128[32] -deleted data_buf_128[41]

pvf_reg_merging  -survived data_buf_128[32] -deleted data_buf_128[48]

pvf_reg_merging  -survived data_buf_128[32] -deleted data_buf_128[49]

pvf_reg_merging  -survived data_buf_128[32] -deleted data_buf_128[50]

pvf_reg_merging  -survived data_buf_128[64] -deleted data_buf_128[65]

pvf_reg_merging  -survived data_buf_128[64] -deleted data_buf_128[66]

pvf_reg_merging  -survived data_buf_128[64] -deleted data_buf_128[72]

pvf_reg_merging  -survived data_buf_128[64] -deleted data_buf_128[73]

pvf_reg_merging  -survived data_buf_128[64] -deleted data_buf_128[80]

pvf_reg_merging  -survived data_buf_128[64] -deleted data_buf_128[81]

pvf_reg_merging  -survived data_buf_128[64] -deleted data_buf_128[82]

pvf_reg_merging  -survived data_buf_128[96] -deleted data_buf_128[97]

pvf_reg_merging  -survived data_buf_128[96] -deleted data_buf_128[98]

pvf_reg_merging  -survived data_buf_128[96] -deleted data_buf_128[104]

pvf_reg_merging  -survived data_buf_128[96] -deleted data_buf_128[105]

pvf_reg_merging  -survived data_buf_128[96] -deleted data_buf_128[112]

pvf_reg_merging  -survived data_buf_128[96] -deleted data_buf_128[113]

pvf_reg_merging  -survived data_buf_128[96] -deleted data_buf_128[114]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[6]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[8]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[9]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[11]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[12]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[13]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[14]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_ba[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_ba[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[4]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[6]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[8]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[9]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[10]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[11]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[12]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[13]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[14]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[15]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[17]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[18]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[19]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[20]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[21]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[22]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[23]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[24]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[25]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[26]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[27]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[28]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[29]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[30]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[31]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[33]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[34]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[35]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[36]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[37]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[38]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[39]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[40]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[41]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[42]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[43]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[44]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[45]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[46]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[47]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[49]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[50]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[51]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[52]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[53]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[54]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[55]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[56]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[57]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[58]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[59]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[60]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[61]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[62]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[63]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[65]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[66]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[67]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[68]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[69]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[70]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[71]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[72]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[73]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[74]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[75]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[76]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[77]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[78]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[79]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[80]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[81]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[82]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[83]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[84]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[85]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[86]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[87]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[88]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[89]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[90]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[91]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[92]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[93]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[94]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[95]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[97]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[98]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[99]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[100]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[101]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[102]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[103]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[104]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[105]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[106]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[107]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[108]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[109]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[110]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[111]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[112]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[113]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[114]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[115]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[116]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[117]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[118]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[119]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[120]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[121]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[122]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[123]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[124]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[125]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[126]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata[127]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_ba[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_ba[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[6]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[8]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[9]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[11]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[12]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[13]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[14]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[6]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[5] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[8]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[9]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[10]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[11]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[12]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[5] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[13]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[14]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[5] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[15]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[18]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[17] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[19]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[20] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[22]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[21] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[23]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[24]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[17] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[25]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[16] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[26]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[17] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[27]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[20] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[28]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[21] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[29]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[20] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[30]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[21] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[31]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[34]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[33] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[35]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[36] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[38]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[37] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[39]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[40]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[33] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[41]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[32] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[42]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[33] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[43]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[36] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[44]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[37] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[45]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[36] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[46]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[37] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[47]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[50]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[49] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[51]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[52] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[54]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[53] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[55]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[56]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[49] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[57]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[48] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[58]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[49] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[59]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[52] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[60]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[53] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[61]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[52] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[62]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[53] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[63]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[66]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[65] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[67]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[68] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[70]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[69] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[71]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[72]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[65] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[73]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[64] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[74]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[65] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[75]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[68] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[76]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[69] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[77]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[68] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[78]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[69] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[79]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[80] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[82]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[81] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[83]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[84] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[86]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[85] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[87]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[80] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[88]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[81] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[89]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[80] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[90]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[81] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[91]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[84] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[92]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[85] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[93]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[84] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[94]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[85] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[95]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[98]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[97] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[99]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[100] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[102]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[101] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[103]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[104]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[97] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[105]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[96] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[106]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[97] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[107]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[100] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[108]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[101] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[109]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[100] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[110]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[101] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[111]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[112] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[114]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[113] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[115]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[116] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[118]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[117] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[119]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[112] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[120]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[113] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[121]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[112] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[122]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[113] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[123]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[116] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[124]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[117] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[125]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[116] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[126]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[117] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata[127]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[13] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[14]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[6]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[8]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[9]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[11]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[12]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[13]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[14]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ck[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ck[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ck[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ck[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[2] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[6] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[8] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[9]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[2] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[6] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[8] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_seq[9]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[10] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[11]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[10] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[12]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[10] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[13]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[10] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[14]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cke[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cke[2]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cke[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cke[3]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_misc[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_misc[1]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_misc[2] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_misc[3]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_pm[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_pm[1]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_pm[2] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_pm[3]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_reset[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_reset[1]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_reset[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_reset[2]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_reset[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_reset[3]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_misc[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_misc[2]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_pm[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_pm[2]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[1]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[12]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[13]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[14]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[15]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[16]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[17]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[18]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[19]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[20]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[21]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[22]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[23]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[24]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[25]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[26]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[27]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[28]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[29]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[30]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[31]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[12]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[13]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[14]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[15]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[16]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[17]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[18]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[19]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[20]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[21]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[22]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[23]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[24]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[25]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[26]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[27]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[28]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[29]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[30]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[31]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[12] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[14]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[11] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[15]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[19] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[21]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[24] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[26]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[27] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[28]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[27] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[29]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[27] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[30]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[27] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[31]

pvf_reg_merging  -survived coms1_reg_config/i2c_data[24] -deleted coms1_reg_config/i2c_data[25]

pvf_reg_merging  -survived coms1_reg_config/i2c_data[24] -deleted coms1_reg_config/i2c_data[26]

pvf_reg_merging  -survived coms1_reg_config/i2c_data[27] -deleted coms1_reg_config/i2c_data[28]

pvf_reg_merging  -survived coms1_reg_config/i2c_data[27] -deleted coms1_reg_config/i2c_data[29]

pvf_reg_merging  -survived coms1_reg_config/i2c_data[27] -deleted coms1_reg_config/i2c_data[30]

pvf_reg_merging  -survived coms1_reg_config/i2c_data[24] -deleted coms1_reg_config/i2c_data[31]

pvf_reg_merging  -survived coms2_reg_config/i2c_data[24] -deleted coms2_reg_config/i2c_data[25]

pvf_reg_merging  -survived coms2_reg_config/i2c_data[24] -deleted coms2_reg_config/i2c_data[26]

pvf_reg_merging  -survived coms2_reg_config/i2c_data[27] -deleted coms2_reg_config/i2c_data[28]

pvf_reg_merging  -survived coms2_reg_config/i2c_data[27] -deleted coms2_reg_config/i2c_data[29]

pvf_reg_merging  -survived coms2_reg_config/i2c_data[27] -deleted coms2_reg_config/i2c_data[30]

pvf_reg_merging  -survived coms2_reg_config/i2c_data[24] -deleted coms2_reg_config/i2c_data[31]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/o_cpld_byte_cnt[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/o_cpld_byte_cnt[11]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/o_mrd_addr[0] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/o_mrd_addr[1]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/o_mwr_addr[0] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/o_mwr_addr[1]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[11]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[12]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[13]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[14]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[15]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[16]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[17]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[18]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[19]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[20]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[21]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[22]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[23]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[24]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[25]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[26]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[27]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[28]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[30]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[31]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[32] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[33]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[32] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[34]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[32] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[35]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[36] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[37]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[36] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[38]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[36] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[39]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[46]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[47]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[48]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[49]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[50]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[96]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[97]

.fromstates blk_state[1] blk_state[0]
.tostates blk_state_reg[3] blk_state_reg[2] blk_state_reg[1] blk_state_reg[0]
.begin
00 0001
01 0010
10 0100
11 1000
.end


.fromstates curr_rd_reg[1] curr_rd_reg[0]
.tostates curr_rd_reg_reg[3] curr_rd_reg_reg[2] curr_rd_reg_reg[1] curr_rd_reg_reg[0]
.begin
00 0001
01 0010
10 0100
11 1000
.end


.fromstates curr_wr_reg[1] curr_wr_reg[0]
.tostates curr_wr_reg_reg[3] curr_wr_reg_reg[2] curr_wr_reg_reg[1] curr_wr_reg_reg[0]
.begin
00 0001
01 0010
10 0100
11 1000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[0]
.begin
0000 0000000001
0001 0000000010
0010 0000000100
0011 0000001000
0100 0000010000
0101 0000100000
0110 0001000000
0111 0010000000
1000 0100000000
1001 1000000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[0]
.begin
0000 0000001
0001 0000010
0010 0000100
0011 0001000
0100 0010000
0101 0100000
0110 1000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[0]
.begin
0000 00000001
0001 00000010
0010 00000100
0011 00001000
0100 00010000
0101 00100000
0110 01000000
0111 10000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[19] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[18] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[17] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[16] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[15] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[14] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[13] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[12] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[11] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[0]
.begin
00000 00000000000000000001
00001 00000000000000000010
00010 00000000000000000100
00011 00000000000000001000
00100 00000000000000010000
00101 00000000000000100000
00110 00000000000001000000
00111 00000000000010000000
01000 00000000000100000000
01001 00000000001000000000
01010 00000000010000000000
01011 00000000100000000000
01100 00000001000000000000
01101 00000010000000000000
01110 00000100000000000000
01111 00001000000000000000
10000 00010000000000000000
10001 00100000000000000000
10010 01000000000000000000
10011 10000000000000000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state_reg[0]
.begin
0000 001
0001 010
0010 100
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[0]
.begin
0000 00000001
0001 00000010
0010 00000100
0011 00001000
0100 00010000
0101 00100000
1001 01000000
1010 10000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]
.begin
0000 000000001
0001 000000010
0010 000000100
0011 000001000
0100 000010000
0101 000100000
0110 001000000
0111 010000000
1000 100000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[0]
.begin
0000 0000000001
0001 0000000010
0010 0000000100
0011 0000001000
0100 0000010000
0101 0000100000
0110 0001000000
0111 0010000000
1000 0100000000
1001 1000000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state[3] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state[2] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state[1] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[0]
.begin
0000 0000000001
0001 0000000010
0010 0000000100
0011 0000001000
0100 0000010000
0101 0000100000
0110 0001000000
0111 0010000000
1000 0100000000
1001 1000000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state[1] u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]
.begin
00 0001
01 0010
10 0100
11 1000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state[3] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state[2] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state[1] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]
.begin
0000 00000000001
0001 00000000010
0010 00000000100
0011 00000001000
0100 00000010000
0101 00000100000
0110 00001000000
0111 00010000000
1000 00100000000
1001 01000000000
1010 10000000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[0]
.begin
000 000001
001 000010
010 000100
011 001000
100 010000
101 100000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[13] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[12] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[11] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[0]
.begin
0000 00000000000001
0001 00000000000010
0010 00000000000100
0011 00000000001000
0100 00000000010000
0101 00000000100000
0110 00000001000000
0111 00000010000000
1000 00000100000000
1001 00001000000000
1010 00010000000000
1011 00100000000000
1100 01000000000000
1101 10000000000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[0]
.begin
000 0000001
001 0000010
010 0000100
011 0001000
100 0010000
101 0100000
110 1000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[0]
.begin
000 00001
001 00010
010 00100
011 01000
100 10000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[0]
.begin
0000 0000001
0001 0000010
0010 0000100
0011 0001000
0100 0010000
0101 0100000
0110 1000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[0]
.begin
0000 0000001
0001 0000010
0010 0000100
0011 0001000
0100 0010000
0101 0100000
0110 1000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[11] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[0]
.begin
0000 000000000001
0001 000000000010
0010 000000000100
0011 000000001000
0100 000000010000
0101 000000100000
0110 000001000000
0111 000010000000
1000 000100000000
1001 001000000000
1010 010000000000
1011 100000000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[0]
.begin
000 000001
001 000010
010 000100
011 001000
100 010000
101 100000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[13] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[12] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[11] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[0]
.begin
0000 00000000000001
0001 00000000000010
0010 00000000000100
0011 00000000001000
0100 00000000010000
0101 00000000100000
0110 00000001000000
0111 00000010000000
1000 00000100000000
1001 00001000000000
1010 00010000000000
1011 00100000000000
1100 01000000000000
1101 10000000000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[0]
.begin
000 0000001
001 0000010
010 0000100
011 0001000
100 0010000
101 0100000
110 1000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[0]
.begin
000 00001
001 00010
010 00100
011 01000
100 10000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[0]
.begin
0000 0000001
0001 0000010
0010 0000100
0011 0001000
0100 0010000
0101 0100000
0110 1000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[0]
.begin
0000 0000001
0001 0000010
0010 0000100
0011 0001000
0100 0010000
0101 0100000
0110 1000000
.end


.fromstates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[0]
.tostates u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[11] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[0]
.begin
0000 000000000001
0001 000000000010
0010 000000000100
0011 000000001000
0100 000000010000
0101 000000100000
0110 000001000000
0111 000010000000
1000 000100000000
1001 001000000000
1010 010000000000
1011 100000000000
.end


.fromstates u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state[2] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state[1] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state[0]
.tostates u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state_reg[4] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state_reg[3] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state_reg[2] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state_reg[1] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state_reg[0]
.begin
000 00001
001 00010
010 00100
011 01000
100 10000
.end


.fromstates u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[5] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[4] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[3] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[2] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[1] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[0]
.tostates u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[5] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[4] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[3] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[2] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[0]
.begin
000001 000001
000010 000010
000100 000100
001000 001000
010000 010000
100000 100000
.end


.fromstates u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state[1] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state[0]
.tostates u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state_reg[3] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state_reg[2] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state_reg[0]
.begin
00 0001
01 0010
10 0100
11 1000
.end


.fromstates u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt[1] u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt[0]
.tostates u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]
.begin
00 01
11 10
.end


.fromstates u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt[3] u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt[2]
.tostates u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]
.begin
00 01
11 10
.end


pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_odt[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_odt[1]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_odt[2] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_odt[3]

.fromstates u_ddr3/u_ips_ddrc_top/mcdq_lp/state[9] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[8] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[7] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[6] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[5] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[4] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[3] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[2] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[1] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[0]
.tostates u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[9] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[8] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[7] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[6] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[5] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[4] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[3] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[2] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[0]
.begin
0000000001 0000000001
0000000010 0000000010
0000000100 0000000100
0000001000 0000001000
0000010000 0000010000
0000100000 0000100000
0001000000 0001000000
0010000000 0010000000
0100000000 0100000000
1000000000 1000000000
.end


.fromstates u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[6] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[5] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[4] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[3] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[2] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[1] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[0]
.tostates u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[6] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[5] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[4] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[3] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[2] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[0]
.begin
0000001 0000001
0000010 0000010
0000100 0000100
0001000 0001000
0010000 0010000
0100000 0100000
1000000 1000000
.end


.fromstates u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state[2] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state[1] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state[0]
.tostates u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[6] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[3] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]
.begin
000 0000001
001 0000010
010 0000100
011 0001000
100 0010000
101 0100000
110 1000000
.end


.fromstates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm[0]
.tostates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[0]
.begin
0000 000000001
0001 000000010
0010 000000100
0011 000001000
0100 000010000
0101 000100000
0110 001000000
0111 010000000
1000 100000000
.end


.fromstates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done[0]
.tostates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done_reg[0]
.begin
0000 0001
0001 0010
0011 0100
1111 1000
.end


.fromstates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[0]
.tostates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[9] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[0]
.begin
0000 0000000001
0001 0000000010
0010 0000000100
0011 0000001000
0100 0000010000
0101 0000100000
0110 0001000000
0111 0010000000
1000 0100000000
1001 1000000000
.end


.fromstates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[0]
.tostates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[9] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[0]
.begin
0000 0000000001
0001 0000000010
0010 0000000100
0011 0000001000
0100 0000010000
0101 0000100000
0110 0001000000
0111 0010000000
1000 0100000000
1001 1000000000
.end


.fromstates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[0]
.tostates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[9] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[0]
.begin
0000 0000000001
0001 0000000010
0010 0000000100
0011 0000001000
0100 0000010000
0101 0000100000
0110 0001000000
0111 0010000000
1000 0100000000
1001 1000000000
.end


.fromstates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[0]
.tostates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[9] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[0]
.begin
0000 0000000001
0001 0000000010
0010 0000000100
0011 0000001000
0100 0000010000
0101 0000100000
0110 0001000000
0111 0010000000
1000 0100000000
1001 1000000000
.end


.fromstates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm[0]
.tostates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[0]
.begin
0000 000000001
0001 000000010
0010 000000100
0011 000001000
0100 000010000
0101 000100000
0110 001000000
0111 010000000
1000 100000000
.end


pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[14] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[27]

.fromstates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_pcie_seio/seio_state[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_pcie_seio/seio_state[0]
.tostates u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_pcie_seio/seio_state_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_pcie_seio/seio_state_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_pcie_seio/seio_state_reg[0]
.begin
00 001
01 010
10 100
.end


.fromstates coms1_reg_config/config_step[1] coms1_reg_config/config_step[0]
.tostates coms1_reg_config/config_step_reg[2] coms1_reg_config/config_step_reg[1] coms1_reg_config/config_step_reg[0]
.begin
00 001
01 010
10 100
.end


.fromstates coms2_reg_config/config_step[1] coms2_reg_config/config_step[0]
.tostates coms2_reg_config/config_step_reg[2] coms2_reg_config/config_step_reg[1] coms2_reg_config/config_step_reg[0]
.begin
00 001
01 010
10 100
.end


.fromstates i2cSlave_u/u_serialInterface/CurrState_SISt[3] i2cSlave_u/u_serialInterface/CurrState_SISt[2] i2cSlave_u/u_serialInterface/CurrState_SISt[1] i2cSlave_u/u_serialInterface/CurrState_SISt[0]
.tostates i2cSlave_u/u_serialInterface/CurrState_SISt_reg[15] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[14] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[13] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[12] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[11] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[10] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[9] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[8] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[7] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[6] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[5] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[4] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[3] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[2] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[1] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[0]
.begin
0000 0000000000000001
0001 0000000000000010
0010 0000000000000100
0011 0000000000001000
0100 0000000000010000
0101 0000000000100000
0110 0000000001000000
0111 0000000010000000
1000 0000000100000000
1001 0000001000000000
1010 0000010000000000
1011 0000100000000000
1100 0001000000000000
1101 0010000000000000
1110 0100000000000000
1111 1000000000000000
.end


.fromstates i2cSlave_u/u_serialInterface/streamSt[1] i2cSlave_u/u_serialInterface/streamSt[0]
.tostates i2cSlave_u/u_serialInterface/streamSt_reg[3] i2cSlave_u/u_serialInterface/streamSt_reg[2] i2cSlave_u/u_serialInterface/streamSt_reg[1] i2cSlave_u/u_serialInterface/streamSt_reg[0]
.begin
00 0001
01 0010
10 0100
11 1000
.end


.fromstates u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/state[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/state[0]
.tostates u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/state_reg[2] u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/state_reg[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/state_reg[0]
.begin
00 001
01 010
10 100
.end


.fromstates u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/state[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/state[0]
.tostates u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/state_reg[2] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/state_reg[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/state_reg[0]
.begin
00 001
01 010
10 100
.end


.fromstates u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/state[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/state[0]
.tostates u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/state_reg[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/state_reg[0]
.begin
00 01
01 10
.end


.fromstates u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/state[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/state[0]
.tostates u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/state_reg[2] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/state_reg[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/state_reg[0]
.begin
00 001
01 010
10 100
.end


.fromstates u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[8] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[7] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[6] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[5] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[4] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[3] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[2] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[1] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[0]
.tostates u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[13] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[12] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[11] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[10] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[9] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[8] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[7] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[6] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[5] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[4] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[3] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[2] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[1] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[0]
.begin
000000000 00000000000001
000000001 00000000000010
000000010 00000000000100
000000011 00000000001000
000000100 00000000010000
000000101 00000000100000
000000110 00000001000000
000000111 00000010000000
000001000 00000100000000
000001001 00001000000000
000001010 00010000000000
000001011 00100000000000
000001100 01000000000000
000001101 10000000000000
.end


pvf_reg_constant data_buf_128[0] 0

pvf_reg_constant data_buf_128[32] 0

pvf_reg_constant data_buf_128[64] 0

pvf_reg_constant data_buf_128[96] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/genblk2.init_ba[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_address[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_ba[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_address[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[13] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_address[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ck[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_info/mr0[15] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_info/mr1[15] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_info/mr2[15] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_info/mr3[15] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[10] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_cas_n[3] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_cs_n[3] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_ras_n[3] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_we_n[3] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_we_n[1] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_bank[2] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[8] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[19] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[20] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[30] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[31] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[41] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_0[42] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_1[8] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_1[19] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_1[20] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_1[30] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_1[31] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_1[41] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_TDATA_X2.P_TDATA_1[42] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/lx_deemph[1] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_misc[1] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/phy_mac_phystatus_pm[1] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/P_LX_RX_CKDIV[1] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_PMA_TX_RATE[2] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/dbi_addr[0] 0

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[14]

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_addr[1] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/dbi_din[0] 0

pvf_reg_merging  -survived coms1_reg_config/i2c_data[0] -deleted coms1_reg_config/i2c_data[24]

pvf_reg_constant coms1_reg_config/i2c_data[0] 0

pvf_reg_constant coms1_reg_config/i2c_data[27] 1

pvf_reg_merging  -survived coms2_reg_config/i2c_data[0] -deleted coms2_reg_config/i2c_data[24]

pvf_reg_constant coms2_reg_config/i2c_data[0] 0

pvf_reg_constant coms2_reg_config/i2c_data[27] 1

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/o_cpld_byte_cnt[10] 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/o_mrd_addr[0] 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/o_mwr_addr[0] 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/o_trgt1_radm_pkt_halt[2] 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tdata[10] 0

pvf_reg_constant u_uart2apb_top/u_uart_top/u_pgr_uart_tx/shift_reg[11] 1

pvf_reg_constant u_uart2apb_top/u_uart_top/u_pgr_uart_tx/shift_reg[10] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/u_force_read_clk_ctrl_sync/sig_async_r1[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/u_force_samp_position_sync/sig_async_r1[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/u_samp_position_dyn_adj_sync/sig_async_r1[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/u_wrcal_position_dyn_adj_sync/sig_async_r1[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/debug_cpd_offset_adj_d[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/debug_cpd_offset_adj_d[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/debug_cpd_offset_adj_d[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/ddrphy_update_sync[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/ddrphy_update_sync[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/dbg_cpd_start_d[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/dbg_cpd_start_d[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/dbg_cpd_start_d[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gate_start_d[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gate_start_d[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gate_start_d[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gpll_scan_rst_d[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gpll_scan_rst_d[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_dly[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_dly[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_dly[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_addr[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_addr[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_addr[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_addr[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_addr[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_addr[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_addr[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_addr[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_sel 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[8] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[9] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[10] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[11] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[12] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[13] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[14] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_wdata[15] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_write 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[10] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[11] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[12] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[13] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[14] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/ddr_zqcs_req_d[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/ddr_zqcs_req_d[1] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/mac_clk_req_n_sync/sig_async_ff 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/link_num_sync/sig_async_ff 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/link_num_synced[0] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/link_num_synced[1] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/word_align_multi_sw_sync/sig_async_ff 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_sync/sig_async_ff 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/word_align_multi_sw_sync/sig_async_ff 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_sync/sig_async_ff 0

pvf_reg_constant u_ddr3/u_ddrphy_top/u_force_read_clk_ctrl_sync/sig_async_r2[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/u_force_samp_position_sync/sig_async_r2[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/u_samp_position_dyn_adj_sync/sig_async_r2[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/u_wrcal_position_dyn_adj_sync/sig_async_r2[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/comp_val[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/comp_val[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[3] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[3] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[3] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[3] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ba_d[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ba_d[4] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ba_d[5] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ba_d[9] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ba_d[10] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ba_d[11] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_refresh_gen[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/sync_src_dly[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/sync_src_dly[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_addr[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_addr[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_addr[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_addr[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_addr[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_addr[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_addr[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_addr[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/sync_src_p_sel[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/sync_src_p_sel[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[8] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[9] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[10] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[11] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[12] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[13] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[14] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_wdata[15] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_des_p_write 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_bank[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[36] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[36] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/mac_clk_req_n_sync/sig_synced 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/link_num_sync/sig_synced 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/word_align_multi_sw_sync/sig_synced 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_sync/sig_synced 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/word_align_multi_sw_sync/sig_synced 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_sync/sig_synced 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/u_cpld_req_fifo/genblk1.rd_data_ff1[0] 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/u_cpld_req_fifo/genblk1.rd_data_ff1[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/samp_position_dyn_adj_d1 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/samp_position_dyn_adj_d1 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/wrcal_position_dyn_adj_d1 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/wrcal_position_dyn_adj_d1 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/debug_cpd_offset_adj_pos 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_cs_n_r[3] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_ras_n_r[3] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_cas_n_r[3] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_we_n_r[3] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_ba_r[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_ba_r[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_ba_r[5] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_ba_r[7] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_ba_r[9] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_ba_r[11] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_ck_dly_flag 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_ck_dly_flag 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_req[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_req[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[9] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[11] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[13] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[14] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[15] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[8] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[9] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[10] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[11] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[12] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[13] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[14] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[15] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[8] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[9] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[10] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[11] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[12] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[13] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[14] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr2[15] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[8] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[9] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[10] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[11] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[12] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[13] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[14] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr3[15] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/word_align_d 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/word_align_d 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/trig_en 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r1[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r1[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_ck_dly_pass 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_ck_dly_pass 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/des_dly[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/des_dly[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/ctrl_clear[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/ctrl_clear[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/ctrl_clear[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_trigger_bit[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_trigger_bit[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_trigger_bit[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_trigger_bit[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[5] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[8] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[10] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr0[12] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[2] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mr1[4] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r2[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r2[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r3[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r3[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/lp_pd_req 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mrs_req 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/norm_req 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/lp_sr_req 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/pd_en 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/sr_en 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/sr_en_dly 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/pd_en_dly 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/pre_ap 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/pre_id[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/pre_id[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/pre_id[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[36] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[36] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_ap 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[34] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[35] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[36] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[34] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[35] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[36] 0

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem_r1 -deleted u_pclk_core_rstn_sync/sig_async_ff

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/dll_update_d1 -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/dll_update_d1

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dqs_gate_comp_done -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dqs_gate_comp_done

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3:0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3:0]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r1 -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r1

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_cke -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_cke

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_cke -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cke

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_cke -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_cke

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/eye_calibration_d -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/eye_calibration_d

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/u_core_rstn_sync/sig_async_ff -deleted u_ref_core_rstn_sync/sig_async_ff

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_sync/sig_async_ff -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/st_recvr_multi_sw_sync/sig_async_ff

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_sync/sig_async_ff -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_sync/sig_async_ff

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/rdel_calibration_d -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/rdel_calibration_d

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/ips2l_pcie_dma_cpld_wr_ctrl/wr_start_ff -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/wr_start_ff

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/u_core_rstn_sync/sig_synced -deleted u_ref_core_rstn_sync/sig_synced

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/rdel_cal_vld -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/rdel_cal_vld

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2 -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/core_rst_n_mem -deleted u_pclk_core_rstn_sync/sig_synced

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_sync/sig_synced -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/st_recvr_multi_sw_sync/sig_synced

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_sync/sig_synced -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_sync/sig_synced

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/addr_ram_wr_en -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/ips2l_pcie_dma_cpld_wr_ctrl/first_dw_ff

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[16]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[17]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[18]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[19]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[20]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[21]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[22]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[23]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[24]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[25]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[26]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[27]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[28]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[29]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[45]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[46]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[47]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[48]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[49]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[50]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[51]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[52]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[53]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[54]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[55]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[56]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[57]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[58]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[59]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_odt_d[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_odt_d[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_odt_d[2] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_odt_d[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[9]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[11]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[13]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[15]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[17]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[19]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[21]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[23]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[25]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[27]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[29]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[31]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[33]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[35]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[37]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[39]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[41]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[43]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[45]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[47]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[49]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[51]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[53]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[55]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[57]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[59]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_odt_r[2] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_odt_r[3]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[9]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[10]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[11]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[12]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[13]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[14]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[15]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wdin_en[2] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wdin_en[3]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly[2] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly[3]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[9]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[10]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[11]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[12]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[13]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[14]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[15]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_address[27] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_address[28]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_address[27] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_address[29]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_cke[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_cke[2]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_cke[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_cke[3]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[35]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[36]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[1]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[3]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[2] -deleted u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[4]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[6]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[7]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[5] -deleted u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[8]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[9]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[11] -deleted u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[13]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[11] -deleted u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[14]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[1]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[2]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[1]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[2]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[34] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[35]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[34] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[36]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/ips2l_pcie_dma_cpld_wr_ctrl/dwbe[3] -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_cpld_wr_ctrl/ips2l_pcie_dma_cpld_wr_ctrl/dwbe[4]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_cke_d[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_cke_d[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_cke_d[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_cke_d[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_cke_d[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_cke_d[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_cke_d[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_cke_d[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_cke_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_cke_r[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_cke_r[1] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_cke_r[3]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[4] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[5]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[4] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[6]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[4] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[7]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[9]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[10]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[11]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[12] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[13]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[12] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[14]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[12] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[15]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[4] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[5]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[4] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[6]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[4] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[7]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[1]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[3]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[2] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[4]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[6]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[7]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[5] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[8]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[9]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[11] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[13]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[11] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[14]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_address[27] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_address[28]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_address[27] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_address[29]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[34] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[35]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[34] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[36]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[2]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[42] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[43]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[42] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[44]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[50] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[54]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[50] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[58]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[1]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[2]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[3]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[2]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[3]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[2]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[3]

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_calib_mux/calib_ba[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_we_n[1] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[11] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_done 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[6] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[7] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[8] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_done 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[6] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[7] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[8] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[34] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[1] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_address[11] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_we_n_r[1] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[34] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cas_n[1] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cs_n[1] 1

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[5] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_cs_n[1] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_ras_n[1] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_cas_n[1] 1

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[3] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[1] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[1] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[1] 1

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[0] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[1] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[2] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[3] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[4] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[5] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[6] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[7] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[0] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[1] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[2] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[3] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[4] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[5] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[6] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_align_wait_timr[7] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_cs_n_r[1] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_ras_n_r[1] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_refresh_gen[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_cas_n_r[1] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r1[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r1[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r2[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r2[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r3[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r3[1] 0

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_PCS_CB_RSTN -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_PCS_RX_RSTN

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_PCS_CB_RSTN -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_PCS_RX_RSTN

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[4]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[6]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[4]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[6]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[4]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[6]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_step[7]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[8]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[9]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[10]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[11]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[12]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[13]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[14]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[15]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[16]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[8]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[9]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[10]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[11]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[12]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[13]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[14]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[15]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[16]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[8]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[9]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[10]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[11]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[12]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[13]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[14]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[15]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[16]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[8]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[9]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[10]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[11]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[12]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[13]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[14]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[15]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[16]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/rom_raddr[6] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/rom_raddr[7]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/rom_raddr[6] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/rom_raddr[8]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/rom_raddr[6] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/rom_raddr[9]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[4]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[6]

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/dfi_phyupd_req 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/lp_status 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mrs_en 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[0] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[8] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[9] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/zqcs_req 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/init_cntr[7] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_IPS2L_PCIE_CFG_SPACE_INIT/rom_raddr[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/dfi_phyupd_ack 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_gray[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/update_req 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/update_req_r 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/count[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/count[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/count[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/count[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/count[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/count[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/count[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_lp/count[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act2wr_pass/r_cnt_pass 0

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cas_n[1:0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cs_n[1:0]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cas_n[1:0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_we_n[1:0]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[4] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[2]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_cke[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_cke[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_cke_d[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_cke_d[1]

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_zqcs 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[6] 0

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff_sample_done -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff_sample_done

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/ptr -deleted u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/wptr

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_comb_r[1:0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_comb_r[1:0]

pvf_reg_merging  -survived coms1_reg_config/clock_20k -deleted coms2_reg_config/clock_20k

pvf_reg_merging  -survived coms1_reg_config/clock_20k_cnt[10:0] -deleted coms2_reg_config/clock_20k_cnt[10:0]

pvf_reg_merging  -survived myReg0_w[7:0] -deleted myReg1_w[7:0]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r1[3:0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r1[3:0]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r2[3:0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r2[3:0]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r3[3:0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_dqs_gate_coarse_cal/read_cmd_mux_r3[3:0]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[2]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[6]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[8]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[9]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[10]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[4] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[11]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[12] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[13]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[12] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[14]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[12] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[15]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[2] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[2] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[4]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[2] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[6] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[1]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[2] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[2] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[4]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[2] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[5]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[6] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[7]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[7:0] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r[7:0]

pvf_reg_constant ddr_wr_cnt_26[0] 0

pvf_reg_constant ddr_wr_cnt_26[1] 0

pvf_reg_constant ddr_wr_cnt_26[2] 0

pvf_reg_constant myReg0_w[0] 1

pvf_reg_constant myReg0_w[1] 0

pvf_reg_constant myReg0_w[2] 0

pvf_reg_constant myReg0_w[3] 0

pvf_reg_constant myReg0_w[4] 0

pvf_reg_constant myReg0_w[5] 0

pvf_reg_constant myReg0_w[6] 0

pvf_reg_constant myReg0_w[7] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/cnt[5] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/cnt[6] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/cnt[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[0] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[0] 1

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[1] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done_reg[3] 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/cpld_addr[0] 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/cpld_addr[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cnt[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cnt[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cnt[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mr_addr[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mr_addr[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mr_addr[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_done 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/ref_tri_r 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/cnt_a[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/cnt_a[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/cnt_a[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/cnt_b[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/cnt_b[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/cnt_b[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/cnt_b[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/cnt_b[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mrs_status 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[12] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_cmd[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_cmd[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_cmd[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_addr[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_bank[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_mrs/mrs_bank[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/update_cal_req 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/next_len[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/pre_len[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt0[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt0[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[0] 0

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_address[26] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_address[27]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly[2] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/calib_done_r -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[15]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wr_enable_d -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_wrdata_en[3]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/rdcal_wrdata_en[3] -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/wr_enable_d

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_cke -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_ck[0]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_cke[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_strb[8]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[12] -deleted u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[8]

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[0] -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[0]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_address[26] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_address[27]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[41] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[42]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[46] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[50]

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[6] 0

pvf_reg_constant ddr_rd_cnt_26[0] 0

pvf_reg_constant ddr_rd_cnt_26[1] 0

pvf_reg_constant ddr_rd_cnt_26[2] 0

pvf_reg_constant ddr_rd_cnt_26[3] 0

pvf_reg_constant ddr_rd_cnt_26[4] 0

pvf_reg_constant ddr_rd_cnt_26[5] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[6] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_value[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/cnt[4] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/cnt[5] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/cnt[6] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/cnt[7] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_value[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/cnt[4] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/cnt[5] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/cnt[6] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/cnt[7] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[8] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[8] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[9] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[9] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[10] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[10] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/update_start 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[5] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state_reg[0] 1

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state_reg[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/pre_addr[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/pre_addr[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/pre_addr[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[5] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[8] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[8] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[9] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[9] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[10] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[10] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/dqs_gate_comp_en 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/comp_dir[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/comp_dir[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/comp_val[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/comp_val[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dqs_gate_comp_done 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/update_done 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_dfi/ddrphy_update_done 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/cnt[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/cnt[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/cnt[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/cnt[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/cnt[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[0] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[4] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[3] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[6] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[7] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[2] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[1] 0

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[2] 0

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_address[16] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_address[26]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_address[16] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_address[17]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_address[16] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_address[17]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_address[16] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mux_dfi_address[26]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[31] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[32]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[31] -deleted u_ddr3/u_ddrphy_top/ddrphy_dfi/phy_addr_d[41]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[6] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[10]

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[6] -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r[46]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2] -deleted u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[2]
