#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: D:\pds2022_sp6_4\PDS_2022.2-SP6.4\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.22631
#Hostname: DESKTOP-50P54KS
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Wed Jan  8 10:11:02 2025
License checkout: fabric_ads from D:\pds_2022_1\PDS_2022.1\license\new_pds_F4A80DA47D72.lic
Compiling verification operator library.
Loading technology operator library.
Compiling technology operator library.
Compiling technology operator (valence) library.
I: Enable Verilog2k features and keywords
Start rtl-analyze.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/prbs15_64bit_v1_0.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/prbs15_64bit_v1_0.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/prbs15_64bit_v1_0.v(line number: 9)] Analyzing module prbs15_64bit_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/prbs15_64bit_v1_0.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/prbs31_128bit_v1_0.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/prbs31_128bit_v1_0.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/prbs31_128bit_v1_0.v(line number: 15)] Analyzing module prbs31_128bit_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/prbs31_128bit_v1_0.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/axi_bist_top_v1_0.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/axi_bist_top_v1_0.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/axi_bist_top_v1_0.v(line number: 9)] Analyzing module axi_bist_top_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/axi_bist_top_v1_0.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_main_ctrl_v1_0.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_main_ctrl_v1_0.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_main_ctrl_v1_0.v(line number: 7)] Analyzing module test_main_ctrl_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_main_ctrl_v1_0.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_rd_ctrl_v1_0.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_rd_ctrl_v1_0.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_rd_ctrl_v1_0.v(line number: 2)] Analyzing module test_rd_ctrl_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_rd_ctrl_v1_0.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_wr_ctrl_v1_0.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_wr_ctrl_v1_0.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_wr_ctrl_v1_0.v(line number: 2)] Analyzing module test_wr_ctrl_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_wr_ctrl_v1_0.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_rd_lock.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_rd_lock.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_rd_lock.v(line number: 2)] Analyzing module uart_rd_lock (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_rd_lock.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 12)] Analyzing module test_ddr (library work)
I: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 78)] Convert attribute name from syn_keep to PAP_KEEP
I: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 79)] Convert attribute name from syn_keep to PAP_KEEP
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 54)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 55)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 56)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 321)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 329)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 341)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 347)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 353)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 357)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 362)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 366)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 370)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 378)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 382)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 386)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 390)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 394)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 717)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_clk_gen_32bit.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_clk_gen_32bit.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_clk_gen_32bit.v(line number: 15)] Analyzing module ips2l_clk_gen_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_clk_gen_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_cmd_parser_32bit.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_cmd_parser_32bit.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_cmd_parser_32bit.v(line number: 15)] Analyzing module ips2l_cmd_parser_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_cmd_parser_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_rs232_intf.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_rs232_intf.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_rs232_intf.v(line number: 15)] Analyzing module ips2l_seu_rs232_intf (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_rs232_intf.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_rx.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_rx.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_rx.v(line number: 15)] Analyzing module ips2l_seu_uart_rx (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_rx.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_tx.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_tx.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_tx.v(line number: 15)] Analyzing module ips2l_seu_uart_tx (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_tx.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_32bit.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_32bit.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_32bit.v(line number: 15)] Analyzing module ips2l_uart_ctrl_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_top_32bit.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_top_32bit.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_top_32bit.v(line number: 15)] Analyzing module ips2l_uart_ctrl_top_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_top_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_ver_ctrl_32bit.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_ver_ctrl_32bit.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_ver_ctrl_32bit.v(line number: 15)] Analyzing module ips2l_ver_ctrl_32bit (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_ver_ctrl_32bit.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc.v(line number: 1)] Analyzing module ADC (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc_ctrl.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc_ctrl.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc_ctrl.v(line number: 1)] Analyzing module adc_ctrl (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc_ctrl.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Analyzing module ips2l_rst_sync_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp(line number: 183)] Analyzing module ips2l_ddrphy_wrlvl_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 495)] Analyzing module ips2l_ddrphy_wrcal_v1_7 (library work)
I: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 514)] Convert attribute name from syn_preserve to PAP_PRESERVE
I: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 515)] Convert attribute name from syn_preserve to PAP_PRESERVE
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp(line number: 232)] Analyzing module ips2l_ddrphy_wdata_path_adj_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp(line number: 151)] Analyzing module ips2l_ddrphy_upcal_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp(line number: 83)] Analyzing module ips2l_ddrphy_training_ctrl_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp(line number: 108)] Analyzing module ips2l_ddrphy_slice_rddata_align_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 268)] Analyzing module ips2l_ddrphy_reset_ctrl_v1_3 (library work)
I: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 298)] Convert attribute name from syn_preserve to PAP_PRESERVE
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp(line number: 750)] Analyzing module ips2l_ddrphy_rdcal_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp(line number: 196)] Analyzing module ips2l_ddrphy_main_ctrl_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp(line number: 577)] Analyzing module ips2l_ddrphy_init_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp(line number: 174)] Analyzing module ips2l_ddrphy_info_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp(line number: 243)] Analyzing module ips2l_ddrphy_gatecal_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp(line number: 100)] Analyzing module ips2l_ddrphy_gate_update_ctrl_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp(line number: 228)] Analyzing module ips2l_ddrphy_eyecal_v1_5 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp(line number: 112)] Analyzing module ips2l_ddrphy_drift_ctrl_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp(line number: 395)] Analyzing module ips2l_ddrphy_dqsi_rdel_cal_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp(line number: 527)] Analyzing module ips2l_ddrphy_dqs_rddata_align_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp(line number: 173)] Analyzing module ips2l_ddrphy_dqs_gate_coarse_cal_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp(line number: 124)] Analyzing module ips2l_ddrphy_dll_update_ctrl_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp(line number: 320)] Analyzing module ips2l_ddrphy_dfi_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp(line number: 69)] Analyzing module ips2l_ddrphy_gpll_phase_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp(line number: 292)] Analyzing module ips2l_ddrphy_data_slice_wrlvl_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 278)] Analyzing module ips2l_ddrphy_data_slice_wrcal_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 583)] Analyzing module ips2l_ddrphy_data_slice_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp(line number: 111)] Analyzing module ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp(line number: 182)] Analyzing module ips2l_ddrphy_cpd_ctrl_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp(line number: 71)] Analyzing module ips2l_ddrphy_cpd_lock_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp(line number: 134)] Analyzing module ips2l_ddrphy_control_path_adj_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 392)] Analyzing module ips2l_ddrphy_calib_top_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp(line number: 199)] Analyzing module ips2l_ddrphy_calib_mux_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp(line number: 84)] Analyzing module ips2l_ddrphy_rst_debounce_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp(line number: 104)] Analyzing module ips2l_ddrphy_rst_clk_phase_adj_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 127)] Analyzing module ips2l_ddrphy_gpll_v1_3 (library work)
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 154)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 155)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 156)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 157)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 158)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 242)] Analyzing module ips2l_ddrphy_ppll_v1_0 (library work)
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 261)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 262)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 263)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 264)] Ansi_parameter force parameter in body to localparam
W: Verilog-2006: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 265)] Ansi_parameter force parameter in body to localparam
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp(line number: 145)] Analyzing module ips2l_mcdq_apb_cross_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp(line number: 101)] Analyzing module ips2l_mcdq_calib_delay_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp(line number: 559)] Analyzing module ips2l_mcdq_cfg_apb_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp(line number: 243)] Analyzing module ips2l_mcdq_dcd_bm_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp(line number: 76)] Analyzing module ips2l_mcdq_dcd_rowaddr_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp(line number: 209)] Analyzing module ips2l_mcdq_dcd_sm_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp(line number: 174)] Analyzing module ips2l_mcdq_dcd_top_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 643)] Analyzing module ips2l_mcdq_dcp_back_ctrl_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp(line number: 298)] Analyzing module ips2l_mcdq_dcp_buf_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp(line number: 210)] Analyzing module ips2l_mcdq_dcp_out_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp(line number: 329)] Analyzing module ips2l_mcdq_dcp_top_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp(line number: 432)] Analyzing module ips2l_mcdq_dfi_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp(line number: 315)] Analyzing module ips2l_mcdq_lp_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp(line number: 321)] Analyzing module ips2l_mcdq_mrs_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp(line number: 95)] Analyzing module ips2l_mcdq_prefetch_fifo_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp(line number: 83)] Analyzing module ips2l_mcdq_rdatapath_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp(line number: 78)] Analyzing module ips2l_mcdq_reg_fifo2_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp(line number: 271)] Analyzing module ips2l_mcdq_ui_axi_v1_2a (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp(line number: 171)] Analyzing module ips2l_mcdq_wdatapath_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp(line number: 140)] Analyzing module ips2l_mcdq_wdp_align_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp(line number: 133)] Analyzing module ips2l_mcdq_wdp_dcp_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 619)] Analyzing module ips2l_mcdq_wrapper_v1_2b (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Analyzing module ips2l_mcdq_com_timing_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp(line number: 128)] Analyzing module ips2l_mcdq_tfaw_timing_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp(line number: 68)] Analyzing module ips2l_mcdq_tfaw_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp(line number: 115)] Analyzing module ips2l_mcdq_timing_act2wr_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp(line number: 92)] Analyzing module ips2l_mcdq_timing_act_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Analyzing module ips2l_mcdq_timing_pre_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp(line number: 128)] Analyzing module ips2l_mcdq_timing_rd_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp(line number: 90)] Analyzing module ips2l_mcdq_timing_ref_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp(line number: 127)] Analyzing module ips2l_mcdq_timing_wr_pass_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Analyzing module ips2l_mcdq_trc_timing_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 130)] Analyzing module ips2l_distributed_fifo_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp(line number: 269)] Analyzing module ips2l_distributed_fifo_ctr_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 130)] Analyzing module ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 120)] Analyzing module ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0 (library work)
I: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 129)] Convert attribute name from syn_ramstyle to PAP_RAM_STYLE
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3.v(line number: 12)] Analyzing module ddr3 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 12)] Analyzing module ddr3_ddrphy_top (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v successfully.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v
I: Verilog-0001: Analyzing file D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v
I: Verilog-0002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 12)] Analyzing module ddr3_slice_top_v1_10 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr} D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v successfully.
I: Module "test_ddr" is set as top module.
Executing : rtl-analyze successfully. Time elapsed: 1.723s wall, 0.078s user + 0.000s system = 0.078s CPU (4.5%)

Start rtl-elaborate.
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 12)] Elaborating module test_ddr
I: Module instance {test_ddr} parameter value:
    MEM_ROW_WIDTH = 32'b00000000000000000000000000001111
    MEM_COLUMN_WIDTH = 32'b00000000000000000000000000001010
    MEM_BANK_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    TH_1S = 27'b001111101111000101001000000
    REM_DQS_WIDTH = 32'b00000000000000000000000000000111
    DFT_CTRL_BUS_0 = 32'b00000000000000000001000000000001
    DFT_CTRL_BUS_1 = 32'b00000000000000000000000000000001
    DFT_CTRL_BUS_2 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_3 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_4 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_5 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_6 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_7 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_8 = 32'b00000000000100000000000000000000
    DFT_CTRL_BUS_9 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_10 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_11 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_12 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_13 = 32'b00000000000000000000000000000000
    MEM_SPACE_AW = 32'b00000000000000000000000000011100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 306)] Elaborating instance free_clk_ibufg
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 514)] Elaborating instance u_manu_clear_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/u_manu_clear_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 525)] Elaborating instance u_free_clk_rst_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/u_free_clk_rst_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 552)] Elaborating instance u_ips2l_uart_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_top_32bit.v(line number: 15)] Elaborating module ips2l_uart_ctrl_top_32bit
I: Module instance {test_ddr/u_ips2l_uart_ctrl} parameter value:
    CLK_DIV_P = 16'b0000000001001000
    FIFO_D = 32'b00000000000000000000000000010000
    WORD_LEN = 2'b11
    PARITY_EN = 1'b0
    PARITY_TYPE = 1'b0
    STOP_LEN = 1'b0
    MODE = 1'b0
    DFT_CTRL_BUS_0 = 32'b00000000000000000001000000000001
    DFT_CTRL_BUS_1 = 32'b00000000000000000000000000000001
    DFT_CTRL_BUS_2 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_3 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_4 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_5 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_6 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_7 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_8 = 32'b00000000000100000000000000000000
    DFT_CTRL_BUS_9 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_10 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_11 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_12 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_13 = 32'b00000000000000000000000000000000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_top_32bit.v(line number: 107)] Elaborating instance u_uart_top
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_rs232_intf.v(line number: 15)] Elaborating module ips2l_seu_rs232_intf
I: Module instance {test_ddr/u_ips2l_uart_ctrl/u_uart_top} parameter value:
    CLK_DIV_P = 16'b0000000001001000
    FIFO_D = 32'b00000000000000000000000000010000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_rs232_intf.v(line number: 74)] Elaborating instance u_ips2l_clk_gen
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_clk_gen_32bit.v(line number: 15)] Elaborating module ips2l_clk_gen_32bit
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_rs232_intf.v(line number: 82)] Elaborating instance u_ips2l_seu_uart_tx
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_tx.v(line number: 15)] Elaborating module ips2l_seu_uart_tx
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_rs232_intf.v(line number: 94)] Elaborating instance u_ips2l_seu_uart_rx
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_seu_uart_rx.v(line number: 15)] Elaborating module ips2l_seu_uart_rx
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_top_32bit.v(line number: 140)] Elaborating instance u_uart_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_32bit.v(line number: 15)] Elaborating module ips2l_uart_ctrl_32bit
I: Module instance {test_ddr/u_ips2l_uart_ctrl/u_uart_ctrl} parameter value:
    CLK_DIV_P = 16'b0000000001001000
    DFT_CTRL_BUS_0 = 32'b00000000000000000001000000000001
    DFT_CTRL_BUS_1 = 32'b00000000000000000000000000000001
    DFT_CTRL_BUS_2 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_3 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_4 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_5 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_6 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_7 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_8 = 32'b00000000000100000000000000000000
    DFT_CTRL_BUS_9 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_10 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_11 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_12 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_13 = 32'b00000000000000000000000000000000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_32bit.v(line number: 83)] Elaborating instance u_cmd_parser
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_cmd_parser_32bit.v(line number: 15)] Elaborating module ips2l_cmd_parser_32bit
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_uart_ctrl_32bit.v(line number: 113)] Elaborating instance u_ver_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_ctrl_32bit/ips2l_ver_ctrl_32bit.v(line number: 15)] Elaborating module ips2l_ver_ctrl_32bit
I: Module instance {test_ddr/u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl} parameter value:
    DFT_CTRL_BUS_0 = 32'b00000000000000000001000000000001
    DFT_CTRL_BUS_1 = 32'b00000000000000000000000000000001
    DFT_CTRL_BUS_2 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_3 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_4 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_5 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_6 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_7 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_8 = 32'b00000000000100000000000000000000
    DFT_CTRL_BUS_9 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_10 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_11 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_12 = 32'b00000000000000000000000000000000
    DFT_CTRL_BUS_13 = 32'b00000000000000000000000000000000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 581)] Elaborating instance u_uart_rd_lock
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/uart_rd_lock.v(line number: 2)] Elaborating module uart_rd_lock
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 705)] Elaborating instance u_core_clk_rst_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/u_core_clk_rst_sync} parameter value:
    DATA_WIDTH = 1'b1
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 746)] Elaborating instance I_ips_ddr_top
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3.v(line number: 12)] Elaborating module ddr3
I: Module instance {test_ddr/I_ips_ddr_top} parameter value:
    MEM_ROW_WIDTH = 32'b00000000000000000000000000001111
    MEM_COLUMN_WIDTH = 32'b00000000000000000000000000001010
    MEM_BANK_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DM_WIDTH = 32'b00000000000000000000000000000010
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3.v(line number: 288)] Elaborating instance u_ddrc_rstn_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrc_rstn_sync} parameter value:
    DATA_WIDTH = 1'b1
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3.v(line number: 323)] Elaborating instance u_ips_ddrc_top
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 619)] Elaborating module ips2l_mcdq_wrapper_v1_2b
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top} parameter value:
    DDR_TYPE = 2'b00
    MEM_ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    MEM_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ADDR_MAPPING_SEL = 32'b00000000000000000000000000000001
    TOTAL_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MR0_DDR3 = 16'b0001100100100000
    MR1_DDR3 = 16'b0000000000010100
    MR2_DDR3 = 16'b0000000000000000
    MR3_DDR3 = 16'b0000000000000000
    MR_DDR2 = 16'b0000000000000000
    EMR1_DDR2 = 16'b0000000000000000
    EMR2_DDR2 = 16'b0000000000000000
    EMR3_DDR2 = 16'b0000000000000000
    MR_LPDDR = 16'b0000000000000000
    EMR_LPDDR = 16'b0000000000000000
    TXSDLL = 32'b00000000000000000000001000000000
    TCCD = 32'b00000000000000000000000000000100
    TXP = 32'b00000000000000000000000000000100
    TFAW = 32'b00000000000000000000000000010111
    TRAS = 32'b00000000000000000000000000010011
    TRCD = 32'b00000000000000000000000000001000
    TREFI = 32'b00000000000000000000111111111111
    TRFC = 32'b00000000000000000000000010001001
    TRC = 32'b00000000000000000000000000011011
    TRP = 32'b00000000000000000000000000001000
    TRRD = 32'b00000000000000000000000000000110
    TRTP = 32'b00000000000000000000000000000100
    TWR = 32'b00000000000000000000000000001000
    TWTR = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 867)] Elaborating instance mcdq_ui_axi
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp(line number: 271)] Elaborating module ips2l_mcdq_ui_axi_v1_2a
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi} parameter value:
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    MEM_ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    ADDR_MAPPING_SEL = 32'b00000000000000000000000000000001
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp(line number: 427)] Elaborating instance mcdq_reg_fifo2
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp(line number: 78)] Elaborating module ips2l_mcdq_reg_fifo2_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2} parameter value:
    W = 32'b00000000000000000000000000100110
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_ui_axi_v1_2a.vp(line number: 543)] Elaborating instance u_user_cmd_fifo
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_reg_fifo2_v1_2.vp(line number: 78)] Elaborating module ips2l_mcdq_reg_fifo2_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo} parameter value:
    W = 32'b00000000000000000000000000110111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 902)] Elaborating instance mcdq_wdatapath
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp(line number: 171)] Elaborating module ips2l_mcdq_wdatapath_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath} parameter value:
    DDR_TYPE = 2'b00
    DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp(line number: 239)] Elaborating instance ips_distributed_fifo
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000000010
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 192)] Elaborating instance u_ips2l_distributed_fifo_distributed_fifo_v1_0
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000000010
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 173)] Elaborating instance ips2l_distributed_sdpram_distributed_fifo_v1_0
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 120)] Elaborating module ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000000010
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    INIT_FILE = NONE
    FILE_FORMAT = BIN
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 193)] Elaborating instance u_ips2l_distributed_fifo_ctr
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp(line number: 269)] Elaborating module ips2l_distributed_fifo_ctr_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr} parameter value:
    DEPTH = 32'b00000000000000000000000000000100
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp(line number: 278)] Elaborating instance mc3q_wdp_dcp
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_dcp_v1_2.vp(line number: 133)] Elaborating module ips2l_mcdq_wdp_dcp_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdatapath_v1_2.vp(line number: 313)] Elaborating instance mcdq_wdp_align
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wdp_align_v1_2.vp(line number: 140)] Elaborating module ips2l_mcdq_wdp_align_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align} parameter value:
    DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 929)] Elaborating instance mcdq_rdatapath
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp(line number: 83)] Elaborating module ips2l_mcdq_rdatapath_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_rdatapath} parameter value:
    DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_rdatapath_v1_2.vp(line number: 114)] Elaborating instance mcdq_prefetch_fifo
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp(line number: 95)] Elaborating module ips2l_mcdq_prefetch_fifo_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo} parameter value:
    D = 32'b00000000000000000000000000100000
    W = 32'b00000000000000000000000000000101
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_prefetch_fifo_v1_2.vp(line number: 165)] Elaborating instance ips2l_distributed_fifo
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000101
    DATA_WIDTH = 32'b00000000000000000000000000000101
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 192)] Elaborating instance u_ips2l_distributed_fifo_distributed_fifo_v1_0
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000101
    DATA_WIDTH = 32'b00000000000000000000000000000101
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 173)] Elaborating instance ips2l_distributed_sdpram_distributed_fifo_v1_0
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 120)] Elaborating module ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000101
    DATA_WIDTH = 32'b00000000000000000000000000000101
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    INIT_FILE = NONE
    FILE_FORMAT = BIN
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 193)] Elaborating instance u_ips2l_distributed_fifo_ctr
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp(line number: 269)] Elaborating module ips2l_distributed_fifo_ctr_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr} parameter value:
    DEPTH = 32'b00000000000000000000000000000101
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000000100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 957)] Elaborating instance mcdq_dcd_top
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp(line number: 174)] Elaborating module ips2l_mcdq_dcd_top_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top} parameter value:
    SINGLE_RANK = true
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    RADDR_WIDTH = 32'b00000000000000000000000000000001
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    BURST_LENGTH = 32'b00000000000000000000000000001000
    TREFI = 32'b00000000000000000000001111111111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp(line number: 238)] Elaborating instance mcdq_dcd_bm
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp(line number: 243)] Elaborating module ips2l_mcdq_dcd_bm_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm} parameter value:
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    TOTAL_BANK_WIDTH = 32'b00000000000000000000000000000011
    TREFI = 32'b00000000000000000000001111111111
    REF_NUM = 32'b00000000000000000000000000001000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_bm_v1_2.vp(line number: 374)] Elaborating instance mcdq_dcd_rowaddr
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_rowaddr_v1_2.vp(line number: 76)] Elaborating module ips2l_mcdq_dcd_rowaddr_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr} parameter value:
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    TOTAL_BANK_WIDTH = 32'b00000000000000000000000000000011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_top_v1_2.vp(line number: 282)] Elaborating instance mcdq_dcd_sm
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcd_sm_v1_2.vp(line number: 209)] Elaborating module ips2l_mcdq_dcd_sm_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm} parameter value:
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    BURST_LENGTH = 32'b00000000000000000000000000001000
    REF_NUM = 32'b00000000000000000000000000001000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1006)] Elaborating instance mcdq_dcp_top
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp(line number: 329)] Elaborating module ips2l_mcdq_dcp_top_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top} parameter value:
    SINGLE_RANK = true
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    RADDR_WIDTH = 32'b00000000000000000000000000000001
    TZQCS = 32'b00000000000000000000000001001011
    TRP = 32'b00000000000000000000000000001000
    TFAW = 32'b00000000000000000000000000010111
    TRAS = 32'b00000000000000000000000000010011
    TRCD = 32'b00000000000000000000000000001000
    TRFC = 32'b00000000000000000000000010001001
    TRRD = 32'b00000000000000000000000000000110
    TRC = 32'b00000000000000000000000000011011
    TCCD = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp(line number: 434)] Elaborating instance mcdq_dcp_buf
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp(line number: 298)] Elaborating module ips2l_mcdq_dcp_buf_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf} parameter value:
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    FIFO_DATA_WIDTH = 32'b00000000000000000000000000101011
    TRFC = 32'b00000000000000000000000010001001
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp(line number: 408)] Elaborating instance A_ips2l_distributed_fifo
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ips2l_distributed_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000101011
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000001100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 192)] Elaborating instance u_ips2l_distributed_fifo_distributed_fifo_v1_0
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000101011
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000001100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 173)] Elaborating instance ips2l_distributed_sdpram_distributed_fifo_v1_0
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 120)] Elaborating module ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/ips2l_distributed_sdpram_distributed_fifo_v1_0} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000101011
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    INIT_FILE = NONE
    FILE_FORMAT = BIN
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp(line number: 193)] Elaborating instance u_ips2l_distributed_fifo_ctr
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_fifo_ctr_v1_0.vp(line number: 269)] Elaborating module ips2l_distributed_fifo_ctr_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr} parameter value:
    DEPTH = 32'b00000000000000000000000000000100
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000001100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp(line number: 459)] Elaborating instance B_ips2l_distributed_fifo
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/ips2l_distributed_fifo_v1_0.vp(line number: 130)] Elaborating module ips2l_distributed_fifo_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000000100
    DATA_WIDTH = 32'b00000000000000000000000000101011
    RST_TYPE = ASYNC
    OUT_REG = 32'b00000000000000000000000000000000
    FIFO_TYPE = SYNC_FIFO
    ALMOST_FULL_NUM = 32'b00000000000000000000000000001100
    ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp(line number: 498)] Elaborating instance mcdq_dcp_back_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 643)] Elaborating module ips2l_mcdq_dcp_back_ctrl_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl} parameter value:
    SINGLE_RANK = true
    FIFO_DATA_WIDTH = 32'b00000000000000000000000000101011
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    RADDR_WIDTH = 32'b00000000000000000000000000000001
    TZQCS = 32'b00000000000000000000000001001011
    TRP = 32'b00000000000000000000000000001000
    TFAW = 32'b00000000000000000000000000010111
    TRAS = 32'b00000000000000000000000000010011
    TRCD = 32'b00000000000000000000000000001000
    TRFC = 32'b00000000000000000000000010001001
    TRRD = 32'b00000000000000000000000000000110
    TRC = 32'b00000000000000000000000000011011
    TCCD = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1038)] Elaborating instance timing_act2wr_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act2wr_pass_v1_2.vp(line number: 115)] Elaborating module ips2l_mcdq_timing_act2wr_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act2wr_pass} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1052)] Elaborating instance mcdq_timing_rd_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_rd_pass_v1_2.vp(line number: 128)] Elaborating module ips2l_mcdq_timing_rd_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000011
    CNT1_WIDTH = 32'b00000000000000000000000000000111
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1048)] Width mismatch between port cnt_init0 and signal bound to it for instantiated module ips2l_mcdq_timing_rd_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1071)] Elaborating instance timing_wr_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_wr_pass_v1_2.vp(line number: 127)] Elaborating module ips2l_mcdq_timing_wr_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000011
    CNT1_WIDTH = 32'b00000000000000000000000000000110
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1067)] Width mismatch between port cnt_init0 and signal bound to it for instantiated module ips2l_mcdq_timing_wr_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1133)] Elaborating instance timing_pre_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1128)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1158)] Elaborating instance timing_prea_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_pre_pass_v1_2.vp(line number: 148)] Elaborating module ips2l_mcdq_timing_pre_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass} parameter value:
    CNT0_WIDTH = 32'b00000000000000000000000000000110
    CNT1_WIDTH = 32'b00000000000000000000000000000111
    CNT2_WIDTH = 32'b00000000000000000000000000000101
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1153)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_pre_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1178)] Elaborating instance timing_ref_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_ref_pass_v1_2.vp(line number: 90)] Elaborating module ips2l_mcdq_timing_ref_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000001000
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1175)] Width mismatch between port cnt_init0 and signal bound to it for instantiated module ips2l_mcdq_timing_ref_pass_v1_2
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1175)] Width mismatch between port cnt_init1 and signal bound to it for instantiated module ips2l_mcdq_timing_ref_pass_v1_2
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1175)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_ref_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000011011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000011011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000011011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000011011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000011011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000011011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000011011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1211)] Elaborating instance trc_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_trc_timing_v1_2.vp(line number: 149)] Elaborating module ips2l_mcdq_trc_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TDELAY = 32'b00000000000000000000000000011011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1245)] Elaborating instance tfaw_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp(line number: 128)] Elaborating module ips2l_mcdq_tfaw_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000101
    TFAW = 32'b00000000000000000000000000010111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp(line number: 168)] Elaborating instance mcdq_tfaw
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp(line number: 68)] Elaborating module ips2l_mcdq_tfaw_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw} parameter value:
    TFAW = 32'b00000000000000000000000000010111
    CNT_WIDTH = 32'b00000000000000000000000000000101
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp(line number: 168)] Elaborating instance mcdq_tfaw
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp(line number: 68)] Elaborating module ips2l_mcdq_tfaw_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw} parameter value:
    TFAW = 32'b00000000000000000000000000010111
    CNT_WIDTH = 32'b00000000000000000000000000000101
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_timing_v1_2.vp(line number: 168)] Elaborating instance mcdq_tfaw
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_tfaw_v1_2.vp(line number: 68)] Elaborating module ips2l_mcdq_tfaw_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw} parameter value:
    TFAW = 32'b00000000000000000000000000010111
    CNT_WIDTH = 32'b00000000000000000000000000000101
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1278)] Elaborating instance twra2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1313)] Elaborating instance trda2act_timing
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_com_timing_v1_2.vp(line number: 102)] Elaborating module ips2l_mcdq_com_timing_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000000110
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1330)] Elaborating instance timing_act_pass
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/syn_mod/ips2l_mcdq_timing_act_pass_v1_2.vp(line number: 92)] Elaborating module ips2l_mcdq_timing_act_pass_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass} parameter value:
    CNT_WIDTH = 32'b00000000000000000000000000001000
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1327)] Width mismatch between port cnt_init0 and signal bound to it for instantiated module ips2l_mcdq_timing_act_pass_v1_2
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1327)] Width mismatch between port cnt_init1 and signal bound to it for instantiated module ips2l_mcdq_timing_act_pass_v1_2
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_back_ctrl_v1_2.vp(line number: 1327)] Width mismatch between port cnt_init2 and signal bound to it for instantiated module ips2l_mcdq_timing_act_pass_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_top_v1_2.vp(line number: 535)] Elaborating instance mcdq_dcp_out
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_out_v1_2.vp(line number: 210)] Elaborating module ips2l_mcdq_dcp_out_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out} parameter value:
    SINGLE_RANK = true
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    COL_ADDR_WIDTH = 32'b00000000000000000000000000001010
    BADDR_WIDTH = 32'b00000000000000000000000000000011
    RADDR_WIDTH = 32'b00000000000000000000000000000001
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1057)] Elaborating instance mcdq_calib_delay
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_calib_delay_v1_2.vp(line number: 101)] Elaborating module ips2l_mcdq_calib_delay_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_calib_delay} parameter value:
    ADDR_WIDTH = 32'b00000000000000000000000000001111
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1085)] Elaborating instance mcdq_dfi
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp(line number: 432)] Elaborating module ips2l_mcdq_dfi_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_dfi} parameter value:
    BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    TOTAL_ADDR_WIDTH = 32'b00000000000000000000000000001111
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
W: Verilog-2039: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp(line number: 553)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2039: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp(line number: 617)] Repeat multiplier in concatenation evaluates to 0
W: Verilog-2039: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dfi_v1_2.vp(line number: 729)] Repeat multiplier in concatenation evaluates to 0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1123)] Elaborating instance mcdq_apb_cross_v1_2
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_apb_cross_v1_2.vp(line number: 145)] Elaborating module ips2l_mcdq_apb_cross_v1_2
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1158)] Elaborating instance mcdq_cfg_apb
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_cfg_apb_v1_2.vp(line number: 559)] Elaborating module ips2l_mcdq_cfg_apb_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_cfg_apb} parameter value:
    DDR_TYPE = 2'b00
    MR0_DDR3 = 16'b0001100100100000
    MR1_DDR3 = 16'b0000000000010100
    MR2_DDR3 = 16'b0000000000000000
    MR3_DDR3 = 16'b0000000000000000
    MR_DDR2 = 16'b0000000000000000
    EMR1_DDR2 = 16'b0000000000000000
    EMR2_DDR2 = 16'b0000000000000000
    EMR3_DDR2 = 16'b0000000000000000
    MR_LPDDR = 16'b0000000000000000
    EMR_LPDDR = 16'b0000000000000000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1207)] Elaborating instance mcdq_mrs
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_mrs_v1_2.vp(line number: 321)] Elaborating module ips2l_mcdq_mrs_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_mrs} parameter value:
    DDR_TYPE = 2'b00
    TOTAL_BA_ADDR_WIDTH = 32'b00000000000000000000000000000011
    TRFC = 32'b00000000000000000000000010001001
    TRP = 32'b00000000000000000000000000001000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_wrapper_v1_2b.vp(line number: 1233)] Elaborating instance mcdq_lp
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_lp_v1_2.vp(line number: 315)] Elaborating module ips2l_mcdq_lp_v1_2
I: Module instance {test_ddr/I_ips_ddr_top/u_ips_ddrc_top/mcdq_lp} parameter value:
    ROW_ADDR_WIDTH = 32'b00000000000000000000000000001111
    TRFC = 32'b00000000000000000000000010001001
    TREFI = 32'b00000000000000000000001111111111
    TRP = 32'b00000000000000000000000000001000
    TXSDLL = 32'b00000000000000000000000010000000
    TXP = 32'b00000000000000000000000000000100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3.v(line number: 397)] Elaborating instance u_ddrphy_top
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 12)] Elaborating module ddr3_ddrphy_top
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top} parameter value:
    MEM_TYPE = DDR3
    TMRD = 8'b00000001
    TMOD = 8'b00000011
    TXPR = 8'b00100100
    TRP = 8'b00000010
    TRFC = 8'b00100011
    TRCD = 8'b00000010
    MEM_ROW_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANK_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DM_WIDTH = 32'b00000000000000000000000000000010
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 422)] Elaborating instance u_clkbufm
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 432)] Elaborating instance u_ips2l_ddrphy_rst_clk_phase_adj
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp(line number: 104)] Elaborating module ips2l_ddrphy_rst_clk_phase_adj_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj} parameter value:
    PHASE_ADJ_DIR = 32'b00000000000000000000000000000000
    PHASE_ADJ_STEP = 32'b00000000000000000000000000001000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 455)] Elaborating instance rst_clk_gpll
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 127)] Elaborating module ips2l_ddrphy_gpll_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll} parameter value:
    CLKIN_FREQ = 25.000000
    BANDWIDTH = OPTIMIZED
    IDIV = 32'b00000000000000000000000000000001
    FDIV = 42.000000
    DUTYF = 32'b00000000000000000000000000101010
    ODIV0 = 42.000000
    ODIV1 = 32'b00000000000000000000000001010100
    DUTY0 = 32'b00000000000000000000000000101010
    STATIC_PHASE0 = 32'b00000000000000000000000000000000
    INTERNAL_FB = CLKOUTF
    ODIV2 = 32'b00000000000000000000000000000100
    ODIV3 = 32'b00000000000000000000000000001000
    ODIV4 = 32'b00000000000000000000000000010000
    ODIV5 = 32'b00000000000000000000000000100000
    ODIV6 = 32'b00000000000000000000000001000000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 221)] Elaborating instance u_gpll
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 470)] Elaborating instance u_rst_clk_bufg
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 479)] Elaborating instance u_ddrphy_rst_seq_rstn_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 497)] Elaborating instance ddrphy_gpll
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 127)] Elaborating module ips2l_ddrphy_gpll_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll} parameter value:
    CLKIN_FREQ = 25.000000
    BANDWIDTH = OPTIMIZED
    IDIV = 32'b00000000000000000000000000000001
    FDIV = 42.000000
    DUTYF = 32'b00000000000000000000000000101010
    ODIV0 = 8.000000
    ODIV1 = 32'b00000000000000000000000000010000
    DUTY0 = 32'b00000000000000000000000000001000
    STATIC_PHASE0 = 32'b00000000000000000000000000000000
    INTERNAL_FB = CLKOUTF
    ODIV2 = 32'b00000000000000000000000000000100
    ODIV3 = 32'b00000000000000000000000000001000
    ODIV4 = 32'b00000000000000000000000000010000
    ODIV5 = 32'b00000000000000000000000000100000
    ODIV6 = 32'b00000000000000000000000001000000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_gpll_v1_3.vp(line number: 221)] Elaborating instance u_gpll
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 512)] Elaborating instance u_ddrphy_gpll_phase
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gpll_phase_v1_0.vp(line number: 69)] Elaborating module ips2l_ddrphy_gpll_phase_v1_0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 521)] Elaborating instance u_sysclk_bufg
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 528)] Elaborating instance u_ddrphy_cpd
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 541)] Elaborating instance u_ddrphy_cpd_rstn_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd_rstn_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 548)] Elaborating instance u_ips2l_ddrphy_cpd_lock
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_lock_v1_0.vp(line number: 71)] Elaborating module ips2l_ddrphy_cpd_lock_v1_0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 556)] Elaborating instance ddrphy_cpd_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_cpd_ctrl_v1_3.vp(line number: 182)] Elaborating module ips2l_ddrphy_cpd_ctrl_v1_3
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 576)] Elaborating instance ddrphy_reset_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 268)] Elaborating module ips2l_ddrphy_reset_ctrl_v1_3
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 412)] Elaborating instance ddrphy_pll_lock_debounce
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_debounce_v1_0.vp(line number: 84)] Elaborating module ips2l_ddrphy_rst_debounce_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce} parameter value:
    RISE_CNTR_WIDTH = 32'b00000000000000000000000000010011
    RISE_CNTR_VALUE = 19'b1000000000000000000
    ACTIVE_HIGH = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 620)] Elaborating instance u_ddrphy_rstn_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_reset_ctrl_v1_3.vp(line number: 630)] Elaborating instance u_dll_rst_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 609)] Elaborating instance ddrphy_dll_update_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dll_update_ctrl_v1_3.vp(line number: 124)] Elaborating module ips2l_ddrphy_dll_update_ctrl_v1_3
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 626)] Elaborating instance u_dll_update_n_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/u_dll_update_n_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b1
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 636)] Elaborating instance u_dll_freeze_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/u_dll_freeze_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 646)] Elaborating instance ddrphy_gate_update_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp(line number: 100)] Elaborating module ips2l_ddrphy_gate_update_ctrl_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl} parameter value:
    UPDATE_EN = 1'b0
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp(line number: 182)] Elaborating instance ddrphy_drift_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp(line number: 112)] Elaborating module ips2l_ddrphy_drift_ctrl_v1_0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp(line number: 182)] Elaborating instance ddrphy_drift_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_drift_ctrl_v1_0.vp(line number: 112)] Elaborating module ips2l_ddrphy_drift_ctrl_v1_0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 681)] Elaborating instance ddrphy_calib_top
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 392)] Elaborating module ips2l_ddrphy_calib_top_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top} parameter value:
    DDR_TYPE = 2'b00
    WRCAL_EN = 1'b0
    EYECAL_EN = 32'b00000000000000000000000000000001
    T200US = 20'b00000110101110101010
    T500US = 20'b00010000010101111001
    T400NS = 8'b00110101
    TMRD = 8'b00000001
    TMOD = 8'b00000011
    TXPR = 8'b00100100
    TRP = 8'b00000010
    TZQINIT = 10'b0010000000
    TRFC = 8'b00100011
    TRCD = 8'b00000010
    REF_CNT = 4'b1001
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DM_WIDTH = 32'b00000000000000000000000000000010
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 597)] Elaborating instance ddrphy_main_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_main_ctrl_v1_10.vp(line number: 196)] Elaborating module ips2l_ddrphy_main_ctrl_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl} parameter value:
    DDR_TYPE = 2'b00
    EYECAL_EN = 32'b00000000000000000000000000000001
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 641)] Elaborating instance ddrphy_init
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_init_v1_0.vp(line number: 577)] Elaborating module ips2l_ddrphy_init_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init} parameter value:
    DDR_TYPE = 2'b00
    T200US = 20'b00000110101110101010
    T500US = 20'b00010000010101111001
    T400NS = 8'b00110101
    TMRD = 8'b00000001
    TMOD = 8'b00000011
    TXPR = 8'b00100100
    TRP = 8'b00000010
    TRFC = 8'b00100011
    TZQINIT = 10'b0010000000
    REF_CNT = 4'b1001
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 669)] Elaborating instance ddrphy_wrlvl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrlvl_v1_0.vp(line number: 183)] Elaborating module ips2l_ddrphy_wrlvl_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl} parameter value:
    TMOD = 8'b00000011
    TRFC = 8'b00100011
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 698)] Elaborating instance ddrphy_rdcal
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rdcal_v1_10.vp(line number: 750)] Elaborating module ips2l_ddrphy_rdcal_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal} parameter value:
    DDR_TYPE = 2'b00
    TRFC = 8'b00100011
    TRCD = 8'b00000010
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 756)] Elaborating instance ddrphy_wrcal
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 495)] Elaborating module ips2l_ddrphy_wrcal_v1_7
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal} parameter value:
    WRCAL_EN = 1'b0
    TRFC = 8'b00100011
    TRCD = 8'b00000010
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 787)] Elaborating instance ddrphy_eyecal
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp(line number: 228)] Elaborating module ips2l_ddrphy_eyecal_v1_5
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal} parameter value:
    TRFC = 8'b00100011
    TRCD = 8'b00000010
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 815)] Elaborating instance ddrphy_calib_mux
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_mux_v1_0.vp(line number: 199)] Elaborating module ips2l_ddrphy_calib_mux_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_calib_mux} parameter value:
    DDR_TYPE = 2'b00
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_calib_top_v1_10.vp(line number: 883)] Elaborating instance ddrphy_upcal
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_upcal_v1_0.vp(line number: 151)] Elaborating module ips2l_ddrphy_upcal_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal} parameter value:
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 753)] Elaborating instance ddrphy_training_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_training_ctrl_v1_0.vp(line number: 83)] Elaborating module ips2l_ddrphy_training_ctrl_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_training_ctrl} parameter value:
    SRB_DQS_RST_TRAINING_HIGH_CLK = 32'b00000000000000000000000000000011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 765)] Elaborating instance u_force_read_clk_ctrl_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/u_force_read_clk_ctrl_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 775)] Elaborating instance u_force_samp_position_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/u_force_samp_position_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 785)] Elaborating instance u_samp_position_dyn_adj_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/u_samp_position_dyn_adj_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 795)] Elaborating instance u_wrcal_position_dyn_adj_sync
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ips2l_rst_sync_v1_3.vp(line number: 59)] Elaborating module ips2l_rst_sync_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/u_wrcal_position_dyn_adj_sync} parameter value:
    DATA_WIDTH = 32'b00000000000000000000000000000001
    DFT_VALUE = 1'b0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 821)] Elaborating instance ddrphy_slice_top
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 12)] Elaborating module ddr3_slice_top_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top} parameter value:
    CLKIN_FREQ = 25.000000
    PPLL_BANDWIDTH = LOW
    DDR_TYPE = 2'b00
    GATE_MODE = 1'b1
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
    SC_LDO_CTRL = 2'b00
    SC_DLY_2X = 1'b1
    PPLL_IDIV = 32'b00000000000000000000000000000001
    PPLL_FDIV = 32'b00000000000000000000000001010100
    PPLL_ODIVPHY = 32'b00000000000000000000000000000010
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
    MEM_DM_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 580)] Elaborating instance u_clkbufr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 597)] Elaborating instance ddrphy_ppll
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 242)] Elaborating module ips2l_ddrphy_ppll_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll} parameter value:
    CLKIN_FREQ = 25.000000
    BANDWIDTH = LOW
    CLKOUT4_SYN_EN = TRUE
    INTERNAL_FB = CLKOUT4
    IDIV = 32'b00000000000000000000000000000001
    FDIV = 32'b00000000000000000000000001010100
    ODIVPHY = 32'b00000000000000000000000000000010
    ODIV0 = 32'b00000000000000000000000000010000
    ODIV1 = 32'b00000000000000000000000000000010
    ODIV2 = 32'b00000000000000000000000000000100
    ODIV3 = 32'b00000000000000000000000000001000
    ODIV4 = 32'b00000000000000000000000001010100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 310)] Elaborating instance u_ppll
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 612)] Elaborating instance u_ddrphy_ioclkdiv
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 580)] Elaborating instance u_clkbufr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 597)] Elaborating instance ddrphy_ppll
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/pll/ips2l_ddrphy_ppll_v1_0.vp(line number: 242)] Elaborating module ips2l_ddrphy_ppll_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll} parameter value:
    CLKIN_FREQ = 25.000000
    BANDWIDTH = LOW
    CLKOUT4_SYN_EN = TRUE
    INTERNAL_FB = CLKOUT4
    IDIV = 32'b00000000000000000000000000000001
    FDIV = 32'b00000000000000000000000001010100
    ODIVPHY = 32'b00000000000000000000000000000010
    ODIV0 = 32'b00000000000000000000000000010000
    ODIV1 = 32'b00000000000000000000000000000010
    ODIV2 = 32'b00000000000000000000000000000100
    ODIV3 = 32'b00000000000000000000000000001000
    ODIV4 = 32'b00000000000000000000000001010100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 612)] Elaborating instance u_ddrphy_ioclkdiv
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 635)] Elaborating instance ddrphy_data_slice
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 583)] Elaborating module ips2l_ddrphy_data_slice_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice} parameter value:
    DDR_TYPE = 2'b00
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
    GATE_MODE = 1'b1
    SC_LDO_CTRL = 2'b00
    SC_DLY_2X = 1'b1
    WL_MAX_STEP = 8'b11001001
    WL_MAX_CHECK = 5'b11111
    MIN_DQSI_WIN = 9'b000001010
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 810)] Elaborating instance ddrphy_data_slice_wrlvl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrlvl_v1_10.vp(line number: 292)] Elaborating module ips2l_ddrphy_data_slice_wrlvl_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl} parameter value:
    WL_MAX_STEP = 8'b11001001
    CK_MAX_STEP = 8'b10000000
    WL_MAX_CHECK = 5'b11111
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 841)] Elaborating instance ddrphy_data_slice_wrcal
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 278)] Elaborating module ips2l_ddrphy_data_slice_wrcal_v1_10
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 868)] Elaborating instance ddrphy_data_slice_dqs_gate_cal
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp(line number: 111)] Elaborating module ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal} parameter value:
    GATE_MODE = 1'b1
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp(line number: 148)] Elaborating instance ddrphy_dqs_gate_coarse_cal
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp(line number: 173)] Elaborating module ips2l_ddrphy_dqs_gate_coarse_cal_v1_0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp(line number: 164)] Elaborating instance ddrphy_gatecal
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gatecal_v1_10.vp(line number: 243)] Elaborating module ips2l_ddrphy_gatecal_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal} parameter value:
    GATE_MODE = 1'b1
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 905)] Elaborating instance ddrphy_dqsi_rdel_cal
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp(line number: 395)] Elaborating module ips2l_ddrphy_dqsi_rdel_cal_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal} parameter value:
    MIN_DQSI_WIN = 9'b000001010
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 947)] Elaborating instance ddrphy_dqs_rddata_align
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dqs_rddata_align_v1_10.vp(line number: 527)] Elaborating module ips2l_ddrphy_dqs_rddata_align_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align} parameter value:
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 983)] Elaborating instance ddrphy_wdata_path_adj
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wdata_path_adj_v1_10.vp(line number: 232)] Elaborating module ips2l_ddrphy_wdata_path_adj_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj} parameter value:
    DQ_WIDTH = 32'b00000000000000000000000000001000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1012)] Elaborating instance u_ddc_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1052)] Elaborating instance u_dll_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1084)] Elaborating instance u_tserdes0_dqs
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1126)] Elaborating instance u_tserdes1_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1168)] Elaborating instance u_oserdes_dqs
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1200)] Elaborating instance u_iobufco_dqs
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1238)] Elaborating instance u_oserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1283)] Elaborating instance u_iserdes_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1304)] Elaborating instance u_iobuf_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1336)] Elaborating instance u_oserdes_dm
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1357)] Elaborating instance u_outbuft_dm
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[0].u_iodelay_dq
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[1].u_iodelay_dq
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[2].u_iodelay_dq
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[3].u_iodelay_dq
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[4].u_iodelay_dq
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[5].u_iodelay_dq
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[6].u_iodelay_dq
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 1262)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice.dq_loop[7].u_iodelay_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 635)] Elaborating instance ddrphy_data_slice
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_v1_10.vp(line number: 583)] Elaborating module ips2l_ddrphy_data_slice_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice} parameter value:
    DDR_TYPE = 2'b00
    TEST_DATA_PATTERN0 = 64'b0101010110101010010101011010101000001000111101110000100011110111
    TEST_DATA_PATTERN1 = 64'b0111111110011111011111111001111110000000111111101000000011111110
    TEST_DATA_PATTERN2 = 64'b1111000000001111111100000000111100000001111111110000000111111111
    TEST_DATA_PATTERN3 = 64'b1101111110101010110111111010101001010101101010100101010110101010
    GATE_MODE = 1'b1
    SC_LDO_CTRL = 2'b00
    SC_DLY_2X = 1'b1
    WL_MAX_STEP = 8'b11001001
    WL_MAX_CHECK = 5'b11111
    MIN_DQSI_WIN = 9'b000001010
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 746)] Elaborating instance ddrphy_slice_rddata_align
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_slice_rddata_align_v1_0.vp(line number: 108)] Elaborating module ips2l_ddrphy_slice_rddata_align_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_slice_rddata_align} parameter value:
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 763)] Elaborating instance ddrphy_control_path_adj
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_control_path_adj_v1_10.vp(line number: 134)] Elaborating module ips2l_ddrphy_control_path_adj_v1_10
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj} parameter value:
    DDR_TYPE = 2'b00
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    SLIP_BIT_NUM = 2'b01
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 801)] Elaborating instance u_ddc_ca
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 853)] Elaborating instance u_tserdes_ca0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 895)] Elaborating instance u_tserdes_ca1
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 801)] Elaborating instance u_ddc_ca
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 853)] Elaborating instance u_tserdes_ca0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 895)] Elaborating instance u_tserdes_ca1
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 801)] Elaborating instance u_ddc_ca
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 853)] Elaborating instance u_tserdes_ca0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 895)] Elaborating instance u_tserdes_ca1
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 940)] Elaborating instance u_oserdes_ck
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 975)] Elaborating instance u_iodelay_dq
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 982)] Elaborating instance u_outbuftco_ck
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1012)] Elaborating instance u_oserdes_odt
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1036)] Elaborating instance u_odelay_odt
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1043)] Elaborating instance u_outbuft_odt
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1071)] Elaborating instance u_oserdes_csn
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1095)] Elaborating instance u_odelay_csn
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1102)] Elaborating instance u_outbuft_csn
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1130)] Elaborating instance u_oserdes_rasn
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1154)] Elaborating instance u_odelay_rasn
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1161)] Elaborating instance u_outbuft_rasn
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1190)] Elaborating instance u_oserdes_casn
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1214)] Elaborating instance u_odelay_casn
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1221)] Elaborating instance u_outbuft_casn
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1249)] Elaborating instance u_oserdes_wen
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1273)] Elaborating instance u_odelay_wen
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1280)] Elaborating instance u_outbuft_wen
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1309)] Elaborating instance u_oserdes_cke
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1333)] Elaborating instance u_odelay_cke
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1340)] Elaborating instance u_outbuft_cke
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1375)] Elaborating instance u_oserdes_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Elaborating instance u_odelay_addr
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1406)] Elaborating instance u_outbuft_addr0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1440)] Elaborating instance u_oserdes_ba
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Elaborating instance u_odelay_ba
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1471)] Elaborating instance u_outbuft_ba
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1440)] Elaborating instance u_oserdes_ba
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Elaborating instance u_odelay_ba
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1471)] Elaborating instance u_outbuft_ba
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1440)] Elaborating instance u_oserdes_ba
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Elaborating instance u_odelay_ba
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1471)] Elaborating instance u_outbuft_ba
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 975)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.u_iodelay_dq
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1036)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.u_odelay_odt
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1095)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.u_odelay_csn
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1154)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.u_odelay_rasn
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1214)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.u_odelay_casn
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1273)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.u_odelay_wen
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1333)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.u_odelay_cke
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[0].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[1].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[2].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[3].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[4].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[5].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[6].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[7].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[8].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[9].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[10].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[11].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[12].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[13].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1399)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.i_mem_addr_0[14].u_odelay_addr
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.k_mem_ba[0].u_odelay_ba
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.k_mem_ba[1].u_odelay_ba
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ddr3_slice_top_v1_10.v(line number: 1464)] Give initial value 0 for the no drive pin EN_N in module instance test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top.k_mem_ba[2].u_odelay_ba
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 947)] Elaborating instance ddrphy_dfi
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_dfi_v1_3.vp(line number: 320)] Elaborating module ips2l_ddrphy_dfi_v1_3
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi} parameter value:
    DDR_TYPE = 2'b00
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_DQS_WIDTH = 32'b00000000000000000000000000000010
    MEM_DM_WIDTH = 32'b00000000000000000000000000000010
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3_ddrphy_top.v(line number: 1019)] Elaborating instance ddrphy_info
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_info_v1_0.vp(line number: 174)] Elaborating module ips2l_ddrphy_info_v1_0
I: Module instance {test_ddr/I_ips_ddr_top/u_ddrphy_top/ddrphy_info} parameter value:
    DDR_TYPE = 2'b00
    MEM_ADDR_WIDTH = 32'b00000000000000000000000000001111
    MEM_BANKADDR_WIDTH = 32'b00000000000000000000000000000011
    MR0_DDR3 = 16'b0001100100100000
    MR1_DDR3 = 16'b0000000000010100
    MR2_DDR3 = 16'b0000000000000000
    MR3_DDR3 = 16'b0000000000000000
    MR_DDR2 = 16'b0000101101000011
    EMR1_DDR2 = 16'b0000000000010100
    EMR2_DDR2 = 16'b0000000000000000
    EMR3_DDR2 = 16'b0000000000000000
    MR_LPDDR = 16'b0000000000100011
    EMR_LPDDR = 16'b0000000000000000
W: Verilog-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/ddr3.v(line number: 323)] Give initial value 0 for the no drive pin ddr_zqcs_req in module instance test_ddr/I_ips_ddr_top.u_ips_ddrc_top
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 868)] Elaborating instance u_axi_bist_top
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/axi_bist_top_v1_0.v(line number: 9)] Elaborating module axi_bist_top_v1_0
I: Module instance {test_ddr/u_axi_bist_top} parameter value:
    DATA_MASK_EN = 32'b00000000000000000000000000000000
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_SPACE_AW = 32'b00000000000000000000000000011100
    DATA_PATTERN0 = 8'b01010101
    DATA_PATTERN1 = 8'b10101010
    DATA_PATTERN2 = 8'b01111111
    DATA_PATTERN3 = 8'b10000000
    DATA_PATTERN4 = 8'b01010101
    DATA_PATTERN5 = 8'b10101010
    DATA_PATTERN6 = 8'b01111111
    DATA_PATTERN7 = 8'b10000000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/axi_bist_top_v1_0.v(line number: 139)] Elaborating instance u_test_main_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_main_ctrl_v1_0.v(line number: 7)] Elaborating module test_main_ctrl_v1_0
I: Module instance {test_ddr/u_axi_bist_top/u_test_main_ctrl} parameter value:
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_SPACE_AW = 32'b00000000000000000000000000011100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_main_ctrl_v1_0.v(line number: 216)] Elaborating instance I_prbs31_128bit
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/prbs31_128bit_v1_0.v(line number: 15)] Elaborating module prbs31_128bit_v1_0
I: Module instance {test_ddr/u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit} parameter value:
    PRBS_INIT = 128'b00010010001101000101011001111000100110101011110011011110111100001000011010000110001000000001011000000111000001110011001101101010
    PRBS_GEN_EN = 1'b1
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/axi_bist_top_v1_0.v(line number: 180)] Elaborating instance u_test_wr_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_wr_ctrl_v1_0.v(line number: 2)] Elaborating module test_wr_ctrl_v1_0
I: Module instance {test_ddr/u_axi_bist_top/u_test_wr_ctrl} parameter value:
    DATA_PATTERN0 = 8'b01010101
    DATA_PATTERN1 = 8'b10101010
    DATA_PATTERN2 = 8'b01111111
    DATA_PATTERN3 = 8'b10000000
    DATA_PATTERN4 = 8'b01010101
    DATA_PATTERN5 = 8'b10101010
    DATA_PATTERN6 = 8'b01111111
    DATA_PATTERN7 = 8'b10000000
    DATA_MASK_EN = 32'b00000000000000000000000000000000
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_SPACE_AW = 32'b00000000000000000000000000011100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_wr_ctrl_v1_0.v(line number: 335)] Elaborating instance u_prbs15_64bit
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/prbs15_64bit_v1_0.v(line number: 9)] Elaborating module prbs15_64bit_v1_0
I: Module instance {test_ddr/u_axi_bist_top/u_test_wr_ctrl/u_prbs15_64bit} parameter value:
    PRBS_INIT = 16'b0000000000000000
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/axi_bist_top_v1_0.v(line number: 225)] Elaborating instance u_test_rd_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_rd_ctrl_v1_0.v(line number: 2)] Elaborating module test_rd_ctrl_v1_0
I: Module instance {test_ddr/u_axi_bist_top/u_test_rd_ctrl} parameter value:
    DATA_PATTERN0 = 8'b01010101
    DATA_PATTERN1 = 8'b10101010
    DATA_PATTERN2 = 8'b01111111
    DATA_PATTERN3 = 8'b10000000
    DATA_PATTERN4 = 8'b01010101
    DATA_PATTERN5 = 8'b10101010
    DATA_PATTERN6 = 8'b01111111
    DATA_PATTERN7 = 8'b10000000
    DATA_MASK_EN = 32'b00000000000000000000000000000000
    CTRL_ADDR_WIDTH = 32'b00000000000000000000000000011100
    MEM_DQ_WIDTH = 32'b00000000000000000000000000010000
    MEM_SPACE_AW = 32'b00000000000000000000000000011100
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_rd_ctrl_v1_0.v(line number: 351)] Elaborating instance u_prbs15_64bit
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/prbs15_64bit_v1_0.v(line number: 9)] Elaborating module prbs15_64bit_v1_0
I: Module instance {test_ddr/u_axi_bist_top/u_test_rd_ctrl/u_prbs15_64bit} parameter value:
    PRBS_INIT = 16'b0000000000000000
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 855)] Width mismatch between port err_data_pre and signal bound to it for instantiated module axi_bist_top_v1_0
W: Verilog-2019: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 855)] Width mismatch between port err_data_aft and signal bound to it for instantiated module axi_bist_top_v1_0
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 918)] Elaborating instance u_adc_ctrl
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc_ctrl.v(line number: 1)] Elaborating module adc_ctrl
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc_ctrl.v(line number: 108)] Elaborating instance ADC_inst
I: Verilog-0003: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc.v(line number: 1)] Elaborating module ADC
I: Module instance {test_ddr/u_adc_ctrl/ADC_inst} parameter value:
    CREG_00H = 16'b1011000000111111
    CREG_01H = 16'b1100100000011110
    CREG_02H = 16'b0000000000000000
    CREG_31H = 16'b0000000000000000
    CREG_03H = 16'b0100000001111100
    CREG_04H = 16'b0000000000000000
    CREG_0AH = 16'b0000000000000000
    CREG_05H = 16'b0100000000000000
    CREG_06H = 16'b0100000000000000
    CREG_0CH = 16'b0000000000000000
    CREG_07H = 16'b0000000001111100
    CREG_08H = 16'b0000000000000000
    CREG_0EH = 16'b0000000000000000
    CREG_20H = 16'b0000000000000000
    CREG_21H = 16'b0000000000000000
    CREG_22H = 16'b0000000000000000
    CREG_23H = 16'b0000000000000000
    CREG_24H = 16'b0000000000000000
    CREG_25H = 16'b0000000000000000
    CREG_26H = 16'b0000000000000000
    CREG_27H = 16'b0000000000000000
    CREG_28H = 16'b0000000000000000
    CREG_29H = 16'b0000000000000000
    CREG_2AH = 16'b0000110011000010
    CREG_2BH = 16'b0000101001011011
I: Verilog-0004: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/adc/adc.v(line number: 83)] Elaborating instance XADC
Executing : rtl-elaborate successfully. Time elapsed: 0.290s wall, 0.016s user + 0.016s system = 0.031s CPU (10.8%)

Start rtl-prep.
Executing : rtl-prep successfully. Time elapsed: 0.217s wall, 0.000s user + 0.000s system = 0.000s CPU (n/a%)

Start rtl-infer.
Start DFF-inference.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 721)] Removed register node cnt[26] that is stuck at constant 0.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/example_design/rtl/test_ddr.v(line number: 721)] Removed register node cnt[25] that is stuck at constant 0.
I: Removed inst ddrphy_update_req that is redundant to update_start.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/ips2l_mcdq_dcp_buf_v1_2.vp(line number: 372)] Removed register node I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/cnt[6] that is stuck at constant 0.
I: Removed inst wrlvl_cs_n that is redundant to wrlvl_cas_n.
I: Removed inst wrlvl_we_n that is redundant to wrlvl_cas_n.
I: Removed inst genblk2.init_ras_n that is redundant to genblk2.init_cas_n.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 354)] Removed register node I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[3] that is stuck at constant 0.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 354)] Removed register node I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[2] that is stuck at constant 0.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 354)] Removed register node I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[3] that is stuck at constant 0.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_data_slice_wrcal_v1_10.vp(line number: 354)] Removed register node I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[2] that is stuck at constant 0.
I: Removed inst dqs_gate_comp_en_r that is redundant to dqs_gate_comp_done.
Executing : DFF-inference successfully.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp(line number: 217)] Removed register node I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/rst_clk_adj_dir that is stuck at constant 0.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_gate_update_ctrl_v1_3.vp(line number: 147)] Removed register node I_ips_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/update_start that is stuck at constant 0.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp(line number: 427)] Removed register node I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[2] that is stuck at constant 0.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp(line number: 427)] Removed register node I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[1] that is stuck at constant 0.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_eyecal_v1_5.vp(line number: 427)] Removed register node I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[0] that is stuck at constant 0.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 732)] Removed register node I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[2] that is stuck at constant 0.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 732)] Removed register node I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[1] that is stuck at constant 0.
W: Sdm-2000: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/ddrphy/ips2l_ddrphy_wrcal_v1_7.vp(line number: 732)] Removed register node I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[0] that is stuck at constant 0.
I: Removed inst mrs2dfi_ras_n that is redundant to mrs2dfi_cs_n.
I: Removed inst lp_ras_n[1:0] that is redundant to lp_cs_n[1:0].
I: Sdm-0001: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 180)] Found Ram mem, depth=16, width=2.
I: Sdm-0001: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 180)] Found Ram mem, depth=16, width=43.
I: Sdm-0001: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/rtl/mcdq_ctrl/distributed_fifo/rtl/ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp(line number: 180)] Found Ram mem, depth=32, width=5.
Executing : rtl-infer successfully. Time elapsed: 3.676s wall, 0.578s user + 0.250s system = 0.828s CPU (22.5%)

Start rtl-control-opt.
Executing : rtl-control-opt successfully. Time elapsed: 0.039s wall, 0.031s user + 0.000s system = 0.031s CPU (79.6%)

Start rtl-data-opt.
Executing : rtl-data-opt successfully. Time elapsed: 0.230s wall, 0.016s user + 0.000s system = 0.016s CPU (6.8%)

Start FSM inference.
I: FSM test_main_state_fsm[3:0] inferred.
I: FSM test_wr_state_fsm[2:0] inferred.
I: FSM test_rd_state_fsm[2:0] inferred.
I: FSM tx_cs_fsm[1:0] inferred.
I: FSM crt_st_fsm[3:0] inferred.
I: FSM dcp2dfi_odt_fsm[3:2] inferred.
I: FSM dcp2dfi_odt_fsm[1:0] inferred.
I: FSM mode_state_fsm[1:0] inferred.
I: FSM cstate_fsm[5:0] inferred.
I: FSM state_fsm[9:0] inferred.
I: FSM state_fsm[6:0] inferred.
I: FSM cpd_state_fsm[2:0] inferred.
I: FSM cpd_state_fsm[3:0] inferred.
I: FSM state_fsm[3:0] inferred.
I: FSM state_fsm[1:0] inferred.
I: FSM state_fsm[2:0] inferred.
I: FSM init_state_fsm[3:0] inferred.
I: FSM wrlvl_state_fsm[3:0] inferred.
W: Loop was found during constant probe.
I: FSM genblk1.rdcal_state_fsm[4:0] inferred.
I: FSM upcal_state_fsm[3:0] inferred.
I: FSM wrcal_state_fsm[3:0] inferred.
I: FSM eyecal_state_fsm[3:0] inferred.
I: FSM error_status_fsm[3:0] inferred.
I: FSM main_state_fsm[3:0] inferred.
I: FSM wl_state_fsm[2:0] inferred.
I: FSM state_fsm[3:0] inferred.
I: FSM state_fsm[3:0] inferred.
I: FSM gdet_state_fsm[2:0] inferred.
I: FSM rdchk_state0_fsm[3:0] inferred.
I: FSM rdchk_state1_fsm[3:0] inferred.
I: FSM gate_state_fsm[2:0] inferred.
Executing : FSM inference successfully. Time elapsed: 0.354s wall, 0.016s user + 0.016s system = 0.031s CPU (8.8%)

Start sdm2adm.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
I: Constant propagation done on N63_2 (bmsWIDEMUX).
I: Constant propagation done on N900 (bmsPMUX).
I: Constant propagation done on N500[0] (bmsWIDEMUX).
I: Constant propagation done on N52 (bmsWIDEMUX).
I: Constant propagation done on N924 (bmsPMUX).
I: Constant propagation done on N861_1 (bmsWIDEMUX).
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
I: Constant propagation done on N630_1 (bmsWIDEMUX).
I: Constant propagation done on N717 (bmsPMUX).
I: Constant propagation done on N551[0] (bmsWIDEMUX).
I: Constant propagation done on N601 (bmsWIDEMUX).
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
Executing : sdm2adm successfully. Time elapsed: 0.326s wall, 0.047s user + 0.000s system = 0.047s CPU (14.4%)

Saving design to DB.
Action compile: Real time elapsed is 0h:0m:10s
Action compile: CPU time elapsed is 0h:0m:1s
Action compile: Process CPU time elapsed is 0h:0m:1s
Current time: Wed Jan  8 10:11:11 2025
Action compile: Peak memory pool usage is 197 MB
