#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: E:\PDS_FPGA\PDS_2022.2-SP6.4\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.26100
#Hostname: 傻额宁儿
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Thu Nov  6 19:58:32 2025
Executing : add_design -verilog F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v
Executing : add_design -verilog F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp successfully.
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp
Executing : add_design -verilog E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp successfully.
Executing : add_constraint -fdc F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.fdc
Executing : add_constraint -fdc F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.fdc successfully.
Executing : set_arch -family Logos2 -device PG2L50H -package FBG484 -speedgrade -6
Executing : set_arch -family Logos2 -device PG2L50H -package FBG484 -speedgrade -6 successfully.


Executing : compile


Process "Compile" started.
Current time: Thu Nov  6 19:58:32 2025
Compiling architecture definition.
Analyzing project file 'F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/dbcore.pds'.
License checkout: fabric_ads from E:\PDS_FPGA\PDS_2022.2-SP6.4\new_pds_F4A80DA47D72.lic
Compiling verification operator library.
Loading technology operator library.
Compiling technology operator library.
Compiling technology operator (valence) library.
I: Enable Verilog2k features and keywords
Start rtl-analyze.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v
I: Verilog-0001: Analyzing file F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v
I: Verilog-0002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 1)] Analyzing module CORES (library work)
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 95)] Convert attribute name from syn_noprune to PAP_NOPRUNE
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 122)] Convert attribute name from syn_noprune to PAP_NOPRUNE
I: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 144)] Convert attribute name from syn_noprune to PAP_NOPRUNE
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp(line number: 90)] Analyzing module ips_dbc_cfg_reg_file_v1_0 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 301)] Analyzing module ips_dbc_compare_256b_v1_0 (library work)
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Analyzing module subtract_16b (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp(line number: 89)] Analyzing module ips_dbc_data_capture_mem_v1_1 (library work)
I: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp(line number: 108)] Convert attribute name from syn_ramstyle to PAP_RAM_STYLE
I: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp(line number: 120)] Convert attribute name from syn_ramstyle to PAP_RAM_STYLE
I: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp(line number: 132)] Convert attribute name from syn_ramstyle to PAP_RAM_STYLE
I: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp(line number: 144)] Convert attribute name from syn_ramstyle to PAP_RAM_STYLE
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 2822)] Analyzing module ips_dbc_debug_core_v1_4 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp(line number: 271)] Analyzing module ips_dbc_hub_decode_v1_2 (library work)
I: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp(line number: 276)] Convert attribute name from syn_preserve to PAP_PRESERVE
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp(line number: 251)] Analyzing module ips_dbc_rd_addr_gen_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 489)] Analyzing module ips_dbc_storage_condition_v1_3 (library work)
I: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 497)] Convert attribute name from syn_preserve to PAP_PRESERVE
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp(line number: 177)] Analyzing module ips_dbc_storage_qualification_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_qualification_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 409)] Analyzing module ips_dbc_trig_unit_v1_3 (library work)
I: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 819)] Convert attribute name from syn_allow_retiming to PAP_ALLOW_RETIMING
W: Verilog-2018: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 819)] The value type of attribute syn_allow_retiming is illegal, ignore the attribute
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 278)] Analyzing module ips_dbc_trigger_condition_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp(line number: 142)] Analyzing module ips_dbc_trigger_output_v1_2 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_output_v1_2.vp successfully.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp
I: Verilog-0001: Analyzing file E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp
I: Verilog-0002: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp(line number: 282)] Analyzing module ips_jtag_hub_v1_3 (library work)
Parsing done.
Executing : .rtl_analyze -work work -include_path {F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev} E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp successfully.
I: Top module is unspecified.
I: Module "CORES" is set as top module.
Executing : rtl-analyze successfully. Time elapsed: 1.653s wall, 0.062s user + 0.000s system = 0.062s CPU (3.8%)

Start rtl-elaborate.
I: Verilog-0003: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 1)] Elaborating module CORES
I: Module instance {CORES} parameter value:
    CTRL_PORT_NUM = 32'b00000000000000000000000000000001
    UJTAG_SEL = 32'b00000000000000000000000000000000
    AREA_SPEED = 32'b00000000000000000000000000000000
    FLA0_MEM_STYLE = 32'b00000000000000000000000000000001
    FLA0_TRIG_PORT_NUM = 32'b00000000000000000000000000000001
    FLA0_MAX_SEQ_LEVEL = 32'b00000000000000000000000000000001
    FLA0_EN_WINDOWS = 32'b00000000000000000000000000000000
    FLA0_CLK_EDGE = 32'b00000000000000000000000000000001
    FLA0_DATA_DEPTH = 32'b00000000000000000000000000001100
    FLA0_EN_STOR_QUAL = 32'b00000000000000000000000000000000
    FLA0_DATA_SAME_AS_TRIG = 32'b00000000000000000000000000000001
    FLA0_DATA_WIDTH = 32'b00000000000000000000000011001011
    FLA0_TRIG0_PORT_WIDTH = 32'b00000000000000000000000011001011
    FLA0_TRIG0_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG0_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG0_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG0_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG1_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG1_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG1_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG1_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG1_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG2_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG2_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG2_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG2_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG2_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG3_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG3_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG3_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG3_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG3_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG4_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG4_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG4_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG4_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG4_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG5_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG5_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG5_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG5_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG5_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG6_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG6_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG6_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG6_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG6_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG7_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG7_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG7_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG7_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG7_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG8_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG8_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG8_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG8_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG8_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG9_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG9_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG9_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG9_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG9_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG10_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG10_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG10_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG10_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG10_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG11_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG11_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG11_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG11_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG11_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG12_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG12_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG12_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG12_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG12_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG13_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG13_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG13_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG13_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG13_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG14_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG14_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG14_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG14_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG14_EXCLUDE = 32'b00000000000000000000000000000000
    FLA0_TRIG15_PORT_WIDTH = 32'b00000000000000000000000000001000
    FLA0_TRIG15_MATCH_UNIT = 32'b00000000000000000000000000000001
    FLA0_TRIG15_CNT_WIDTH = 32'b00000000000000000000000000000000
    FLA0_TRIG15_MATCH_TYPE = 32'b00000000000000000000000000000001
    FLA0_TRIG15_EXCLUDE = 32'b00000000000000000000000000000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 122)] Elaborating instance u_GTP_SCANCHAIN_PG
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 144)] Elaborating instance u_jtag_hub
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_jtag_hub_v1_3.vp(line number: 282)] Elaborating module ips_jtag_hub_v1_3
I: Module instance {CORES/u_jtag_hub} parameter value:
    CTRL_PORT_NUM = 32'b00000000000000000000000000000001
    UJTAG_SEL = 32'b00000000000000000000000000000000
I: Verilog-0004: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 260)] Elaborating instance u_debug_core_0
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 2822)] Elaborating module ips_dbc_debug_core_v1_4
I: Module instance {CORES/u_debug_core_0} parameter value:
    FLA_VERSION = 32'b10010000000000011111000000000011
    AREA_SPEED = 32'b00000000000000000000000000000000
    MEM_STYLE = 32'b00000000000000000000000000000001
    TRIG_PORT_NUM = 32'b00000000000000000000000000000001
    MAX_SEQ_LEVEL = 32'b00000000000000000000000000000001
    EN_TRIG_OUT = 32'b00000000000000000000000000000000
    EN_WINDOWS = 32'b00000000000000000000000000000000
    CLK_EDGE = 32'b00000000000000000000000000000001
    DATA_DEPTH = 32'b00000000000000000000000000001100
    EN_STOR_QUAL = 32'b00000000000000000000000000000000
    DATA_SAME_AS_TRIG = 32'b00000000000000000000000000000001
    DATA_WIDTH = 32'b00000000000000000000000011001011
    TRIG0_PORT_WIDTH = 32'b00000000000000000000000011001011
    TRIG0_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG0_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG0_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG0_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG1_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG1_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG1_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG1_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG1_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG2_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG2_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG2_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG2_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG2_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG3_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG3_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG3_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG3_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG3_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG4_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG4_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG4_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG4_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG4_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG5_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG5_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG5_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG5_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG5_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG6_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG6_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG6_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG6_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG6_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG7_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG7_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG7_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG7_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG7_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG8_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG8_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG8_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG8_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG8_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG9_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG9_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG9_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG9_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG9_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG10_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG10_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG10_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG10_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG10_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG11_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG11_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG11_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG11_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG11_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG12_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG12_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG12_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG12_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG12_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG13_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG13_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG13_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG13_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG13_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG14_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG14_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG14_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG14_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG14_EXCLUDE = 32'b00000000000000000000000000000000
    TRIG15_PORT_WIDTH = 32'b00000000000000000000000000001000
    TRIG15_MATCH_UNIT = 32'b00000000000000000000000000000001
    TRIG15_CNT_WIDTH = 32'b00000000000000000000000000000000
    TRIG15_MATCH_TYPE = 32'b00000000000000000000000000000001
    TRIG15_EXCLUDE = 32'b00000000000000000000000000000000
    INIT_ENABLE = 32'b00000000000000000000000000000000
    INIT_TRIG_COND = 32'b00000000000000000000000000000000
    INIT_TRIG_OUT = 3'b000
    INIT_STOR_TYPE = 32'b00000000000000000000000000000000
    INIT_STOR_QUAL = 32'b00000000000000000000000000000000
    INIT_M0_CONFIG = 32'b00000000000000000000000000000000
    INIT_M1_CONFIG = 32'b00000000000000000000000000000000
    INIT_M2_CONFIG = 32'b00000000000000000000000000000000
    INIT_M3_CONFIG = 32'b00000000000000000000000000000000
    INIT_M4_CONFIG = 32'b00000000000000000000000000000000
    INIT_M5_CONFIG = 32'b00000000000000000000000000000000
    INIT_M6_CONFIG = 32'b00000000000000000000000000000000
    INIT_M7_CONFIG = 32'b00000000000000000000000000000000
    INIT_M8_CONFIG = 32'b00000000000000000000000000000000
    INIT_M9_CONFIG = 32'b00000000000000000000000000000000
    INIT_M10_CONFIG = 32'b00000000000000000000000000000000
    INIT_M11_CONFIG = 32'b00000000000000000000000000000000
    INIT_M12_CONFIG = 32'b00000000000000000000000000000000
    INIT_M13_CONFIG = 32'b00000000000000000000000000000000
    INIT_M14_CONFIG = 32'b00000000000000000000000000000000
    INIT_M15_CONFIG = 32'b00000000000000000000000000000000
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5059)] Elaborating instance u_hub_data_decode
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_hub_decode_v1_2.vp(line number: 271)] Elaborating module ips_dbc_hub_decode_v1_2
I: Module instance {CORES/u_debug_core_0/u_hub_data_decode} parameter value:
    NEW_JTAG_IF = 32'b00000000000000000000000000000001
    INIT_ENABLE = 32'b00000000000000000000000000000000
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5196)] Elaborating instance u0_trig_unit
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 409)] Elaborating module ips_dbc_trig_unit_v1_3
W: Sdm-2008: The attribute named register_balancing is not legal, then it has no effect, ignore its value.
I: Module instance {CORES/u_debug_core_0/u0_trig_unit} parameter value:
    NEW_JTAG_IF = 32'b00000000000000000000000000000001
    MU_PIPELINE = 32'b00000000000000000000000000000000
    MU_TYPE = 32'b00000000000000000000000000000001
    MU_WIDTH = 32'b00000000000000000000000011001011
    MU_CNT = 32'b00000000000000000000000000000000
    SIGNAL_MSB = 32'b00000000000000000000000110010101
    MU_CHAIN_BIT = 32'b00000000000000000000001001100010
    INIT_MU_CONFIG_SRC = 805'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 531)] Elaborating instance u_cfg_reg_file
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp(line number: 90)] Elaborating module ips_dbc_cfg_reg_file_v1_0
I: Module instance {CORES/u_debug_core_0/u0_trig_unit/u_cfg_reg_file} parameter value:
    NEW_JTAG_IF = 32'b00000000000000000000000000000001
    c_CFG_CHAIN_BIT = 32'b00000000000000000000001001100010
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 739)] Elaborating instance u_larger_than
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 301)] Elaborating module ips_dbc_compare_256b_v1_0
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 317)] Elaborating instance I_subtract_16b
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 494)] Elaborating module subtract_16b
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 748)] Elaborating instance u_less_than
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_compare_256b_v1_0.vp(line number: 301)] Elaborating module ips_dbc_compare_256b_v1_0
W: Verilog-2021: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 577)] Net value in ips_dbc_trig_unit_v1_3(original module ips_dbc_trig_unit_v1_3) does not have a driver, tie it to 0
W: Verilog-2021: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trig_unit_v1_3.vp(line number: 578)] Net value2 in ips_dbc_trig_unit_v1_3(original module ips_dbc_trig_unit_v1_3) does not have a driver, tie it to 0
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5830)] Elaborating instance u_Trigger_Condition
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 278)] Elaborating module ips_dbc_trigger_condition_v1_3
I: Module instance {CORES/u_debug_core_0/u_Trigger_Condition} parameter value:
    NEW_JTAG_IF = 32'b00000000000000000000000000000001
    TRIG_PIPELINE = 32'b00000000000000000000000000000000
    MU_PIPELINE = 32'b00000000000000000000000000000000
    TRIG0_TO_15_MU = 32'b00000000000000000000000000000001
    MAX_SEQ_LEVEL = 32'b00000000000000000000000000000001
    TRIG_COND_CHAIN_BIT = 32'b00000000000000000000000000000011
    INIT_TRIG_COND = 32'b00000000000000000000000000000000
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 379)] Elaborating instance u_cfg_reg_file
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp(line number: 90)] Elaborating module ips_dbc_cfg_reg_file_v1_0
I: Module instance {CORES/u_debug_core_0/u_Trigger_Condition/u_cfg_reg_file} parameter value:
    NEW_JTAG_IF = 32'b00000000000000000000000000000001
    c_CFG_CHAIN_BIT = 32'b00000000000000000000000000000011
W: Verilog-2021: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_trigger_condition_v1_3.vp(line number: 513)] Net seq_match_s in ips_dbc_trigger_condition_v1_3(original module ips_dbc_trigger_condition_v1_3) does not have a driver, tie it to 0
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5907)] Elaborating instance u_Storage_Condition
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 489)] Elaborating module ips_dbc_storage_condition_v1_3
I: Module instance {CORES/u_debug_core_0/u_Storage_Condition} parameter value:
    EN_WINDOWS = 32'b00000000000000000000000000000000
    NEW_JTAG_IF = 32'b00000000000000000000000000000001
    DATA_DEPTH = 32'b00000000000000000000000000001100
    STOR_TYPE_CHAIN_BIT = 32'b00000000000000000000000000010001
    INIT_STOR_TYPE = 32'b00000000000000000000000000000000
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 570)] Elaborating instance u_cfg_reg_file
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_cfg_reg_file_v1_0.vp(line number: 90)] Elaborating module ips_dbc_cfg_reg_file_v1_0
I: Module instance {CORES/u_debug_core_0/u_Storage_Condition/u_cfg_reg_file} parameter value:
    NEW_JTAG_IF = 32'b00000000000000000000000000000001
    c_CFG_CHAIN_BIT = 32'b00000000000000000000000000010001
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[0] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[1] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[2] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[3] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[4] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[5] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[6] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[7] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[8] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[9] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[10] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[11] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_storage_condition_v1_3.vp(line number: 900)] Net counter_nsa[12] in ips_dbc_storage_condition_v1_3(original module ips_dbc_storage_condition_v1_3) does not have a driver, tie it to 0
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 6004)] Elaborating instance u_Data_Capture_Memory
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp(line number: 89)] Elaborating module ips_dbc_data_capture_mem_v1_1
I: Module instance {CORES/u_debug_core_0/u_Data_Capture_Memory} parameter value:
    MEM_STYLE = 32'b00000000000000000000000000000001
    DATA_DEPTH = 32'b00000000000000000000000000001100
    DATA_WIDTH = 32'b00000000000000000000000011001100
I: Verilog-0004: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 6032)] Elaborating instance u_rd_addr_gen
I: Verilog-0003: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_rd_addr_gen_v1_3.vp(line number: 251)] Elaborating module ips_dbc_rd_addr_gen_v1_3
I: Module instance {CORES/u_debug_core_0/u_rd_addr_gen} parameter value:
    NEW_JTAG_IF = 32'b00000000000000000000000000000001
    INFO_CHAIN_BIT = 32'b00000000000000000000000001010010
    INFO_CHAIN = 412'b0000000001000001110000000000000100000111000000000000010000011100000000000001000001110000000000000100000111000000000000010000011100000000000001000001110000000000000100000111000000000000010000011100000000000001000001110000000000000100000111000000000000010000011100000000000001000001110000000000000100000111000000000000010000011100000000000001110010100000000000000000000110010101011010010000000000011111000000000011
    DATA_DEPTH = 32'b00000000000000000000000000001100
    DATA_BIT = 32'b00000000000000000000000011001011
    DATA_CHAIN_BIT = 32'b00000000000000000000000011001100
    STATUS_CHAIN_BIT = 32'b00000000000000000000000000001101
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[1] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[2] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[3] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[4] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[5] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[6] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[7] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[8] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[9] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[10] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[11] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[12] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[13] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[14] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[15] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[17] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5037)] Net conf_rdlast[19] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[1] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[2] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[3] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[4] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[5] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[6] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[7] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[8] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[9] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[10] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[11] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[12] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[13] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[14] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[15] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[17] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2020: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_debug_core_v1_4.vp(line number: 5038)] Net conf_rdata[19] in ips_dbc_debug_core_v1_4(original module ips_dbc_debug_core_v1_4) does not have a driver, tie it to 0
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 122)] Give initial value 0 for the no drive pin TCK in module instance CORES.u_GTP_SCANCHAIN_PG
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 122)] Give initial value 0 for the no drive pin TDI in module instance CORES.u_GTP_SCANCHAIN_PG
W: Verilog-2023: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 122)] Give initial value 0 for the no drive pin TMS in module instance CORES.u_GTP_SCANCHAIN_PG
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[1] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[2] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[3] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[4] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[5] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[6] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[7] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[8] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[9] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[10] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[11] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[12] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[13] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[14] in CORES(original module CORES) does not have a driver, tie it to 0
W: Verilog-2020: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/cores.v(line number: 136)] Net hub_tdo[15] in CORES(original module CORES) does not have a driver, tie it to 0
Executing : rtl-elaborate successfully. Time elapsed: 0.420s wall, 0.281s user + 0.141s system = 0.422s CPU (100.6%)

Start rtl-prep.
Executing : rtl-prep successfully. Time elapsed: 0.207s wall, 0.219s user + 0.000s system = 0.219s CPU (105.6%)

Start rtl-infer.
Start DFF-inference.
I: Removed inst tu_sig_dly that is redundant to signal_dly[202:0].
Executing : DFF-inference successfully.
I: Sdm-0001: [E:/PDS_FPGA/PDS_2022.2-SP6.4/arch/vendor/pango/arch/cdt/debug_core_rtls_pdir/ips_dbc_data_capture_mem_v1_1.vp(line number: 122)] Found Ram block_ram.ram_data, depth=4096, width=204.
Executing : rtl-infer successfully. Time elapsed: 2.001s wall, 1.578s user + 0.406s system = 1.984s CPU (99.2%)

Start rtl-control-opt.
Executing : rtl-control-opt successfully. Time elapsed: 0.061s wall, 0.047s user + 0.000s system = 0.047s CPU (76.5%)

Start rtl-data-opt.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
Executing : rtl-data-opt successfully. Time elapsed: 0.301s wall, 0.312s user + 0.000s system = 0.312s CPU (103.8%)

Start FSM inference.
Executing : FSM inference successfully. Time elapsed: 0.027s wall, 0.031s user + 0.000s system = 0.031s CPU (117.3%)

Start sdm2adm.
I: Constant propagation done on N412 (bmsWIDEMUX).
I: Constant propagation done on N362 (bmsWIDEMUX).
I: Constant propagation done on N1186 (bmsWIDEMUX).
I: Constant propagation done on N1143 (bmsWIDEMUX).
I: Constant propagation done on N1100 (bmsWIDEMUX).
I: Constant propagation done on N1057 (bmsWIDEMUX).
I: Constant propagation done on N1014 (bmsWIDEMUX).
I: Constant propagation done on N971 (bmsWIDEMUX).
I: Constant propagation done on N928 (bmsWIDEMUX).
I: Constant propagation done on N885 (bmsWIDEMUX).
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
W: Loop was found during constant probe.
Executing : sdm2adm successfully. Time elapsed: 0.305s wall, 0.281s user + 0.016s system = 0.297s CPU (97.3%)

Saving design to DB.
Action compile: Real time elapsed is 0h:0m:8s
Action compile: CPU time elapsed is 0h:0m:4s
Action compile: Process CPU time elapsed is 0h:0m:4s
Current time: Thu Nov  6 19:58:39 2025
Action compile: Peak memory pool usage is 218 MB
Action from compile to compile: Total Real Time elapsed is 0h:0m:8s
Action from compile to compile: Total CPU time elapsed is 0h:0m:4s
Action from compile to compile: Total Process CPU Time elapsed is 0h:0m:4s
Process "Compile" done.
Executing : compile successfully.


Executing : synthesize -ADS -disable_io_insertion


Process "Synthesize" started.
Current time: Thu Nov  6 19:58:39 2025
Compiling architecture definition.
Analyzing project file 'F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/device_map/ins_rev/dbcore.pds'.
License checkout: fabric_ads from E:\PDS_FPGA\PDS_2022.2-SP6.4\new_pds_F4A80DA47D72.lic
Compiling verification operator library.
Compiling common defs.
Loading technology operator library.
Compiling technology operator library.
Compiling technology operator (valence) library.
Reading design from compile DB
Reading design from compile DB successfully.
NOTE: The technology fpga was specified.
NOTE: delay_model specified was generic_cmos.
NOTE: Using the fpga syntax tables...
Totals:
 Calls to malloc = 0
 Calls to calloc = 148672

Constraint check start.
Compiling prim grid devices.
Building architecture model.
Loading device packaging model.
Building architecture floorplan logic view.
Executing : get_pins u_GTP_SCANCHAIN_PG.TCK_USER
Executing : get_pins u_GTP_SCANCHAIN_PG.TCK_USER successfully.
Executing : create_clock -name DebugCore_JCLK [get_pins u_GTP_SCANCHAIN_PG.TCK_USER] -period 50.000 -waveform {0.000 25.000}
Executing : create_clock -name DebugCore_JCLK [get_pins u_GTP_SCANCHAIN_PG.TCK_USER] -period 50.000 -waveform {0.000 25.000} successfully.
Executing : get_pins u_GTP_SCANCHAIN_PG.CAPDR
Executing : get_pins u_GTP_SCANCHAIN_PG.CAPDR successfully.
Executing : create_clock -name DebugCore_CAPTURE [get_pins u_GTP_SCANCHAIN_PG.CAPDR] -period 100.000 -waveform {25.000 75.000}
Executing : create_clock -name DebugCore_CAPTURE [get_pins u_GTP_SCANCHAIN_PG.CAPDR] -period 100.000 -waveform {25.000 75.000} successfully.
Executing : set_clock_groups -name DebugCoreClockGroup -asynchronous -group {DebugCore_JCLK DebugCore_CAPTURE}
Executing : set_clock_groups -name DebugCoreClockGroup -asynchronous -group {DebugCore_JCLK DebugCore_CAPTURE} successfully.
W: ConstraintEditor-4019: Port Bus 'fla0_data_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig0_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig1_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig2_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig3_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig4_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig5_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig6_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig7_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig8_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig9_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig10_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig11_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig12_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig13_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig14_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'fla0_trig15_i' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'dbc_urck_in' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'dbc_utdi_in' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_clk' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'fla0_rstn' unspecified I/O constraint.
Constraint check end.

C: SDC-2025: Clock source 'n:fla0_clk' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
Executing : get_ports fla0_clk
Executing : get_ports fla0_clk successfully.
Executing : create_clock -name CORES|fla0_clk [get_ports fla0_clk] -period 1000.000 -waveform {0.000 500.000} -add
Executing : create_clock -name CORES|fla0_clk [get_ports fla0_clk] -period 1000.000 -waveform {0.000 500.000} -add successfully.
Executing : set_clock_groups -name Inferred_clock_group_0 -asynchronous -group CORES|fla0_clk
Executing : set_clock_groups -name Inferred_clock_group_0 -asynchronous -group CORES|fla0_clk successfully.
Start pre-mapping.
I: Removed bmsWIDEDFFCPE inst match_single_to_16[14] that is redundant to match_single_to_16[13]
I: Removed bmsWIDEDFFCPE inst match_single_to_16[15] that is redundant to match_single_to_16[13]
W: Removed bmsWIDEDFFCPE inst cs.conf_sel[15:0] at 15 that is stuck at constant 0.
I: Constant propagation done on u_jtag_hub/cs.conf_sel[15:0] (bmsWIDEDFFCPE).
Executing : pre-mapping successfully. Time elapsed: 0.303s wall, 0.328s user + 0.141s system = 0.469s CPU (154.8%)

Start mod-gen.
W: Public-4008: Instance 'u_larger_than/result_equal_to' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/result_equal_to_16' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/result_larger_than' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/result_larger_than_8h[1:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/result_larger_than_8l' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[15].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[15].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[0].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[0].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[1].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[1].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[2].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[2].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[3].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[3].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[4].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[4].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[5].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[5].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[6].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[6].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[7].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[7].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[8].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[8].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[9].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[9].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[10].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[10].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[11].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[11].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[12].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[12].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[13].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[13].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[14].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_larger_than/sub[14].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/result_equal_to' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/result_equal_to_16' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/result_larger_than' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/result_larger_than_8h[1:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/result_larger_than_8l' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[15].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[15].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[0].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[0].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[1].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[1].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[2].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[2].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[3].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[3].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[4].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[4].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[5].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[5].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[6].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[6].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[7].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[7].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[8].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[8].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[9].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[9].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[10].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[10].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[11].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[11].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[12].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[12].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[13].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[13].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[14].I_subtract_16b/subtract_16b_equal_to_zero' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_less_than/sub[14].I_subtract_16b/subtract_16b_flag' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u0_trig_unit/test_reg0' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u0_trig_unit/u_cfg_reg_file/getback_n.cfg_rdlast' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_Storage_Condition/u_cfg_reg_file/getback_n.cfg_rdlast' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_Trigger_Condition/u_cfg_reg_file/getback_n.cfg_rdlast' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
I: Constant propagation done on u_debug_core_0/u0_trig_unit/N11644 (bmsREDOR).
I: Constant propagation done on u_debug_core_0/u0_trig_unit/N11645 (bmsREDAND).
I: Constant propagation done on u_debug_core_0/u_Storage_Condition/N301 (bmsWIDEMUX).
I: Constant propagation done on u_debug_core_0/u_Storage_Condition/N336 (bmsREDOR).
I: Constant propagation done on u_debug_core_0/u_Storage_Condition/N459 (bmsREDAND).
I: Constant propagation done on u_debug_core_0/u_Storage_Condition/N446 (bmsREDAND).
I: Removed bmsWIDEDFFCPE inst u_debug_core_0/u0_trig_unit/signal_dly[202:0] that is redundant to u_debug_core_0/TRIG0_ff[1][202:0]
I: Constant propagation done on u_debug_core_0/u_rd_addr_gen/N675 (bmsREDAND).
I: Constant propagation done on u_debug_core_0/u_rd_addr_gen/N676 (bmsREDAND).
I: Constant propagation done on u_debug_core_0/u_rd_addr_gen/N677 (bmsREDAND).
I: Removed bmsREDOR inst u_debug_core_0/u_Storage_Condition/N327 that is redundant to u_debug_core_0/u_Storage_Condition/N316
Executing : mod-gen successfully. Time elapsed: 1.108s wall, 1.062s user + 0.297s system = 1.359s CPU (122.6%)

Start logic-optimization.
I: Removed bmsREDAND inst u_debug_core_0/u0_trig_unit/u_cfg_reg_file/ND2[609] that is redundant to u_debug_core_0/u0_trig_unit/u_cfg_reg_file/N494
I: Removed bmsWIDEDFFCPE inst u_debug_core_0/u0_trig_unit/match_single_to_16[13] that is redundant to u_debug_core_0/data_start
Executing : logic-optimization successfully. Time elapsed: 2.121s wall, 1.625s user + 0.500s system = 2.125s CPU (100.2%)

Start tech-mapping phase 1.
W: Public-4008: Instance 'cs.conf_sel[13]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[14]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[15]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[1]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[2]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[3]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[4]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[5]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[6]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[7]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[8]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[9]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[10]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[11]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'cs.conf_sel[12]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
Executing : tech-mapping phase 1 successfully. Time elapsed: 0.197s wall, 0.188s user + 0.000s system = 0.188s CPU (95.0%)

Start tech-mapping phase 2.
Executing : tech-mapping phase 2 successfully. Time elapsed: 1.683s wall, 1.609s user + 0.578s system = 2.188s CPU (130.0%)

Start tech-optimization.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[1]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[2]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[3]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[4]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[5]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[6]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[7]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[8]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[9]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[10]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[11]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[12]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[13]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[14]'.
I: Adm-6001: Trying to disconnect a un-connected port 'conf_sel[15]'.
I: Adm-6001: Trying to disconnect a un-connected port 'h_rstn'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[1]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[2]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[3]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[4]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[5]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[6]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[7]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[8]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[9]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[10]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[11]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[12]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[13]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[14]'.
I: Adm-6001: Trying to disconnect a un-connected port 'hub_tdo[15]'.
Executing : tech-optimization successfully. Time elapsed: 1.616s wall, 1.547s user + 0.188s system = 1.734s CPU (107.3%)

Start phys-optimization.
Executing : phys-optimization successfully. Time elapsed: 0.000s wall, 0.000s user + 0.000s system = 0.000s CPU (n/a%)

Start restore-hierarchy.
Executing : restore-hierarchy successfully. Time elapsed: 0.239s wall, 0.250s user + 0.000s system = 0.250s CPU (104.8%)


Cell Usage:
GTP_DFF                     621 uses
GTP_DFF_C                  1956 uses
GTP_DFF_CE                  695 uses
GTP_DFF_E                     9 uses
GTP_DFF_P                    12 uses
GTP_DFF_PE                   26 uses
GTP_DRM36K_E1                23 uses
GTP_INV                       4 uses
GTP_LUT2                      5 uses
GTP_LUT3                      6 uses
GTP_LUT4                     45 uses
GTP_LUT5                    238 uses
GTP_LUT6                    326 uses
GTP_LUT6CARRY                64 uses
GTP_LUT6D                   889 uses
GTP_MUX2LUT7                 84 uses
GTP_MUX2LUT8                 40 uses
GTP_ROM32X2                  10 uses
GTP_SCANCHAIN_E1              1 use

I/O ports: 0

Mapping Summary:
Total LUTs: 1583 of 35800 (4.42%)
	LUTs as dram: 0 of 9500 (0.00%)
	LUTs as logic: 1583
Total Registers: 3319 of 71600 (4.64%)
Total Latches: 0

DRM36K/FIFO:
Total DRM = 23.0 of 85 (27.06%)

APMs:
Total APMs = 0.00 of 120 (0.00%)

Total I/O ports = 0 of 250 (0.00%)


Overview of Control Sets:

Number of unique control sets : 23

Histogram:
**************************************************************
  Fanout      | Count    | Sync Set/Reset    Async Set/Reset
--------------------------------------------------------------
  [0, 2)      | 1        | 0                 1
  [2, 4)      | 5        | 1                 4
  [4, 6)      | 3        | 0                 3
  [6, 8)      | 2        | 1                 1
  [8, 10)     | 1        | 1                 0
  [10, 12)    | 1        | 0                 1
  [12, 14)    | 5        | 0                 5
  [14, 16)    | 0        | 0                 0
  [16, Inf)   | 5        | 1                 4
--------------------------------------------------------------
  The maximum fanout: 1896
==============================================================

Flip-Flop Distribution:
************************************************************************
  Clock Enable    Sync Set/Reset    Async Set/Reset    Total Registers
------------------------------------------------------------------------
  NO              NO                NO                 621
  NO              NO                YES                1968
  NO              YES               NO                 0
  YES             NO                NO                 9
  YES             NO                YES                721
  YES             YES               NO                 0
========================================================================

Latch Distribution:
************************************************
  Gate Enable    Preset/Clear    Total Latches
************************************************
  NO             NO              0
  NO             YES             0
  YES            NO              0
  YES            YES             0
************************************************

Design 'CORES' has been successfully synthesized to architecture-specific objects.
Saving design to DB.
Saving design to CORES_syn.vm
Constructing timing graph ...
Timing graph has been constructed successfully
W: Timing-4086: Port 'fla0_rstn' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[0]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[1]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[2]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[3]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[4]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[5]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[6]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[7]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[8]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[9]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[10]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[11]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[12]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[13]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[14]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[15]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[16]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[17]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[18]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[19]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[20]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[21]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[22]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[23]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[24]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[25]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[26]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[27]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[28]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[29]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[30]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[31]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[32]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[33]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[34]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[35]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[36]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[37]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[38]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[39]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[40]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[41]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[42]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[43]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[44]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[45]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[46]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[47]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[48]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[49]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[50]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[51]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[52]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[53]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[54]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[55]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[56]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[57]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[58]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[59]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[60]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[61]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[62]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[63]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[64]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[65]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[66]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[67]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[68]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[69]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[70]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[71]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[72]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[73]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[74]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[75]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[76]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[77]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[78]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[79]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[80]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[81]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[82]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[83]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[84]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[85]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[86]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[87]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[88]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[89]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[90]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[91]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[92]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[93]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[94]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[95]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[96]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[97]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[98]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[99]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[100]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[101]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[102]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[103]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[104]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[105]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[106]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[107]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[108]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[109]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[110]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[111]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[112]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[113]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[114]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[115]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[116]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[117]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[118]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[119]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[120]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[121]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[122]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[123]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[124]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[125]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[126]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[127]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[128]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[129]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[130]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[131]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[132]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[133]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[134]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[135]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[136]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[137]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[138]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[139]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[140]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[141]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[142]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[143]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[144]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[145]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[146]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[147]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[148]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[149]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[150]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[151]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[152]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[153]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[154]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[155]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[156]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[157]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[158]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[159]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[160]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[161]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[162]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[163]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[164]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[165]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[166]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[167]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[168]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[169]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[170]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[171]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[172]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[173]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[174]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[175]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[176]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[177]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[178]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[179]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[180]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[181]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[182]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[183]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[184]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[185]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[186]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[187]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[188]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[189]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[190]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[191]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[192]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[193]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[194]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[195]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[196]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[197]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[198]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[199]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[200]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[201]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'fla0_trig0_i[202]' is not constrained, it is treated as combinational input.
Action synthesize: Real time elapsed is 0h:0m:18s
Action synthesize: CPU time elapsed is 0h:0m:14s
Action synthesize: Process CPU time elapsed is 0h:0m:15s
Current time: Thu Nov  6 19:58:56 2025
Action synthesize: Peak memory pool usage is 450 MB
Action from compile to synthesize: Total Real Time elapsed is 0h:0m:26s
Action from compile to synthesize: Total CPU time elapsed is 0h:0m:18s
Action from compile to synthesize: Total Process CPU Time elapsed is 0h:0m:19s
Process "Synthesize" done.
Executing : synthesize -ADS -disable_io_insertion successfully.
