<?xml version="1.0" encoding="UTF-8"?>
<ip_inst>
    <header>
        <vendor>Pango</vendor>
        <id>042004</id>
        <display_name>PCI Express</display_name>
        <name>Logos2 PCI Express</name>
        <version>1.8</version>
        <instance>pcie_test</instance>
        <family>Logos2</family>
        <device>PG2L50H</device>
        <package>FBG484</package>
        <speedgrade>-6</speedgrade>
        <generator version="2022.2-SP6.4" build="146967">IP Compiler</generator>
    </header>
    <param_list>
        <param>
            <name>Enable_Rcv_Queue_Manage</name>
            <value>false</value>
        </param>
        <param>
            <name>Expansion_ROM_Size</name>
            <item>2</item>
            <item>4</item>
            <item>8</item>
            <item>16</item>
            <item>32</item>
            <item>64</item>
            <item>128</item>
            <item>256</item>
            <item>512</item>
            <value>2</value>
        </param>
        <param>
            <name>Base_Class_Code</name>
            <value>05</value>
        </param>
        <param>
            <name>MSIx_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>ROM_BAR_ENABLED</name>
            <value>false</value>
        </param>
        <param>
            <name>BAR1_Enable</name>
            <value>true</value>
        </param>
        <param>
            <name>BAR2_Type</name>
            <item>32bit Memory</item>
            <item>64bit Prefetchable Memory</item>
            <item>64bit Non-Prefetchable Memory</item>
            <value>32bit Memory</value>
        </param>
        <param>
            <name>BAR0_Type</name>
            <item>32bit Memory</item>
            <item>64bit Prefetchable Memory</item>
            <item>64bit Non-Prefetchable Memory</item>
            <value>32bit Memory</value>
        </param>
        <param>
            <name>BAR3_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>Max_Payload_Size</name>
            <value>1024 Bytes</value>
        </param>
        <param>
            <name>TPH_Cmplt_Support</name>
            <value>00</value>
        </param>
        <param>
            <name>BAR0_TYPE_PAR</name>
            <value>2'd0</value>
        </param>
        <param>
            <name>Axis_Slave_Num</name>
            <value>3</value>
        </param>
        <param>
            <name>BAR0_MEM_IO</name>
            <value>1'b0</value>
        </param>
        <param>
            <name>TX_POST_CURSOR_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>BAR4_PREFETCH</name>
            <value>1'b0</value>
        </param>
        <param>
            <name>NUM_OF_LANES</name>
            <value>5'b1</value>
        </param>
        <param>
            <name>Table_BIR</name>
            <item>BAR0</item>
            <item>BAR1</item>
            <value>BAR0</value>
        </param>
        <param>
            <name>BAR5_MASK_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>BAR3_Size</name>
            <item>256</item>
            <item>512</item>
            <value>256</value>
        </param>
        <param>
            <name>Expansion_ROM_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>PRE_CURSOR_EMPHASIS</name>
            <value>0</value>
        </param>
        <param>
            <name>BAR2_TYPE_PAR</name>
            <value>2'd0</value>
        </param>
        <param>
            <name>BAR5_MEM_IO</name>
            <value>1'b0</value>
        </param>
        <param>
            <name>BAR1_Type</name>
            <item>32bit Memory</item>
            <value>32bit Memory</value>
        </param>
        <param>
            <name>BAR0_PREFETCH</name>
            <value>1'b0</value>
        </param>
        <param>
            <name>Cpl_Timeout_Ports</name>
            <value>false</value>
        </param>
        <param>
            <name>Subsystem_ID</name>
            <value>0000</value>
        </param>
        <param>
            <name>Error_Handling_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>Table_BIR_Value</name>
            <value>3'd0</value>
        </param>
        <param>
            <name>Extended_Tag_Default</name>
            <value>true</value>
        </param>
        <param>
            <name>MSI_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>BAR0_Enable</name>
            <value>true</value>
        </param>
        <param>
            <name>RCB</name>
            <value>128 byte</value>
        </param>
        <param>
            <name>INT_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>Programming_Interface</name>
            <value>00</value>
        </param>
        <param>
            <name>Table_Size</name>
            <value>0x1</value>
        </param>
        <param>
            <name>BAR2_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>Vendor_ID</name>
            <value>0755</value>
        </param>
        <param>
            <name>Reference_Clk</name>
            <value>100 MHz</value>
        </param>
        <param>
            <name>BAR3_MEM_IO</name>
            <value>1'b0</value>
        </param>
        <param>
            <name>MAX_LINK_WIDTH</name>
            <value>6'd2</value>
        </param>
        <param>
            <name>MSI_MULTIPLE_MSG_CAP</name>
            <value>3'd0</value>
        </param>
        <param>
            <name>BAR5_Type</name>
            <value>32bit Memory</value>
        </param>
        <param>
            <name>Interrupt_Pin</name>
            <value>INTA</value>
        </param>
        <param>
            <name>BAR1_MEM_IO</name>
            <value>1'b0</value>
        </param>
        <param>
            <name>LINK_CAPABLE</name>
            <value>6'd3</value>
        </param>
        <param>
            <name>BAR1_Size</name>
            <item>1</item>
            <item>2</item>
            <item>4</item>
            <item>8</item>
            <item>16</item>
            <item>32</item>
            <item>64</item>
            <item>128</item>
            <item>256</item>
            <item>512</item>
            <value>4</value>
        </param>
        <param>
            <name>BAR4_Size</name>
            <item>256</item>
            <item>512</item>
            <value>256</value>
        </param>
        <param>
            <name>BAR4_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>BAR3_Size_Unit</name>
            <item>Bytes</item>
            <item>Kilobytes</item>
            <item>Megabytes</item>
            <item>Gigabytes</item>
            <value>Bytes</value>
        </param>
        <param>
            <name>RCB_Value</name>
            <value>1'b1</value>
        </param>
        <param>
            <name>BAR2_MASK</name>
            <value>31'h0</value>
        </param>
        <param>
            <name>DEV_TYPE</name>
            <value>3'b000</value>
        </param>
        <param>
            <name>Per_Vector_Masking_Capable</name>
            <value>false</value>
        </param>
        <param>
            <name>ECRC_Gen</name>
            <value>false</value>
        </param>
        <param>
            <name>POST_CURSOR_EMPHASIS</name>
            <value>12</value>
        </param>
        <param>
            <name>BAR2_Size_Unit</name>
            <item>Bytes</item>
            <item>Kilobytes</item>
            <item>Megabytes</item>
            <item>Gigabytes</item>
            <value>Bytes</value>
        </param>
        <param>
            <name>BAR2_Size</name>
            <item>256</item>
            <item>512</item>
            <value>256</value>
        </param>
        <param>
            <name>DLL_Active_Rep_Cap</name>
            <value>false</value>
        </param>
        <param>
            <name>BAR1_MASK</name>
            <value>31'h1fffff</value>
        </param>
        <param>
            <name>Hot_Rst_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>INTX_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>DYN_Cfg_PCIe</name>
            <value>true</value>
        </param>
        <param>
            <name>PBA_Offset</name>
            <value>0x0</value>
        </param>
        <param>
            <name>Disable_Scrambling</name>
            <value>false</value>
        </param>
        <param>
            <name>Subsystem_Vendor_ID</name>
            <value>0000</value>
        </param>
        <param>
            <name>BAR5_MASK</name>
            <value>31'h0</value>
        </param>
        <param>
            <name>BAR3_Type</name>
            <value>32bit Memory</value>
        </param>
        <param>
            <name>Table_Offset</name>
            <value>0x0</value>
        </param>
        <param>
            <name>BAR0_Size_Unit</name>
            <item>Bytes</item>
            <item>Kilobytes</item>
            <item>Megabytes</item>
            <item>Gigabytes</item>
            <value>Kilobytes</value>
        </param>
        <param>
            <name>Unlock_Message_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>BAR0_MASK</name>
            <value>31'h7fff</value>
        </param>
        <param>
            <name>BAR5_Size</name>
            <item>256</item>
            <item>512</item>
            <value>256</value>
        </param>
        <param>
            <name>BAR1_MASK_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>PBA_BIR</name>
            <item>BAR0</item>
            <item>BAR1</item>
            <value>BAR0</value>
        </param>
        <param>
            <name>Enable_CfgOut_Ports</name>
            <value>true</value>
        </param>
        <param>
            <name>MAX_LINK_SPEED</name>
            <value>4'd2</value>
        </param>
        <param>
            <name>Target_Link_Speed_Value</name>
            <value>4'h2</value>
        </param>
        <param>
            <name>TX_PRE_CURSOR_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>Multiple_Message_Capable</name>
            <value>1 Vector</value>
        </param>
        <param>
            <name>Sub_Class_Code</name>
            <value>80</value>
        </param>
        <param>
            <name>BAR4_MASK</name>
            <value>31'h0</value>
        </param>
        <param>
            <name>BAR5_Size_Unit</name>
            <item>Bytes</item>
            <item>Kilobytes</item>
            <item>Megabytes</item>
            <item>Gigabytes</item>
            <value>Bytes</value>
        </param>
        <param>
            <name>MAX_PAYLOAD_SIZE_PAR</name>
            <value>3'd3</value>
        </param>
        <param>
            <name>Maximum_Link_Speed</name>
            <value>5 GT/s</value>
        </param>
        <param>
            <name>BAR4_TYPE_PAR</name>
            <value>2'd0</value>
        </param>
        <param>
            <name>BAR2_MEM_IO</name>
            <value>1'b0</value>
        </param>
        <param>
            <name>Table_Size_Value</name>
            <value>1</value>
        </param>
        <param>
            <name>Expansion_ROM_Size_Unit</name>
            <value>Kilobytes</value>
        </param>
        <param>
            <name>HW_AUTO_SPEED_DISABLE</name>
            <value>false</value>
        </param>
        <param>
            <name>CRS</name>
            <value>false</value>
        </param>
        <param>
            <name>Power_Management_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>PBA_Offset_Value</name>
            <value>0</value>
        </param>
        <param>
            <name>RX_EQ_ENABLE</name>
            <value>true</value>
        </param>
        <param>
            <name>BAR3_MASK_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>Revision_ID</name>
            <value>00</value>
        </param>
        <param>
            <name>ROM_MASK</name>
            <value>31'h0</value>
        </param>
        <param>
            <name>Maximum_Link_Width</name>
            <value>X2</value>
        </param>
        <param>
            <name>BAR4_Size_Unit</name>
            <item>Bytes</item>
            <item>Kilobytes</item>
            <item>Megabytes</item>
            <item>Gigabytes</item>
            <value>Bytes</value>
        </param>
        <param>
            <name>BAR3_MASK</name>
            <value>31'h0</value>
        </param>
        <param>
            <name>Cplq_Management_Enable</name>
            <value>true</value>
        </param>
        <param>
            <name>ECRC_Check</name>
            <value>true</value>
        </param>
        <param>
            <name>BAR0_Size</name>
            <item>1</item>
            <item>2</item>
            <item>4</item>
            <item>8</item>
            <item>16</item>
            <item>32</item>
            <item>64</item>
            <item>128</item>
            <item>256</item>
            <item>512</item>
            <value>64</value>
        </param>
        <param>
            <name>Upconfigure_Capable</name>
            <value>true</value>
        </param>
        <param>
            <name>Enable_Lane_Reversal</name>
            <value>false</value>
        </param>
        <param>
            <name>BAR1_Size_Unit</name>
            <item>Bytes</item>
            <item>Kilobytes</item>
            <item>Megabytes</item>
            <item>Gigabytes</item>
            <value>Megabytes</value>
        </param>
        <param>
            <name>Atomic_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>MSI_PIN_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>POST1_CURSOR_EMPHASIS</name>
            <value>19</value>
        </param>
        <param>
            <name>PBA_BIR_Value</name>
            <value>3'd0</value>
        </param>
        <param>
            <name>BAR4_Type</name>
            <value>32bit Memory</value>
        </param>
        <param>
            <name>BAR4_MEM_IO</name>
            <value>1'b0</value>
        </param>
        <param>
            <name>Table_Offset_Value</name>
            <value>0</value>
        </param>
        <param>
            <name>Enable_Debug_Share_Ports</name>
            <value>true</value>
        </param>
        <param>
            <name>BAR5_Enable</name>
            <value>false</value>
        </param>
        <param>
            <name>Device_Type</name>
            <value>PCI Express Endpoint</value>
        </param>
        <param>
            <name>Target_Link_Speed</name>
            <value>5 GT/s</value>
        </param>
        <param>
            <name>MSI_64_Address_Capable</name>
            <value>false</value>
        </param>
        <param>
            <name>Device_ID</name>
            <value>0755</value>
        </param>
        <param>
            <name>Enable_Debug_Ports</name>
            <value>true</value>
        </param>
        <param>
            <name>Extended_Tag_Field</name>
            <value>true</value>
        </param>
        <param>
            <name>Enable_Credit_Ports</name>
            <value>false</value>
        </param>
        <param>
            <name>BAR2_PREFETCH</name>
            <value>1'b0</value>
        </param>
    </param_list>
    <pin_list>
        <pin>
            <name>pclk</name>
            <text>pclk</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>pclk_div2</name>
            <text>pclk_div2</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>ref_clk</name>
            <text>ref_clk</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>ref_clk_n</name>
            <text>ref_clk_n</text>
            <dir>input</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>ref_clk_p</name>
            <text>ref_clk_p</text>
            <dir>input</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>button_rst_n</name>
            <text>button_rst_n</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>power_up_rst_n</name>
            <text>power_up_rst_n</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>perst_n</name>
            <text>perst_n</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>core_rst_n</name>
            <text>core_rst_n</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>smlh_link_up</name>
            <text>smlh_link_up</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>rdlh_link_up</name>
            <text>rdlh_link_up</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>smlh_ltssm_state</name>
            <text>smlh_ltssm_state</text>
            <dir>output</dir>
            <pos>left</pos>
            <msb>4</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>p_sel</name>
            <text>p_sel</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>p_strb</name>
            <text>p_strb</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>p_addr</name>
            <text>p_addr</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>15</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>p_wdata</name>
            <text>p_wdata</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>31</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>p_ce</name>
            <text>p_ce</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>p_we</name>
            <text>p_we</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>p_rdy</name>
            <text>p_rdy</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>p_rdata</name>
            <text>p_rdata</text>
            <dir>output</dir>
            <pos>left</pos>
            <msb>31</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>rxn</name>
            <text>rxn</text>
            <dir>input</dir>
            <pos>right</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>rxp</name>
            <text>rxp</text>
            <dir>input</dir>
            <pos>right</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>txn</name>
            <text>txn</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>txp</name>
            <text>txp</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>pcs_nearend_loop</name>
            <text>pcs_nearend_loop</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>pma_nearend_ploop</name>
            <text>pma_nearend_ploop</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>pma_nearend_sloop</name>
            <text>pma_nearend_sloop</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axis_master_tvalid</name>
            <text>axis_master_tvalid</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_master_tready</name>
            <text>axis_master_tready</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_master_tdata</name>
            <text>axis_master_tdata</text>
            <dir>output</dir>
            <pos>left</pos>
            <msb>127</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axis_master_tkeep</name>
            <text>axis_master_tkeep</text>
            <dir>output</dir>
            <pos>left</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axis_master_tlast</name>
            <text>axis_master_tlast</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_master_tuser</name>
            <text>axis_master_tuser</text>
            <dir>output</dir>
            <pos>left</pos>
            <msb>7</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axis_slave0_tready</name>
            <text>axis_slave0_tready</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_slave0_tvalid</name>
            <text>axis_slave0_tvalid</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_slave0_tdata</name>
            <text>axis_slave0_tdata</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>127</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axis_slave0_tlast</name>
            <text>axis_slave0_tlast</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_slave0_tuser</name>
            <text>axis_slave0_tuser</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_slave1_tready</name>
            <text>axis_slave1_tready</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_slave1_tvalid</name>
            <text>axis_slave1_tvalid</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_slave1_tdata</name>
            <text>axis_slave1_tdata</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>127</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axis_slave1_tlast</name>
            <text>axis_slave1_tlast</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_slave1_tuser</name>
            <text>axis_slave1_tuser</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_slave2_tready</name>
            <text>axis_slave2_tready</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_slave2_tvalid</name>
            <text>axis_slave2_tvalid</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_slave2_tdata</name>
            <text>axis_slave2_tdata</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>127</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>axis_slave2_tlast</name>
            <text>axis_slave2_tlast</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>axis_slave2_tuser</name>
            <text>axis_slave2_tuser</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>pm_xtlh_block_tlp</name>
            <text>pm_xtlh_block_tlp</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>cfg_send_cor_err_mux</name>
            <text>cfg_send_cor_err_mux</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>cfg_send_nf_err_mux</name>
            <text>cfg_send_nf_err_mux</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>cfg_send_f_err_mux</name>
            <text>cfg_send_f_err_mux</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>cfg_sys_err_rc</name>
            <text>cfg_sys_err_rc</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>cfg_aer_rc_err_mux</name>
            <text>cfg_aer_rc_err_mux</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>radm_cpl_timeout</name>
            <text>radm_cpl_timeout</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>cfg_max_rd_req_size</name>
            <text>cfg_max_rd_req_size</text>
            <dir>output</dir>
            <pos>bottom</pos>
            <msb>2</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>cfg_bus_master_en</name>
            <text>cfg_bus_master_en</text>
            <dir>output</dir>
            <pos>bottom</pos>
        </pin>
        <pin>
            <name>cfg_max_payload_size</name>
            <text>cfg_max_payload_size</text>
            <dir>output</dir>
            <pos>bottom</pos>
            <msb>2</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>cfg_ext_tag_en</name>
            <text>cfg_ext_tag_en</text>
            <dir>output</dir>
            <pos>bottom</pos>
        </pin>
        <pin>
            <name>cfg_rcb</name>
            <text>cfg_rcb</text>
            <dir>output</dir>
            <pos>bottom</pos>
        </pin>
        <pin>
            <name>cfg_mem_space_en</name>
            <text>cfg_mem_space_en</text>
            <dir>output</dir>
            <pos>bottom</pos>
        </pin>
        <pin>
            <name>cfg_pm_no_soft_rst</name>
            <text>cfg_pm_no_soft_rst</text>
            <dir>output</dir>
            <pos>bottom</pos>
        </pin>
        <pin>
            <name>cfg_crs_sw_vis_en</name>
            <text>cfg_crs_sw_vis_en</text>
            <dir>output</dir>
            <pos>bottom</pos>
        </pin>
        <pin>
            <name>cfg_no_snoop_en</name>
            <text>cfg_no_snoop_en</text>
            <dir>output</dir>
            <pos>bottom</pos>
        </pin>
        <pin>
            <name>cfg_relax_order_en</name>
            <text>cfg_relax_order_en</text>
            <dir>output</dir>
            <pos>bottom</pos>
        </pin>
        <pin>
            <name>cfg_tph_req_en</name>
            <text>cfg_tph_req_en</text>
            <dir>output</dir>
            <pos>bottom</pos>
            <msb>1</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>cfg_pf_tph_st_mode</name>
            <text>cfg_pf_tph_st_mode</text>
            <dir>output</dir>
            <pos>bottom</pos>
            <msb>2</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>cfg_pbus_num</name>
            <text>cfg_pbus_num</text>
            <dir>output</dir>
            <pos>bottom</pos>
            <msb>7</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>cfg_pbus_dev_num</name>
            <text>cfg_pbus_dev_num</text>
            <dir>output</dir>
            <pos>bottom</pos>
            <msb>4</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>rbar_ctrl_update</name>
            <text>rbar_ctrl_update</text>
            <dir>output</dir>
            <pos>bottom</pos>
        </pin>
        <pin>
            <name>cfg_atomic_req_en</name>
            <text>cfg_atomic_req_en</text>
            <dir>output</dir>
            <pos>bottom</pos>
        </pin>
        <pin>
            <name>radm_idle</name>
            <text>radm_idle</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>radm_q_not_empty</name>
            <text>radm_q_not_empty</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>radm_qoverflow</name>
            <text>radm_qoverflow</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>diag_ctrl_bus</name>
            <text>diag_ctrl_bus</text>
            <dir>input</dir>
            <pos>top</pos>
            <msb>1</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>dyn_debug_info_sel</name>
            <text>dyn_debug_info_sel</text>
            <dir>input</dir>
            <pos>top</pos>
            <msb>3</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>cfg_link_auto_bw_mux</name>
            <text>cfg_link_auto_bw_mux</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>cfg_bw_mgt_mux</name>
            <text>cfg_bw_mgt_mux</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>cfg_pme_mux</name>
            <text>cfg_pme_mux</text>
            <dir>output</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>debug_info_mux</name>
            <text>debug_info_mux</text>
            <dir>output</dir>
            <pos>top</pos>
            <msb>132</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>app_ras_des_sd_hold_ltssm</name>
            <text>app_ras_des_sd_hold_ltssm</text>
            <dir>input</dir>
            <pos>top</pos>
        </pin>
        <pin>
            <name>app_ras_des_tba_ctrl</name>
            <text>app_ras_des_tba_ctrl</text>
            <dir>input</dir>
            <pos>top</pos>
            <msb>1</msb>
            <lsb>0</lsb>
        </pin>
    </pin_list>
    <synthesis>
        <script><![CDATA[set_option -vlog_std v2001]]></script>
        <script><![CDATA[set_option -disable_io_insertion 1]]></script>
    </synthesis>
    <file_list>
        <output>
            <file pathname="generate.log" format="log" description="Generate Log"/>
            <file pathname="example_design/bench/pango_pcie_top_tb.v" format="verilog" description="Compiled File"/>
            <file pathname="example_design/bench/pango_pcie_top.v" format="verilog" description="Compiled File"/>
            <file pathname="example_design/bench/pango_pcie_top_sim.v" format="verilog" description="Compiled File"/>
            <file pathname="example_design/bench/ips2l_pcie_wrap_v1_8_sim.v" format="verilog" description="Compiled File"/>
            <file pathname="pcie_test_tmpl.v" format="verilog" description="Instantiation Template"/>
            <file pathname="pcie_test_tmpl.vhdl" format="vhdl" description="Instantiation Template"/>
        </output>
        <source>
            <file pathname="rtl/ips2l_pcie_apb_cross_v1_0.v"/>
            <file pathname="rtl/ips2l_pcie_apb_mux_v1_0.v"/>
            <file pathname="rtl/ips2l_pcie_apb2dbi_v1_1.v"/>
            <file pathname="rtl/ips2l_pcie_cfg_init_v1_7.v"/>
            <file pathname="rtl/ips2l_pcie_hard_ctrl_v1_8.v"/>
            <file pathname="rtl/ips2l_pcie_pll_v1_0.v"/>
            <file pathname="rtl/ips2l_pcie_soft_phy_v1_3.v"/>
            <file pathname="rtl/ips2l_pcie_top_v1_8.v"/>
            <file pathname="rtl/ips2l_pcie_seio_intf_v1_2.v"/>
            <file pathname="rtl/external_ram/rcv_data_ram/rcv_data_ram.v"/>
            <file pathname="rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v"/>
            <file pathname="rtl/external_ram/rcv_header_ram/rcv_header_ram.v"/>
            <file pathname="rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v"/>
            <file pathname="rtl/external_ram/retry_data_ram/retry_data_ram.v"/>
            <file pathname="rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v"/>
            <file pathname="rtl/hsst_pipe/hsst_rst_cross_sync_v1_0.v"/>
            <file pathname="rtl/hsst_pipe/hsst_rst_debounce_v1_0.v"/>
            <file pathname="rtl/hsst_pipe/hsst_rst_sync_v1_0.v"/>
            <file pathname="rtl/hsst_pipe/hsst_rst_wtchdg_v1_0.v"/>
            <file pathname="rtl/hsst_pipe/hsstl_phy_mac_rdata_proc.v"/>
            <file pathname="rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v"/>
            <file pathname="rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_fsm_v1_0.v"/>
            <file pathname="rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v"/>
            <file pathname="rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v"/>
            <file pathname="rtl/hsst_pipe/hsstl_rst4mcrsw_tx_rst_fsm_v1_1.v"/>
            <file pathname="rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v"/>
            <file pathname="rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v"/>
            <file pathname="rtl/hsst_pipe/ips_hsst_rst_sync_v1_0.v"/>
            <file pathname="rtl/hsstlp/ipm2l_pcie_hsstlp_x1_top.v"/>
            <file pathname="rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v"/>
            <file pathname="rtl/hsstlp/ipm2l_pcie_hsstlp_x4_top.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_apb_bridge_v1_2.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_fifo_clr_v1_3.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_pll_rst_fsm_v1_0.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_debounce_v1_0.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_pll_v1_0.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_rx_v1_6.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_sync_v1_0.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_tx_v1_6.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_v1_6.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_wtchdg_v1_0.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rxlane_rst_fsm_v1_6.v"/>
            <file pathname="rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_txlane_rst_fsm_v1_6.v"/>
            <file pathname="pcie_test.v"/>
        </source>
    </file_list>
</ip_inst>
