##### Written on 2025/11/07 01:34:13 ###############################


##### INFO ##################################################

Current device : 
	PG2L50H-6FBG484

Top Module : 
	pcie_dma_test

Constraint File(s) : 
	F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc

##### SUMMARY ######################################################

Found 0 error(s), 22 critical warning(s), 11 warning(s), out of 650 constraint(s)


Inapplicable constraints(except overwritten constraints):
********************************************

define_attribute {p:button_rst_n} {PAP_IO_LOC} {M15}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 18)] | Port button_rst_n has been placed at location M15, whose type is share pin.

define_attribute {p:perst_n} {PAP_IO_LOC} {M16}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 40)] | Port perst_n has been placed at location M16, whose type is share pin.

define_attribute {p:i2c_sda} {PAP_IO_LOC} {R19}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 49)] | Port i2c_sda has been placed at location R19, whose type is share pin.

define_attribute {p:i2c_scl} {PAP_IO_LOC} {P19}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 56)] | Port i2c_scl has been placed at location P19, whose type is share pin.

define_attribute {p:cmos1_data[7]} {PAP_IO_LOC} {AB21}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 72)] | Port cmos1_data[7] has been placed at location AB21, whose type is share pin.

define_attribute {p:cmos1_data[5]} {PAP_IO_LOC} {AB22}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 82)] | Port cmos1_data[5] has been placed at location AB22, whose type is share pin.

define_attribute {p:cmos1_data[4]} {PAP_IO_LOC} {L13}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 87)] | Port cmos1_data[4] has been placed at location L13, whose type is share pin.

define_attribute {p:cmos1_data[2]} {PAP_IO_LOC} {AB20}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 97)] | Port cmos1_data[2] has been placed at location AB20, whose type is share pin.

define_attribute {p:cmos1_data[1]} {PAP_IO_LOC} {AA19}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 102)] | Port cmos1_data[1] has been placed at location AA19, whose type is share pin.

define_attribute {p:cmos2_data[7]} {PAP_IO_LOC} {AB18}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 112)] | Port cmos2_data[7] has been placed at location AB18, whose type is share pin.

define_attribute {p:cmos2_data[6]} {PAP_IO_LOC} {P17}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 117)] | Port cmos2_data[6] has been placed at location P17, whose type is share pin.

define_attribute {p:cmos2_data[3]} {PAP_IO_LOC} {P15}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 132)] | Port cmos2_data[3] has been placed at location P15, whose type is share pin.

define_attribute {p:cmos2_data[2]} {PAP_IO_LOC} {R16}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 137)] | Port cmos2_data[2] has been placed at location R16, whose type is share pin.

define_attribute {p:cmos2_data[0]} {PAP_IO_LOC} {U17}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 147)] | Port cmos2_data[0] has been placed at location U17, whose type is share pin.

define_attribute {p:cmos1_scl} {PAP_IO_LOC} {R14}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 152)] | Port cmos1_scl has been placed at location R14, whose type is share pin.

define_attribute {p:cmos1_sda} {PAP_IO_LOC} {P14}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 159)] | Port cmos1_sda has been placed at location P14, whose type is share pin.

define_attribute {p:cmos2_reset} {PAP_IO_LOC} {AA21}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 187)] | Port cmos2_reset has been placed at location AA21, whose type is share pin.

define_attribute {p:cmos1_pclk} {PAP_IO_LOC} {T18}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 199)] | Port cmos1_pclk has been placed at location T18, whose type is share pin.

define_attribute {p:cmos1_vsync} {PAP_IO_LOC} {W17}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 204)] | Port cmos1_vsync has been placed at location W17, whose type is share pin.

define_attribute {p:cmos2_href} {PAP_IO_LOC} {U18}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 209)] | Port cmos2_href has been placed at location U18, whose type is share pin.

define_attribute {p:cmos2_pclk} {PAP_IO_LOC} {P16}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 214)] | Port cmos2_pclk has been placed at location P16, whose type is share pin.

define_attribute {p:cmos2_vsync} {PAP_IO_LOC} {R17}
	C: ConstraintEditor-2002: [F:/rknn2/pcie_test/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 219)] | Port cmos2_vsync has been placed at location R17, whose type is share pin.


Constraints with issues:
********************************************


Issues without commands:
********************************************


Unconstrained ports:
********************************************

W: ConstraintEditor-4019: Port Bus 'eth_rgmii_rxd_0' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'eth_rgmii_txd_0' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'rxn' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'rxp' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'txn' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'txp' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'eth_rgmii_rx_ctl_0' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'eth_rgmii_rxc_0' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'eth_rgmii_tx_ctl_0' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'eth_rgmii_txc_0' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'eth_rst_n_0' unspecified I/O constraint.

Constraints with matching wildcard expressions:
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