
----------------------------------------------------------------------------------------------------
| Tool Version : Fabric Compiler (version 2022.2-SP6.4 <build 146967>)
| Date         : Wed Jan  8 10:15:06 2025
| Design       : test_ddr
| Device       : PG2L50H
| Speed Grade  : -6
| Package      : FBG484
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
| Timing Models: Production
| Tcl Command  : report_timing -configuration 
----------------------------------------------------------------------------------------------------

Timing analysis mode : multi corner

 Clock Summary:                                                                                                                                                                                                     
********************************************************************************************************************************************************************************************************************
                                                                                      Clock   Non-clock                                                                                                             
 Clock                    Period       Waveform            Type                       Loads       Loads  Sources                                                                                                    
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 ref_clk                  40.0000      {0.0000 20.0000}    Declared                     577          15  {free_clk}                                                                                                 
   rst_clk                40.0000      {0.0000 20.0000}    Generated (ref_clk)          124          37  {I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0}                                         
   ddrphy_sysclk          7.6190       {0.0000 3.8090}     Generated (ref_clk)         3367         248  {I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0}                                          
   phy_dq_clk_0           0.9524       {0.0000 0.4760}     Generated (ref_clk)           35           1  {I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY}         
     phy_dq_sysclk_0      7.6190       {1.9040 5.7140}     Generated (phy_dq_clk_0)      35           0  {I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT} 
   phy_dq_clk_1           0.9524       {0.0000 0.4760}     Generated (ref_clk)           42           1  {I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY}         
     phy_dq_sysclk_1      7.6190       {1.9040 5.7140}     Generated (phy_dq_clk_1)      42           0  {I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT} 
====================================================================================================================================================================================================================

 Clock Groups:                                                                                      
****************************************************************************************************
 Clock Group                   Group Type                 Clocks                                    
----------------------------------------------------------------------------------------------------
 ref_clk                       asynchronous               ref_clk                                   
 rst_clk                       asynchronous               rst_clk                                   
 phy_dq_clk_0                  asynchronous               phy_dq_clk_0                              
 phy_dq_clk_1                  asynchronous               phy_dq_clk_1                              
====================================================================================================

 Performance Summary:                                                                               
****************************************************************************************************
                              Requested       Estimated      Requested      Estimated               
 Clock                        Frequency       Frequency      Period         Period             Slack
----------------------------------------------------------------------------------------------------
 ref_clk                    25.0000 MHz    196.0016 MHz        40.0000         5.1020         34.898
 rst_clk                    25.0000 MHz    193.0129 MHz        40.0000         5.1810         34.819
 ddrphy_sysclk             131.2500 MHz    165.3155 MHz         7.6190         6.0490          1.570
====================================================================================================

Design Summary : All Constraints Met.

Setup Summary(Slow Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                     34.898       0.000              0           1373
 rst_clk                rst_clk                     34.819       0.000              0            560
 ddrphy_sysclk          ddrphy_sysclk                1.570       0.000              0          13370
 phy_dq_sysclk_1        ddrphy_sysclk                2.267       0.000              0            130
 phy_dq_sysclk_0        ddrphy_sysclk                3.756       0.000              0              1
 ddrphy_sysclk          phy_dq_sysclk_0              1.635       0.000              0            196
 ddrphy_sysclk          phy_dq_sysclk_1              1.263       0.000              0            210
====================================================================================================

Hold Summary(Slow Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                      0.180       0.000              0           1373
 rst_clk                rst_clk                      0.173       0.000              0            560
 ddrphy_sysclk          ddrphy_sysclk                0.144       0.000              0          13370
 phy_dq_sysclk_1        ddrphy_sysclk                0.556       0.000              0            130
 phy_dq_sysclk_0        ddrphy_sysclk                0.763       0.000              0              1
 ddrphy_sysclk          phy_dq_sysclk_0              0.448       0.000              0            196
 ddrphy_sysclk          phy_dq_sysclk_1              0.481       0.000              0            210
====================================================================================================

Recovery Summary(Slow Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                     37.389       0.000              0            575
 rst_clk                rst_clk                     37.236       0.000              0            122
 ddrphy_sysclk          ddrphy_sysclk                4.332       0.000              0           3340
====================================================================================================

Removal Summary(Slow Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                      0.358       0.000              0            575
 rst_clk                rst_clk                      0.363       0.000              0            122
 ddrphy_sysclk          ddrphy_sysclk                0.387       0.000              0           3340
====================================================================================================

Minimum Pulse Width Summary(Slow Corner):
****************************************************************************************************
                                                                         WPWS Failing     WPWS Total
 Clock                                            WPWS(ns)    TPWS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                                            19.800       0.000              0            576
 rst_clk                                            19.800       0.000              0            123
 ddrphy_sysclk                                       3.609       0.000              0           3366
 phy_dq_clk_0                                        0.011       0.000              0             35
 phy_dq_sysclk_0                                     1.659       0.000              0             35
 phy_dq_clk_1                                        0.011       0.000              0             42
 phy_dq_sysclk_1                                     2.209       0.000              0             42
====================================================================================================

Setup Summary(Fast Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                     37.057       0.000              0           1373
 rst_clk                rst_clk                     36.860       0.000              0            560
 ddrphy_sysclk          ddrphy_sysclk                4.072       0.000              0          13370
 phy_dq_sysclk_1        ddrphy_sysclk                4.222       0.000              0            130
 phy_dq_sysclk_0        ddrphy_sysclk                4.978       0.000              0              1
 ddrphy_sysclk          phy_dq_sysclk_0              3.855       0.000              0            196
 ddrphy_sysclk          phy_dq_sysclk_1              3.582       0.000              0            210
====================================================================================================

Hold Summary(Fast Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                      0.116       0.000              0           1373
 rst_clk                rst_clk                      0.105       0.000              0            560
 ddrphy_sysclk          ddrphy_sysclk                0.101       0.000              0          13370
 phy_dq_sysclk_1        ddrphy_sysclk                0.101       0.000              0            130
 phy_dq_sysclk_0        ddrphy_sysclk                0.192       0.000              0              1
 ddrphy_sysclk          phy_dq_sysclk_0              0.101       0.000              0            196
 ddrphy_sysclk          phy_dq_sysclk_1              0.101       0.000              0            210
====================================================================================================

Recovery Summary(Fast Corner):
****************************************************************************************************
                                                                          TNS Failing      TNS Total
 Launch Clock           Capture Clock              WNS(ns)     TNS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                     38.385       0.000              0            575
 rst_clk                rst_clk                     38.285       0.000              0            122
 ddrphy_sysclk          ddrphy_sysclk                5.565       0.000              0           3340
====================================================================================================

Removal Summary(Fast Corner):
****************************************************************************************************
                                                                          THS Failing      THS Total
 Launch Clock           Capture Clock              WHS(ns)     THS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                ref_clk                      0.234       0.000              0            575
 rst_clk                rst_clk                      0.232       0.000              0            122
 ddrphy_sysclk          ddrphy_sysclk                0.253       0.000              0           3340
====================================================================================================

Minimum Pulse Width Summary(Fast Corner):
****************************************************************************************************
                                                                         WPWS Failing     WPWS Total
 Clock                                            WPWS(ns)    TPWS(ns)      Endpoints      Endpoints
----------------------------------------------------------------------------------------------------
 ref_clk                                            19.800       0.000              0            576
 rst_clk                                            19.800       0.000              0            123
 ddrphy_sysclk                                       3.609       0.000              0           3366
 phy_dq_clk_0                                        0.011       0.000              0             35
 phy_dq_sysclk_0                                     1.659       0.000              0             35
 phy_dq_clk_1                                        0.011       0.000              0             42
 phy_dq_sysclk_1                                     2.209       0.000              0             42
====================================================================================================

Slow Corner
****************************************************************************************************
====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[0]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.193  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.356
  Launch Clock Delay      :  3.899
  Clock Pessimism Removal :  0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.468       3.899         _N127            
 CLMS_159_355/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMS_159_355/CR1                  tco                   0.240       4.139 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      1.505       5.644         uart_read_addr[4]
 CLMA_231_324/Y3                   td                    0.217       5.861 r       u_uart_rd_lock/N214_37[9]_1/LUT6D_inst_perm/L6
                                   net (fanout=32)       1.064       6.925         _N41114          
 CLMS_177_379/CR2                  td                    0.231       7.156 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N262/LUT6D_inst_perm/L5
                                   net (fanout=31)       1.364       8.520         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N330
 CLMA_219_300/CE                                                           r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[0]/opit_0_inv/CE

 Data arrival time                                                   8.520         Logic Levels: 2  
                                                                                   Logic: 0.688ns(14.889%), Route: 3.933ns(85.111%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_190/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_5/CLKOUT
                                   net (fanout=57)       0.413      43.356         _N128            
 CLMA_219_300/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[0]/opit_0_inv/CLK
 clock pessimism                                         0.350      43.706                          
 clock uncertainty                                      -0.050      43.656                          

 Setup time                                             -0.238      43.418                          

 Data required time                                                 43.418                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.418                          
 Data arrival time                                                   8.520                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        34.898                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[1]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.193  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.356
  Launch Clock Delay      :  3.899
  Clock Pessimism Removal :  0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.468       3.899         _N127            
 CLMS_159_355/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMS_159_355/CR1                  tco                   0.240       4.139 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      1.505       5.644         uart_read_addr[4]
 CLMA_231_324/Y3                   td                    0.217       5.861 r       u_uart_rd_lock/N214_37[9]_1/LUT6D_inst_perm/L6
                                   net (fanout=32)       1.064       6.925         _N41114          
 CLMS_177_379/CR2                  td                    0.231       7.156 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N262/LUT6D_inst_perm/L5
                                   net (fanout=31)       1.364       8.520         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N330
 CLMA_219_300/CE                                                           r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[1]/opit_0_inv/CE

 Data arrival time                                                   8.520         Logic Levels: 2  
                                                                                   Logic: 0.688ns(14.889%), Route: 3.933ns(85.111%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_190/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_5/CLKOUT
                                   net (fanout=57)       0.413      43.356         _N128            
 CLMA_219_300/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[1]/opit_0_inv/CLK
 clock pessimism                                         0.350      43.706                          
 clock uncertainty                                      -0.050      43.656                          

 Setup time                                             -0.238      43.418                          

 Data required time                                                 43.418                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.418                          
 Data arrival time                                                   8.520                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        34.898                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[2]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.193  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.356
  Launch Clock Delay      :  3.899
  Clock Pessimism Removal :  0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.468       3.899         _N127            
 CLMS_159_355/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMS_159_355/CR1                  tco                   0.240       4.139 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      1.505       5.644         uart_read_addr[4]
 CLMA_231_324/Y3                   td                    0.217       5.861 r       u_uart_rd_lock/N214_37[9]_1/LUT6D_inst_perm/L6
                                   net (fanout=32)       1.064       6.925         _N41114          
 CLMS_177_379/CR2                  td                    0.231       7.156 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N262/LUT6D_inst_perm/L5
                                   net (fanout=31)       1.364       8.520         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N330
 CLMA_219_300/CE                                                           r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[2]/opit_0_inv/CE

 Data arrival time                                                   8.520         Logic Levels: 2  
                                                                                   Logic: 0.688ns(14.889%), Route: 3.933ns(85.111%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_190/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_5/CLKOUT
                                   net (fanout=57)       0.413      43.356         _N128            
 CLMA_219_300/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[2]/opit_0_inv/CLK
 clock pessimism                                         0.350      43.706                          
 clock uncertainty                                      -0.050      43.656                          

 Setup time                                             -0.238      43.418                          

 Data required time                                                 43.418                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.418                          
 Data arrival time                                                   8.520                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        34.898                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b3[5]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[29]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.212  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.891
  Launch Clock Delay      :  3.329
  Clock Pessimism Removal :  -0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.386       3.329         _N129            
 CLMA_171_396/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b3[5]/opit_0_inv/CLK

 CLMA_171_396/Q1                   tco                   0.166       3.495 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b3[5]/opit_0_inv/Q
                                   net (fanout=14)       0.272       3.767         u_ips2l_uart_ctrl/u_uart_ctrl/data [29]
 CLMS_159_397/BD                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[29]/opit_0_inv/D

 Data arrival time                                                   3.767         Logic Levels: 0  
                                                                                   Logic: 0.166ns(37.900%), Route: 0.272ns(62.100%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.460       3.891         _N127            
 CLMS_159_397/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[29]/opit_0_inv/CLK
 clock pessimism                                        -0.350       3.541                          
 clock uncertainty                                       0.000       3.541                          

 Hold time                                               0.046       3.587                          

 Data required time                                                  3.587                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.587                          
 Data arrival time                                                   3.767                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.180                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[7]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.212  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.893
  Launch Clock Delay      :  3.331
  Clock Pessimism Removal :  -0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.388       3.331         _N129            
 CLMA_171_384/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[7]/opit_0_inv/CLK

 CLMA_171_384/Q1                   tco                   0.166       3.497 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[7]/opit_0_inv/Q
                                   net (fanout=14)       0.272       3.769         u_ips2l_uart_ctrl/u_uart_ctrl/data [15]
 CLMS_159_385/BD                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/D

 Data arrival time                                                   3.769         Logic Levels: 0  
                                                                                   Logic: 0.166ns(37.900%), Route: 0.272ns(62.100%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.462       3.893         _N127            
 CLMS_159_385/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/CLK
 clock pessimism                                        -0.350       3.543                          
 clock uncertainty                                       0.000       3.543                          

 Hold time                                               0.046       3.589                          

 Data required time                                                  3.589                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.589                          
 Data arrival time                                                   3.769                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.180                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b0[2]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[2]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.220  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.916
  Launch Clock Delay      :  3.346
  Clock Pessimism Removal :  -0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.403       3.346         _N129            
 CLMA_195_324/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b0[2]/opit_0_inv/CLK

 CLMA_195_324/Q2                   tco                   0.166       3.512 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b0[2]/opit_0_inv/Q
                                   net (fanout=14)       0.286       3.798         u_ips2l_uart_ctrl/u_uart_ctrl/data [2]
 CLMA_213_301/BD                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[2]/opit_0_inv/D

 Data arrival time                                                   3.798         Logic Levels: 0  
                                                                                   Logic: 0.166ns(36.726%), Route: 0.286ns(63.274%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_190/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_5/CLKOUT
                                   net (fanout=57)       0.485       3.916         _N128            
 CLMA_213_301/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[2]/opit_0_inv/CLK
 clock pessimism                                        -0.350       3.566                          
 clock uncertainty                                       0.000       3.566                          

 Hold time                                               0.046       3.612                          

 Data required time                                                  3.612                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.612                          
 Data arrival time                                                   3.798                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.186                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/tran_err_rst_cnt[3]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/I1
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.083  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.660
  Launch Clock Delay      :  5.513
  Clock Pessimism Removal :  0.770

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.480       5.513         _N132            
 CLMS_195_307/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/tran_err_rst_cnt[3]/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_195_307/Q0                   tco                   0.213       5.726 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/tran_err_rst_cnt[3]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=5)        0.594       6.320         dbg_tran_err_rst_cnt[2]
 CLMA_183_306/Y1                   td                    0.240       6.560 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N161_1_3/LUT6_inst_perm/L6
                                   net (fanout=2)        0.282       6.842         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N46507
 CLMA_177_306/Y0                   td                    0.188       7.030 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_9/gateop_perm/L6
                                   net (fanout=3)        0.429       7.459         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N39912
 CLMA_171_319/Y0                   td                    0.240       7.699 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_106/gateop_perm/L6
                                   net (fanout=2)        1.077       8.776         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N41888
 CLMA_219_403/CR1                  td                    0.222       8.998 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N260_8[6]/gateop_LUT6DL5_perm/L5
                                   net (fanout=1)        1.183      10.181         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N48
 CLMA_171_336/A1                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/I1

 Data arrival time                                                  10.181         Logic Levels: 4  
                                                                                   Logic: 1.103ns(23.629%), Route: 3.565ns(76.371%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.397      44.660         _N132            
 CLMA_171_336/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/CLK
 clock pessimism                                         0.770      45.430                          
 clock uncertainty                                      -0.150      45.280                          

 Setup time                                             -0.280      45.000                          

 Data required time                                                 45.000                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 45.000                          
 Data arrival time                                                  10.181                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        34.819                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_L6Q_perm/I0
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.663
  Launch Clock Delay      :  5.506
  Clock Pessimism Removal :  0.843

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.473       5.506         _N134            
 CLMS_159_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_325/Q1                   tco                   0.213       5.719 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=7)        0.608       6.327         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [2]
 CLMS_159_319/Y2                   td                    0.235       6.562 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_111/LUT6_inst_perm/L6
                                   net (fanout=8)        0.750       7.312         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N41325
 CLMA_159_330/Y0                   td                    0.078       7.390 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N357_7/LUT6_inst_perm/L6
                                   net (fanout=1)        0.752       8.142         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N8214
 CLMS_159_319/Y1                   td                    0.240       8.382 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N357_11_3/gateop_perm/L6
                                   net (fanout=6)        0.286       8.668         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N8215
 CLMS_159_325/C0                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_L6Q_perm/I0

 Data arrival time                                                   8.668         Logic Levels: 3  
                                                                                   Logic: 0.766ns(24.225%), Route: 2.396ns(75.775%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.400      44.663         _N134            
 CLMS_159_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.843      45.506                          
 clock uncertainty                                      -0.150      45.356                          

 Setup time                                             -0.286      45.070                          

 Data required time                                                 45.070                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 45.070                          
 Data arrival time                                                   8.668                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        36.402                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_L6Q_perm/I2
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.663
  Launch Clock Delay      :  5.506
  Clock Pessimism Removal :  0.843

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.473       5.506         _N134            
 CLMS_159_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_325/Q1                   tco                   0.213       5.719 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=7)        0.608       6.327         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [2]
 CLMS_159_319/Y2                   td                    0.235       6.562 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_111/LUT6_inst_perm/L6
                                   net (fanout=8)        0.750       7.312         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N41325
 CLMA_159_330/Y0                   td                    0.078       7.390 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N357_7/LUT6_inst_perm/L6
                                   net (fanout=1)        0.752       8.142         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N8214
 CLMS_159_319/Y1                   td                    0.240       8.382 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N357_11_3/gateop_perm/L6
                                   net (fanout=6)        0.286       8.668         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N8215
 CLMS_159_325/D2                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_L6Q_perm/I2

 Data arrival time                                                   8.668         Logic Levels: 3  
                                                                                   Logic: 0.766ns(24.225%), Route: 2.396ns(75.775%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.400      44.663         _N134            
 CLMS_159_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.843      45.506                          
 clock uncertainty                                      -0.150      45.356                          

 Setup time                                             -0.228      45.128                          

 Data required time                                                 45.128                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 45.128                          
 Data arrival time                                                   8.668                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        36.460                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gate_start_d[2]/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L6Q_perm/I5
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.210  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.506
  Launch Clock Delay      :  4.664
  Clock Pessimism Removal :  -0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.401       4.664         _N134            
 CLMA_159_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gate_start_d[2]/opit_0_inv/CLK

 CLMA_159_318/Q1                   tco                   0.166       4.830 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gate_start_d[2]/opit_0_inv/Q
                                   net (fanout=2)        0.198       5.028         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gate_start_d [2]
 CLMA_171_318/A5                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L6Q_perm/I5

 Data arrival time                                                   5.028         Logic Levels: 0  
                                                                                   Logic: 0.166ns(45.604%), Route: 0.198ns(54.396%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.473       5.506         _N132            
 CLMA_171_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                        -0.632       4.874                          
 clock uncertainty                                       0.000       4.874                          

 Hold time                                              -0.019       4.855                          

 Data required time                                                  4.855                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.855                          
 Data arrival time                                                   5.028                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.173                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/opit_0_inv_L6QL5Q_perm/I4
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.210  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.507
  Launch Clock Delay      :  4.665
  Clock Pessimism Removal :  -0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.402       4.665         _N134            
 CLMS_159_313/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_313/Q0                   tco                   0.166       4.831 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=5)        0.199       5.030         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg [1]
 CLMA_171_313/A4                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/opit_0_inv_L6QL5Q_perm/I4

 Data arrival time                                                   5.030         Logic Levels: 0  
                                                                                   Logic: 0.166ns(45.479%), Route: 0.199ns(54.521%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.474       5.507         _N132            
 CLMA_171_313/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                        -0.632       4.875                          
 clock uncertainty                                       0.000       4.875                          

 Hold time                                              -0.029       4.846                          

 Data required time                                                  4.846                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.846                          
 Data arrival time                                                   5.030                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.184                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/ddrphy_cpd_start_d0/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[3]/opit_0_inv_L6Q_perm/I3
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.208  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.509
  Launch Clock Delay      :  4.669
  Clock Pessimism Removal :  -0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_171/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=17)       0.406       4.669         _N133            
 CLMS_153_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/ddrphy_cpd_start_d0/opit_0_inv_srl/CLK

 CLMS_153_301/CR1                  tco                   0.183       4.852 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/ddrphy_cpd_start_d0/opit_0_inv_srl/CR0
                                   net (fanout=2)        0.173       5.025         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/ddrphy_cpd_start_d1
 CLMS_153_313/B3                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[3]/opit_0_inv_L6Q_perm/I3

 Data arrival time                                                   5.025         Logic Levels: 0  
                                                                                   Logic: 0.183ns(51.404%), Route: 0.173ns(48.596%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.476       5.509         _N134            
 CLMS_153_313/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[3]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                        -0.632       4.877                          
 clock uncertainty                                       0.000       4.877                          

 Hold time                                              -0.041       4.836                          

 Data required time                                                  4.836                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.836                          
 Data arrival time                                                   5.025                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.189                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L6QL5Q_perm/I2
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.184  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.354
  Launch Clock Delay      :  5.792
  Clock Pessimism Removal :  1.254

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.459       5.792         _N124            
 CLMA_201_426/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK

 CLMA_201_426/CR1                  tco                   0.264       6.056 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/L5Q
                                   net (fanout=3)        1.619       7.675         I_ips_ddr_top/u_ddrphy_top/dbg_slice_status [31]
 CLMA_261_348/CR1                  td                    0.301       7.976 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_fsm[3:0]_37_or[1]_1/gateop_LUT6DL5_perm/L5
                                   net (fanout=4)        0.413       8.389         I_ips_ddr_top/u_ddrphy_top/wrlvl_dqs_resp
 CLMA_261_354/Y1                   td                    0.113       8.502 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/dbg_wrlvl_4_or[0]_4/LUT6_inst_perm/L6
                                   net (fanout=1)        0.749       9.251         I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N48291
 CLMA_261_306/Y1                   td                    0.188       9.439 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=7)        0.672      10.111         debug_calib_ctrl[18]
 CLMS_255_283/Y1                   td                    0.188      10.299 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[0]/opit_0_inv_L6Q_perm/L6
                                   net (fanout=8)        0.975      11.274         I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N144
 CLMA_285_235/A2                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L6QL5Q_perm/I2

 Data arrival time                                                  11.274         Logic Levels: 4  
                                                                                   Logic: 1.054ns(19.227%), Route: 4.428ns(80.773%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.413      11.973         _N123            
 CLMA_285_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                         1.254      13.227                          
 clock uncertainty                                      -0.150      13.077                          

 Setup time                                             -0.233      12.844                          

 Data required time                                                 12.844                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.844                          
 Data arrival time                                                  11.274                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.570                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CE
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.097  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.333
  Launch Clock Delay      :  5.822
  Clock Pessimism Removal :  1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.489       5.822         _N124            
 CLMA_261_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/CLK

 CLMA_261_318/Q3                   tco                   0.213       6.035 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=8)        1.650       7.685         I_ips_ddr_top/u_ddrphy_top/wrlvl_dqs_req
 CLMA_195_438/Y1                   td                    0.240       7.925 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L6Q_perm/L6
                                   net (fanout=2)        1.179       9.104         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/_N27
 CLMA_213_355/Y2                   td                    0.101       9.205 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=6)        0.661       9.866         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_next_state [1]
 CLMA_201_421/Y3                   td                    0.101       9.967 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/L6
                                   net (fanout=14)       0.765      10.732         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N370
 CLMA_201_397/Y2                   td                    0.113      10.845 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N478/LUT6_inst_perm/L6
                                   net (fanout=6)        0.410      11.255         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N478
 CLMA_207_396/CE                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CE

 Data arrival time                                                  11.255         Logic Levels: 4  
                                                                                   Logic: 0.768ns(14.136%), Route: 4.665ns(85.864%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.392      11.952         _N124            
 CLMA_207_396/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CLK
 clock pessimism                                         1.392      13.344                          
 clock uncertainty                                      -0.150      13.194                          

 Setup time                                             -0.238      12.956                          

 Data required time                                                 12.956                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.956                          
 Data arrival time                                                  11.255                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.701                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[2]/opit_0_inv_L6QL5Q_perm/CE
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -0.097  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.333
  Launch Clock Delay      :  5.822
  Clock Pessimism Removal :  1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.489       5.822         _N124            
 CLMA_261_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/CLK

 CLMA_261_318/Q3                   tco                   0.213       6.035 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=8)        1.650       7.685         I_ips_ddr_top/u_ddrphy_top/wrlvl_dqs_req
 CLMA_195_438/Y1                   td                    0.240       7.925 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L6Q_perm/L6
                                   net (fanout=2)        1.179       9.104         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/_N27
 CLMA_213_355/Y2                   td                    0.101       9.205 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=6)        0.661       9.866         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_next_state [1]
 CLMA_201_421/Y3                   td                    0.101       9.967 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/L6
                                   net (fanout=14)       0.765      10.732         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N370
 CLMA_201_397/Y2                   td                    0.113      10.845 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N478/LUT6_inst_perm/L6
                                   net (fanout=6)        0.410      11.255         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N478
 CLMS_207_397/CE                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[2]/opit_0_inv_L6QL5Q_perm/CE

 Data arrival time                                                  11.255         Logic Levels: 4  
                                                                                   Logic: 0.768ns(14.136%), Route: 4.665ns(85.864%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.392      11.952         _N124            
 CLMS_207_397/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[2]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                         1.392      13.344                          
 clock uncertainty                                      -0.150      13.194                          

 Setup time                                             -0.238      12.956                          

 Data required time                                                 12.956                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.956                          
 Data arrival time                                                  11.255                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.701                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[3]/opit_0_inv_32X2DL6QL5Q/WADDR[0]
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.070  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.801
  Launch Clock Delay      :  4.339
  Clock Pessimism Removal :  -1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.398       4.339         _N123            
 CLMA_213_222/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK

 CLMA_213_222/CR1                  tco                   0.183       4.522 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/L5Q
                                   net (fanout=23)       0.271       4.793         I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
 CLMS_207_211/D0                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[3]/opit_0_inv_32X2DL6QL5Q/WADDR[0]

 Data arrival time                                                   4.793         Logic Levels: 0  
                                                                                   Logic: 0.183ns(40.308%), Route: 0.271ns(59.692%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.468       5.801         _N123            
 CLMS_207_211/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[3]/opit_0_inv_32X2DL6QL5Q/CLK
 clock pessimism                                        -1.392       4.409                          
 clock uncertainty                                       0.000       4.409                          

 Hold time                                               0.240       4.649                          

 Data required time                                                  4.649                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.649                          
 Data arrival time                                                   4.793                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.144                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/WADDR[0]
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.070  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.801
  Launch Clock Delay      :  4.339
  Clock Pessimism Removal :  -1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.398       4.339         _N123            
 CLMA_213_222/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK

 CLMA_213_222/CR1                  tco                   0.183       4.522 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/L5Q
                                   net (fanout=23)       0.271       4.793         I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
 CLMS_207_211/D0                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/WADDR[0]

 Data arrival time                                                   4.793         Logic Levels: 0  
                                                                                   Logic: 0.183ns(40.308%), Route: 0.271ns(59.692%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.468       5.801         _N123            
 CLMS_207_211/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/CLK
 clock pessimism                                        -1.392       4.409                          
 clock uncertainty                                       0.000       4.409                          

 Hold time                                               0.240       4.649                          

 Data required time                                                  4.649                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.649                          
 Data arrival time                                                   4.793                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.144                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[41]/opit_0_inv_32X2DL6QL5Q/WADDR[0]
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    0.070  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.801
  Launch Clock Delay      :  4.339
  Clock Pessimism Removal :  -1.392

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.398       4.339         _N123            
 CLMA_213_222/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK

 CLMA_213_222/CR1                  tco                   0.183       4.522 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/L5Q
                                   net (fanout=23)       0.271       4.793         I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
 CLMS_207_211/D0                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[41]/opit_0_inv_32X2DL6QL5Q/WADDR[0]

 Data arrival time                                                   4.793         Logic Levels: 0  
                                                                                   Logic: 0.183ns(40.308%), Route: 0.271ns(59.692%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.468       5.801         _N123            
 CLMS_207_211/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[41]/opit_0_inv_32X2DL6QL5Q/CLK
 clock pessimism                                        -1.392       4.409                          
 clock uncertainty                                       0.000       4.409                          

 Hold time                                               0.240       4.649                          

 Data required time                                                  4.649                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.649                          
 Data arrival time                                                   4.793                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.144                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[40]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    1.258  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.346
  Launch Clock Delay      :  3.345
  Clock Pessimism Removal :  0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.227       5.249         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_438/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_438/RX_DATA[0]          tco                   0.449       5.698 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/RX_DATA[0]
                                   net (fanout=1)        0.662       6.360         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [40]
 CLMS_279_433/CR3                  td                    0.119       6.479 r       CLKROUTE_106/CR  
                                   net (fanout=1)        1.042       7.521         _N112            
 CLMS_273_415/CR3                  td                    0.119       7.640 r       CLKROUTE_107/CR  
                                   net (fanout=1)        1.731       9.371         _N113            
 CLMA_261_378/M3                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[40]/opit_0_inv_srl/D

 Data arrival time                                                   9.371         Logic Levels: 2  
                                                                                   Logic: 0.687ns(16.667%), Route: 3.435ns(83.333%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.405      11.965         _N124            
 CLMA_261_378/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[40]/opit_0_inv_srl/CLK
 clock pessimism                                         0.257      12.222                          
 clock uncertainty                                      -0.550      11.672                          

 Setup time                                             -0.034      11.638                          

 Data required time                                                 11.638                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.638                          
 Data arrival time                                                   9.371                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         2.267                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[44]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    1.259  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.347
  Launch Clock Delay      :  3.345
  Clock Pessimism Removal :  0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.227       5.249         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_438/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_438/RX_DATA[4]          tco                   0.449       5.698 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1/RX_DATA[4]
                                   net (fanout=1)        0.502       6.200         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [44]
 CLMA_285_445/CR3                  td                    0.131       6.331 r       CLKROUTE_108/CR  
                                   net (fanout=1)        1.121       7.452         _N114            
 CLMA_267_384/CR2                  td                    0.120       7.572 r       CLKROUTE_109/CR  
                                   net (fanout=1)        1.606       9.178         _N115            
 CLMA_261_372/M2                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[44]/opit_0_inv_srl/D

 Data arrival time                                                   9.178         Logic Levels: 2  
                                                                                   Logic: 0.700ns(17.816%), Route: 3.229ns(82.184%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.406      11.966         _N124            
 CLMA_261_372/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[44]/opit_0_inv_srl/CLK
 clock pessimism                                         0.257      12.223                          
 clock uncertainty                                      -0.550      11.673                          

 Setup time                                             -0.143      11.530                          

 Data required time                                                 11.530                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.530                          
 Data arrival time                                                   9.178                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         2.352                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[14]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    1.261  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.349
  Launch Clock Delay      :  3.345
  Clock Pessimism Removal :  0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.227       5.249         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_324/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_324/RX_DATA[6]          tco                   0.449       5.698 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/RX_DATA[6]
                                   net (fanout=1)        0.812       6.510         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_rdata [14]
 CLMS_273_307/CR1                  td                    0.122       6.632 r       CLKROUTE_40/CR   
                                   net (fanout=1)        0.681       7.313         _N46             
 CLMS_273_319/CR3                  td                    0.119       7.432 r       CLKROUTE_41/CR   
                                   net (fanout=1)        1.722       9.154         _N47             
 CLMA_237_336/M1                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[14]/opit_0_inv_srl/D

 Data arrival time                                                   9.154         Logic Levels: 2  
                                                                                   Logic: 0.690ns(17.670%), Route: 3.215ns(82.330%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.408      11.968         _N124            
 CLMA_237_336/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[14]/opit_0_inv_srl/CLK
 clock pessimism                                         0.257      12.225                          
 clock uncertainty                                      -0.550      11.675                          

 Setup time                                             -0.143      11.532                          

 Data required time                                                 11.532                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.532                          
 Data arrival time                                                   9.154                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         2.378                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[32]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    2.701  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.810
  Launch Clock Delay      :  2.852
  Clock Pessimism Removal :  -0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    1.002      10.623 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.623         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      10.718 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      10.978         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      11.111 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      11.489         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      11.645 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      12.047         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      12.074 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      12.074         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      12.180 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.195      12.375         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_342/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_342/RX_DATA[0]          tco                   0.272      12.647 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/RX_DATA[0]
                                   net (fanout=1)        1.584      14.231         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_rdata [32]
 CLMA_219_342/M0                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[32]/opit_0_inv_srl/D

 Data arrival time                                                  14.231         Logic Levels: 0  
                                                                                   Logic: 0.272ns(14.655%), Route: 1.584ns(85.345%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.477      13.429         _N124            
 CLMA_219_342/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[32]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.257      13.172                          
 clock uncertainty                                       0.550      13.722                          

 Hold time                                              -0.047      13.675                          

 Data required time                                                 13.675                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 13.675                          
 Data arrival time                                                  14.231                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.556                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[18]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    2.706  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.815
  Launch Clock Delay      :  2.852
  Clock Pessimism Removal :  -0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    1.002      10.623 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.623         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      10.718 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      10.978         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      11.111 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      11.489         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      11.645 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      12.047         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      12.074 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      12.074         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      12.180 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.195      12.375         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_330/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_330/RX_DATA[2]          tco                   0.272      12.647 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/RX_DATA[2]
                                   net (fanout=1)        1.699      14.346         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_rdata [18]
 CLMA_237_336/M3                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[18]/opit_0_inv_srl/D

 Data arrival time                                                  14.346         Logic Levels: 0  
                                                                                   Logic: 0.272ns(13.800%), Route: 1.699ns(86.200%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.482      13.434         _N124            
 CLMA_237_336/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[18]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.257      13.177                          
 clock uncertainty                                       0.550      13.727                          

 Hold time                                               0.045      13.772                          

 Data required time                                                 13.772                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 13.772                          
 Data arrival time                                                  14.346                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.574                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[58]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    2.698  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.807
  Launch Clock Delay      :  2.852
  Clock Pessimism Removal :  -0.257

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    1.002      10.623 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.623         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      10.718 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      10.978         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      11.111 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      11.489         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      11.645 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      12.047         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      12.074 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      12.074         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      12.180 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.195      12.375         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_378/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_378/RX_DATA[2]          tco                   0.272      12.647 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/RX_DATA[2]
                                   net (fanout=1)        1.619      14.266         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_rdata [58]
 CLMA_213_355/M0                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[58]/opit_0_inv_srl/D

 Data arrival time                                                  14.266         Logic Levels: 0  
                                                                                   Logic: 0.272ns(14.384%), Route: 1.619ns(85.616%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.474      13.426         _N124            
 CLMA_213_355/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[58]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.257      13.169                          
 clock uncertainty                                       0.550      13.719                          

 Hold time                                              -0.047      13.672                          

 Data required time                                                 13.672                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 13.672                          
 Data arrival time                                                  14.266                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.594                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
Endpoint    : I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    1.685  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.342
  Launch Clock Delay      :  3.118
  Clock Pessimism Removal :  0.461

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       5.022         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 DDRPHY_CPD_297_4/PPLL_SYSCLK                                              r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY

 DDRPHY_CPD_297_4/CPD_UP_DNB       tco                   0.070       5.092 r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/FLAG_PD
                                   net (fanout=2)        2.249       7.341         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_up_dnb
 CLMA_153_300/CR3                  td                    0.131       7.472 r       CLKROUTE_1/CR    
                                   net (fanout=1)        0.501       7.973         _N7              
 CLMA_171_283/M2                                                           r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D

 Data arrival time                                                   7.973         Logic Levels: 1  
                                                                                   Logic: 0.201ns(6.811%), Route: 2.750ns(93.189%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.401      11.961         _N123            
 CLMA_171_283/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                         0.461      12.422                          
 clock uncertainty                                      -0.550      11.872                          

 Setup time                                             -0.143      11.729                          

 Data required time                                                 11.729                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.729                          
 Data arrival time                                                   7.973                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.756                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
Endpoint    : I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    2.689  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.807
  Launch Clock Delay      :  2.657
  Clock Pessimism Removal :  -0.461

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    1.002      10.623 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.623         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      10.718 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      10.978         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      11.111 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      11.489         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156      11.645 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      12.047         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      12.074 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      12.074         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      12.180 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      12.180         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 DDRPHY_CPD_297_4/PPLL_SYSCLK                                              r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY

 DDRPHY_CPD_297_4/CPD_UP_DNB       tco                   0.078      12.258 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/FLAG_PD
                                   net (fanout=2)        1.575      13.833         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_up_dnb
 CLMA_153_300/CR3                  td                    0.092      13.925 f       CLKROUTE_1/CR    
                                   net (fanout=1)        0.306      14.231         _N7              
 CLMA_171_283/M2                                                           f       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D

 Data arrival time                                                  14.231         Logic Levels: 1  
                                                                                   Logic: 0.170ns(8.289%), Route: 1.881ns(91.711%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.474      13.426         _N123            
 CLMA_171_283/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.461      12.965                          
 clock uncertainty                                       0.550      13.515                          

 Hold time                                              -0.047      13.468                          

 Data required time                                                 13.468                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 13.468                          
 Data arrival time                                                  14.231                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.763                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/TX_DATA[7]
Path Group  : phy_dq_sysclk_0
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.493  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.808
  Clock Pessimism Removal :  0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.475      13.427         _N123            
 CLMA_261_199/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_261_199/Q0                   tco                   0.213      13.640 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        1.260      14.900         debug_data[66]   
 CLMA_285_198/Y0                   td                    0.078      14.978 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       1.074      16.052         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_271/Y0                   td                    0.240      16.292 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_39:32_2[4]/LUT6D_inst_perm/L6
                                   net (fanout=1)        1.606      17.898         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [39]
 IOLHR_292_270/TX_DATA[7]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/TX_DATA[7]

 Data arrival time                                                  17.898         Logic Levels: 2  
                                                                                   Logic: 0.531ns(11.877%), Route: 3.940ns(88.123%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_270/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.461      20.457                          
 clock uncertainty                                      -0.550      19.907                          

 Setup time                                             -0.374      19.533                          

 Data required time                                                 19.533                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.533                          
 Data arrival time                                                  17.898                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.635                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[2].u_outbuft_addr0/opit_1/TX_DATA[7]
Path Group  : phy_dq_sysclk_0
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.493  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.808
  Clock Pessimism Removal :  0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.475      13.427         _N123            
 CLMA_261_199/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_261_199/Q0                   tco                   0.213      13.640 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        1.260      14.900         debug_data[66]   
 CLMA_285_198/Y0                   td                    0.078      14.978 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       0.945      15.923         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_271/Y2                   td                    0.188      16.111 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_15:8_2[4]/LUT6D_inst_perm/L6
                                   net (fanout=6)        1.697      17.808         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [15]
 IOLHR_292_282/TX_DATA[7]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[2].u_outbuft_addr0/opit_1/TX_DATA[7]

 Data arrival time                                                  17.808         Logic Levels: 2  
                                                                                   Logic: 0.479ns(10.934%), Route: 3.902ns(89.066%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_282/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[2].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.461      20.457                          
 clock uncertainty                                      -0.550      19.907                          

 Setup time                                             -0.374      19.533                          

 Data required time                                                 19.533                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.533                          
 Data arrival time                                                  17.808                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.725                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[5].u_outbuft_addr0/opit_1/TX_DATA[1]
Path Group  : phy_dq_sysclk_0
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.493  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.808
  Clock Pessimism Removal :  0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.475      13.427         _N123            
 CLMA_261_199/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_261_199/Q0                   tco                   0.213      13.640 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        1.260      14.900         debug_data[66]   
 CLMA_285_198/Y0                   td                    0.078      14.978 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       0.945      15.923         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_271/Y1                   td                    0.240      16.163 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_47:40_2[1]/LUT6D_inst_perm/L6
                                   net (fanout=2)        1.612      17.775         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [41]
 IOLHR_292_264/TX_DATA[1]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[5].u_outbuft_addr0/opit_1/TX_DATA[1]

 Data arrival time                                                  17.775         Logic Levels: 2  
                                                                                   Logic: 0.531ns(12.213%), Route: 3.817ns(87.787%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_264/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[5].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.461      20.457                          
 clock uncertainty                                      -0.550      19.907                          

 Setup time                                             -0.374      19.533                          

 Data required time                                                 19.533                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.533                          
 Data arrival time                                                  17.775                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.758                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_casn/opit_1/TX_DATA[2]
Path Group  : phy_dq_sysclk_0
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.461  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.349
  Clock Pessimism Removal :  -0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.408       4.349         _N123            
 CLMA_273_222/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_273_222/CR1                  tco                   0.183       4.532 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=7)        0.500       5.032         I_ips_ddr_top/u_ddrphy_top/phy_cas_n [0]
 CLMA_285_157/Y1                   td                    0.082       5.114 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_cas_n_2[1]/LUT6D_inst_perm/L6
                                   net (fanout=2)        0.657       5.771         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_cas_n [1]
 IOLHR_292_108/TX_DATA[2]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_casn/opit_1/TX_DATA[2]

 Data arrival time                                                   5.771         Logic Levels: 1  
                                                                                   Logic: 0.265ns(18.636%), Route: 1.157ns(81.364%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_108/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_casn/opit_1/OCLKDIV
 clock pessimism                                        -0.461       4.792                          
 clock uncertainty                                       0.550       5.342                          

 Hold time                                              -0.019       5.323                          

 Data required time                                                  5.323                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.323                          
 Data arrival time                                                   5.771                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.448                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_rasn/opit_1/TX_DATA[1]
Path Group  : phy_dq_sysclk_0
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.461  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.349
  Clock Pessimism Removal :  -0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.408       4.349         _N123            
 CLMS_267_229/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_267_229/CR1                  tco                   0.183       4.532 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=7)        0.579       5.111         I_ips_ddr_top/u_ddrphy_top/phy_ras_n [0]
 CLMA_285_175/Y2                   td                    0.082       5.193 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_ras_n_2[1]/LUT6D_inst_perm/L6
                                   net (fanout=2)        0.584       5.777         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_ras_n [1]
 IOLHR_292_114/TX_DATA[1]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_rasn/opit_1/TX_DATA[1]

 Data arrival time                                                   5.777         Logic Levels: 1  
                                                                                   Logic: 0.265ns(18.557%), Route: 1.163ns(81.443%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_114/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_rasn/opit_1/OCLKDIV
 clock pessimism                                        -0.461       4.792                          
 clock uncertainty                                       0.550       5.342                          

 Hold time                                              -0.019       5.323                          

 Data required time                                                  5.323                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.323                          
 Data arrival time                                                   5.777                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.454                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/calib_done_r/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/TX_DATA[2]
Path Group  : phy_dq_sysclk_0
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.465  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.353
  Clock Pessimism Removal :  -0.461
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_180/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.412       4.353         _N123            
 CLMA_285_229/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/calib_done_r/opit_0_inv_srl/CLK

 CLMA_285_229/CR0                  tco                   0.182       4.535 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/calib_done_r/opit_0_inv_srl/CR0
                                   net (fanout=20)       0.495       5.030         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r [1]
 CLMA_285_265/CR2                  td                    0.177       5.207 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_39:32_2[0]/LUT6D_inst_perm/L5
                                   net (fanout=2)        0.572       5.779         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [33]
 IOLHR_292_270/TX_DATA[2]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/TX_DATA[2]

 Data arrival time                                                   5.779         Logic Levels: 1  
                                                                                   Logic: 0.359ns(25.175%), Route: 1.067ns(74.825%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_270/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                        -0.461       4.792                          
 clock uncertainty                                       0.550       5.342                          

 Hold time                                              -0.019       5.323                          

 Data required time                                                  5.323                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.323                          
 Data arrival time                                                   5.779                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.456                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/TX_DATA[3]
Path Group  : phy_dq_sysclk_1
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.710  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.821
  Clock Pessimism Removal :  0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.488      13.440         _N124            
 CLMA_261_324/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/CLK

 CLMA_261_324/CR0                  tco                   0.261      13.701 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/L5Q
                                   net (fanout=82)       1.626      15.327         debug_data[67]   
 CLMA_279_444/Y3                   td                    0.188      15.515 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[71]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.288      15.803         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdq [59]
 CLMS_279_463/CR2                  td                    0.120      15.923 r       CLKROUTE_24/CR   
                                   net (fanout=1)        2.143      18.066         _N30             
 IOLHR_292_378/TX_DATA[3]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/TX_DATA[3]

 Data arrival time                                                  18.066         Logic Levels: 2  
                                                                                   Logic: 0.569ns(12.300%), Route: 4.057ns(87.700%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_378/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/OCLKDIV
 clock pessimism                                         0.257      20.253                          
 clock uncertainty                                      -0.550      19.703                          

 Setup time                                             -0.374      19.329                          

 Data required time                                                 19.329                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.329                          
 Data arrival time                                                  18.066                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.263                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[7]
Path Group  : phy_dq_sysclk_1
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.701  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.812
  Clock Pessimism Removal :  0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.479      13.431         _N124            
 CLMA_279_396/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv_L6QQ_perm/CLK

 CLMA_279_396/Q0                   tco                   0.213      13.644 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv_L6QQ_perm/L6Q
                                   net (fanout=10)       1.565      15.209         I_ips_ddr_top/u_ddrphy_top/phy_wrdata_en [1]
 CLMS_279_403/Y1                   td                    0.078      15.287 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/N28[7]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.684      15.971         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdq_en [7]
 CLMA_267_402/CR1                  td                    0.122      16.093 r       CLKROUTE_90/CR   
                                   net (fanout=1)        1.919      18.012         _N96             
 TSERDES_299_309/TS_CTRL[7]                                                r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[7]

 Data arrival time                                                  18.012         Logic Levels: 2  
                                                                                   Logic: 0.413ns(9.015%), Route: 4.168ns(90.985%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 TSERDES_299_309/OCLKDIV                                                   r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/OCLKDIV
 clock pessimism                                         0.257      20.253                          
 clock uncertainty                                      -0.550      19.703                          

 Setup time                                             -0.325      19.378                          

 Data required time                                                 19.378                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.378                          
 Data arrival time                                                  18.012                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.366                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[39]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/TX_DATA[0]
Path Group  : phy_dq_sysclk_1
Path Type   : max (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -2.693  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.854
  Launch Clock Delay      :  5.804
  Clock Pessimism Removal :  0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.173       8.890 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.890         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       9.000 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       9.309         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       9.464 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       9.909         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186      10.095 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473      10.568         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039      10.607 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.607         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130      10.737 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.737         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294      11.031 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791      11.822         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177      11.999 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651      12.650         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302      12.952 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.471      13.423         _N124            
 CLMA_279_438/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[39]/opit_0_inv_L6QQ_perm/CLK

 CLMA_279_438/CR0                  tco                   0.261      13.684 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[39]/opit_0_inv_L6QQ_perm/L6QQ
                                   net (fanout=8)        1.445      15.129         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r [39]
 CLMS_279_439/Y3                   td                    0.217      15.346 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[44]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.752      16.098         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdq [32]
 CLMS_267_475/CR3                  td                    0.119      16.217 r       CLKROUTE_72/CR   
                                   net (fanout=1)        1.730      17.947         _N78             
 IOLHR_292_432/TX_DATA[0]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/TX_DATA[0]

 Data arrival time                                                  17.947         Logic Levels: 2  
                                                                                   Logic: 0.597ns(13.196%), Route: 3.927ns(86.804%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    1.002      18.242 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      18.242         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      18.337 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260      18.597         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133      18.730 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378      19.108         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.156      19.264 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      19.666         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.027      19.693 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      19.693         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.106      19.799 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.197      19.996         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_432/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/OCLKDIV
 clock pessimism                                         0.257      20.253                          
 clock uncertainty                                      -0.550      19.703                          

 Setup time                                             -0.374      19.329                          

 Data required time                                                 19.329                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 19.329                          
 Data arrival time                                                  17.947                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         1.382                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_outbuft_dm/opit_1/TX_DATA[0]
Path Group  : phy_dq_sysclk_1
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.261  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.353
  Clock Pessimism Removal :  -0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.412       4.353         _N124            
 CLMA_285_366/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_srl/CLK

 CLMA_285_366/CR3                  tco                   0.181       4.534 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_srl/CR0
                                   net (fanout=4)        0.380       4.914         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r [0]
 CLMA_285_342/Y1                   td                    0.053       4.967 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[0]/gateop_perm/L6
                                   net (fanout=1)        1.041       6.008         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdata_mask [0]
 IOLHR_292_312/TX_DATA[0]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_outbuft_dm/opit_1/TX_DATA[0]

 Data arrival time                                                   6.008         Logic Levels: 1  
                                                                                   Logic: 0.234ns(14.139%), Route: 1.421ns(85.861%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_312/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_outbuft_dm/opit_1/OCLKDIV
 clock pessimism                                        -0.257       4.996                          
 clock uncertainty                                       0.550       5.546                          

 Hold time                                              -0.019       5.527                          

 Data required time                                                  5.527                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.527                          
 Data arrival time                                                   6.008                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.481                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[12]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_outbuft_dm/opit_1/TX_DATA[2]
Path Group  : phy_dq_sysclk_1
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.260  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.352
  Clock Pessimism Removal :  -0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.411       4.352         _N124            
 CLMA_285_372/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[12]/opit_0_inv_srl/CLK

 CLMA_285_372/CR0                  tco                   0.182       4.534 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[12]/opit_0_inv_srl/CR0
                                   net (fanout=12)       0.247       4.781         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r [6]
 CLMA_285_379/Y1                   td                    0.153       4.934 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[2]/gateop_perm/L6
                                   net (fanout=1)        1.081       6.015         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdata_mask [2]
 IOLHR_292_390/TX_DATA[2]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_outbuft_dm/opit_1/TX_DATA[2]

 Data arrival time                                                   6.015         Logic Levels: 1  
                                                                                   Logic: 0.335ns(20.144%), Route: 1.328ns(79.856%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_390/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_outbuft_dm/opit_1/OCLKDIV
 clock pessimism                                        -0.257       4.996                          
 clock uncertainty                                       0.550       5.546                          

 Hold time                                              -0.019       5.527                          

 Data required time                                                  5.527                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.527                          
 Data arrival time                                                   6.015                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.488                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[18]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/TX_DATA[5]
Path Group  : phy_dq_sysclk_1
Path Type   : min (slow corner)
Path Class  : sequential timing path
Clock Skew  :    -1.250  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.349
  Launch Clock Delay      :  4.342
  Clock Pessimism Removal :  -0.257
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.401       4.342         _N124            
 CLMA_285_427/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[18]/opit_0_inv_L6QQ_perm/CLK

 CLMA_285_427/Q0                   tco                   0.166       4.508 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[18]/opit_0_inv_L6QQ_perm/L6Q
                                   net (fanout=6)        0.248       4.756         I_ips_ddr_top/u_ddrphy_top/phy_wrdata [34]
 CLMA_285_433/Y2                   td                    0.053       4.809 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[33]/LUT6_inst_perm/L6
                                   net (fanout=1)        1.211       6.020         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdq [21]
 IOLHR_292_408/TX_DATA[5]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/TX_DATA[5]

 Data arrival time                                                   6.020         Logic Levels: 1  
                                                                                   Logic: 0.219ns(13.051%), Route: 1.459ns(86.949%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    1.173       3.175 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       3.175         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       3.285 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       3.594         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       3.749 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       4.194         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.186       4.380 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       4.853         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       4.892 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       4.892         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.130       5.022 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.231       5.253         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_408/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/OCLKDIV
 clock pessimism                                        -0.257       4.996                          
 clock uncertainty                                       0.550       5.546                          

 Hold time                                              -0.019       5.527                          

 Data required time                                                  5.527                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  5.527                          
 Data arrival time                                                   6.020                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.493                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[9]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.229  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.331
  Launch Clock Delay      :  3.910
  Clock Pessimism Removal :  0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.479       3.910         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.212       4.122 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      1.310       5.432         free_clk_rst_n   
 CLMA_201_373/RSCO                 td                    0.098       5.530 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[8]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.530         ntR405           
 CLMA_201_379/RSCO                 td                    0.079       5.609 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[9]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.609         ntR404           
 CLMA_201_385/RSCO                 td                    0.079       5.688 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[8]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.688         ntR403           
 CLMA_201_391/RSCO                 td                    0.079       5.767 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[9]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.767         ntR402           
 CLMA_201_397/RSCO                 td                    0.079       5.846 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[11]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.846         ntR401           
 CLMA_201_403/RSCO                 td                    0.079       5.925 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_1[11]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.925         ntR400           
 CLMA_201_409/RSCO                 td                    0.079       6.004 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[30]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       6.004         ntR399           
 CLMA_201_415/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[9]/opit_0_inv/RS

 Data arrival time                                                   6.004         Logic Levels: 7  
                                                                                   Logic: 0.784ns(37.440%), Route: 1.310ns(62.560%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.388      43.331         _N129            
 CLMA_201_415/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[9]/opit_0_inv/CLK
 clock pessimism                                         0.350      43.681                          
 clock uncertainty                                      -0.050      43.631                          

 Recovery time                                          -0.238      43.393                          

 Data required time                                                 43.393                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.393                          
 Data arrival time                                                   6.004                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.389                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[30]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.228  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.332
  Launch Clock Delay      :  3.910
  Clock Pessimism Removal :  0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.479       3.910         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.212       4.122 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      1.310       5.432         free_clk_rst_n   
 CLMA_201_373/RSCO                 td                    0.098       5.530 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[8]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.530         ntR405           
 CLMA_201_379/RSCO                 td                    0.079       5.609 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[9]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.609         ntR404           
 CLMA_201_385/RSCO                 td                    0.079       5.688 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[8]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.688         ntR403           
 CLMA_201_391/RSCO                 td                    0.079       5.767 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[9]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.767         ntR402           
 CLMA_201_397/RSCO                 td                    0.079       5.846 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[11]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.846         ntR401           
 CLMA_201_403/RSCO                 td                    0.079       5.925 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_1[11]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.925         ntR400           
 CLMA_201_409/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[30]/opit_0_inv/RS

 Data arrival time                                                   5.925         Logic Levels: 6  
                                                                                   Logic: 0.705ns(34.988%), Route: 1.310ns(65.012%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.389      43.332         _N129            
 CLMA_201_409/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[30]/opit_0_inv/CLK
 clock pessimism                                         0.350      43.682                          
 clock uncertainty                                      -0.050      43.632                          

 Recovery time                                          -0.238      43.394                          

 Data required time                                                 43.394                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.394                          
 Data arrival time                                                   5.925                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.469                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[27]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.235  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.325
  Launch Clock Delay      :  3.910
  Clock Pessimism Removal :  0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.479       3.910         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.212       4.122 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      0.682       4.804         free_clk_rst_n   
 CLMS_177_349/RSCO                 td                    0.098       4.902 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[23]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       4.902         ntR236           
 CLMS_177_355/RSCO                 td                    0.079       4.981 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[13]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       4.981         ntR235           
 CLMS_177_361/RSCO                 td                    0.079       5.060 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[15]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=1)        0.000       5.060         ntR234           
 CLMS_177_367/RSCO                 td                    0.079       5.139 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_9[13]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.139         ntR233           
 CLMS_177_373/RSCO                 td                    0.079       5.218 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[15]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.218         ntR232           
 CLMS_177_379/RSCO                 td                    0.079       5.297 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[15]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.297         ntR231           
 CLMS_177_385/RSCO                 td                    0.079       5.376 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_9[15]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.376         ntR230           
 CLMS_177_391/RSCO                 td                    0.079       5.455 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[30]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       5.455         ntR229           
 CLMS_177_397/RSCO                 td                    0.079       5.534 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[30]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.534         ntR228           
 CLMS_177_403/RSCO                 td                    0.079       5.613 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b3[6]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       5.613         ntR227           
 CLMS_177_409/RSCO                 td                    0.079       5.692 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_13[30]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       5.692         ntR226           
 CLMS_177_415/RSCO                 td                    0.079       5.771 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[27]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.771         ntR225           
 CLMS_177_421/RSCO                 td                    0.079       5.850 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[27]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       5.850         ntR224           
 CLMS_177_427/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[27]/opit_0_inv/RS

 Data arrival time                                                   5.850         Logic Levels: 13 
                                                                                   Logic: 1.258ns(64.845%), Route: 0.682ns(35.155%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783      41.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150      42.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      42.685         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.258      42.943 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.382      43.325         _N129            
 CLMS_177_427/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[27]/opit_0_inv/CLK
 clock pessimism                                         0.350      43.675                          
 clock uncertainty                                      -0.050      43.625                          

 Recovery time                                          -0.238      43.387                          

 Data required time                                                 43.387                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.387                          
 Data arrival time                                                   5.850                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.537                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[19]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.213  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.911
  Launch Clock Delay      :  3.348
  Clock Pessimism Removal :  -0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.405       3.348         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.182       3.530 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      0.328       3.858         free_clk_rst_n   
 CLMA_147_295/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[19]/opit_0_inv/RS

 Data arrival time                                                   3.858         Logic Levels: 0  
                                                                                   Logic: 0.182ns(35.686%), Route: 0.328ns(64.314%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_170/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_7/CLKOUT
                                   net (fanout=4)        0.480       3.911         _N130            
 CLMA_147_295/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[19]/opit_0_inv/CLK
 clock pessimism                                        -0.350       3.561                          
 clock uncertainty                                       0.000       3.561                          

 Removal time                                           -0.061       3.500                          

 Data required time                                                  3.500                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.500                          
 Data arrival time                                                   3.858                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.358                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[6]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.208  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.906
  Launch Clock Delay      :  3.348
  Clock Pessimism Removal :  -0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.405       3.348         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.182       3.530 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      0.325       3.855         free_clk_rst_n   
 CLMA_177_312/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[6]/opit_0_inv/RS

 Data arrival time                                                   3.855         Logic Levels: 0  
                                                                                   Logic: 0.182ns(35.897%), Route: 0.325ns(64.103%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.475       3.906         _N129            
 CLMA_177_312/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[6]/opit_0_inv/CLK
 clock pessimism                                        -0.350       3.556                          
 clock uncertainty                                       0.000       3.556                          

 Removal time                                           -0.061       3.495                          

 Data required time                                                  3.495                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.495                          
 Data arrival time                                                   3.855                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.360                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_13[19]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.212  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.910
  Launch Clock Delay      :  3.348
  Clock Pessimism Removal :  -0.350

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.783       1.978         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.150       2.128 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       2.685         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.258       2.943 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.405       3.348         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.182       3.530 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      0.346       3.876         free_clk_rst_n   
 CLMA_153_294/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_13[19]/opit_0_inv/RS

 Data arrival time                                                   3.876         Logic Levels: 0  
                                                                                   Logic: 0.182ns(34.470%), Route: 0.346ns(65.530%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.920       2.301         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.177       2.478 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       3.129         free_clk_g       
 HCKB_165_170/CLKOUT               td                    0.302       3.431 r       HCKBROUTE_7/CLKOUT
                                   net (fanout=4)        0.479       3.910         _N130            
 CLMA_153_294/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_13[19]/opit_0_inv/CLK
 clock pessimism                                        -0.350       3.560                          
 clock uncertainty                                       0.000       3.560                          

 Removal time                                           -0.061       3.499                          

 Data required time                                                  3.499                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.499                          
 Data arrival time                                                   3.876                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.377                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv/RS
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.194  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.676
  Launch Clock Delay      :  5.502
  Clock Pessimism Removal :  0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_171/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=17)       0.469       5.502         _N133            
 CLMA_147_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_147_235/CR0                  tco                   0.261       5.763 r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=42)       1.921       7.684         I_ips_ddr_top/u_ddrphy_top/rst_seq_rstn
 CLMA_285_54/RS                                                            r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv/RS

 Data arrival time                                                   7.684         Logic Levels: 0  
                                                                                   Logic: 0.261ns(11.962%), Route: 1.921ns(88.038%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_8/CLKOUT
                                   net (fanout=11)       0.413      44.676         _N131            
 CLMA_285_54/CLK                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv/CLK
 clock pessimism                                         0.632      45.308                          
 clock uncertainty                                      -0.150      45.158                          

 Recovery time                                          -0.238      44.920                          

 Data required time                                                 44.920                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.920                          
 Data arrival time                                                   7.684                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.236                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv/RS
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.194  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.676
  Launch Clock Delay      :  5.502
  Clock Pessimism Removal :  0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_171/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=17)       0.469       5.502         _N133            
 CLMA_147_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_147_235/CR0                  tco                   0.261       5.763 r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=42)       1.733       7.496         I_ips_ddr_top/u_ddrphy_top/rst_seq_rstn
 CLMA_285_360/RS                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv/RS

 Data arrival time                                                   7.496         Logic Levels: 0  
                                                                                   Logic: 0.261ns(13.089%), Route: 1.733ns(86.911%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.413      44.676         _N132            
 CLMA_285_360/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv/CLK
 clock pessimism                                         0.632      45.308                          
 clock uncertainty                                      -0.150      45.158                          

 Recovery time                                          -0.238      44.920                          

 Data required time                                                 44.920                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.920                          
 Data arrival time                                                   7.496                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.424                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[9]/opit_0_inv_AQ_perm/RS
Path Group  : rst_clk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.205  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.668
  Launch Clock Delay      :  5.505
  Clock Pessimism Removal :  0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.472       5.505         _N132            
 CLMA_171_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_171_325/CR1                  tco                   0.214       5.719 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=48)       1.242       6.961         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_69_367/RSCO                  td                    0.098       7.059 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[0]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=4)        0.000       7.059         ntR786           
 CLMA_69_373/RSCO                  td                    0.079       7.138 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[4]/opit_0_inv_AQ_perm/RSCO
                                   net (fanout=4)        0.000       7.138         ntR785           
 CLMA_69_379/RSCO                  td                    0.079       7.217 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[8]/opit_0_inv_AQ_perm/RSCO
                                   net (fanout=1)        0.000       7.217         ntR784           
 CLMA_69_385/RSCI                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[9]/opit_0_inv_AQ_perm/RS

 Data arrival time                                                   7.217         Logic Levels: 3  
                                                                                   Logic: 0.470ns(27.453%), Route: 1.242ns(72.547%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002      41.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      41.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095      41.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597      41.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258      42.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541      42.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033      42.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      43.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150      43.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      44.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.258      44.263 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.405      44.668         _N134            
 CLMA_69_385/CLK                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[9]/opit_0_inv_AQ_perm/CLK
 clock pessimism                                         0.632      45.300                          
 clock uncertainty                                      -0.150      45.150                          

 Recovery time                                          -0.238      44.912                          

 Data required time                                                 44.912                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 44.912                          
 Data arrival time                                                   7.217                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.695                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/RS
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.216  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.510
  Launch Clock Delay      :  4.662
  Clock Pessimism Removal :  -0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.399       4.662         _N132            
 CLMA_171_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_171_325/CR1                  tco                   0.183       4.845 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=48)       0.335       5.180         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_171_301/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/RS

 Data arrival time                                                   5.180         Logic Levels: 0  
                                                                                   Logic: 0.183ns(35.328%), Route: 0.335ns(64.672%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_8/CLKOUT
                                   net (fanout=11)       0.477       5.510         _N131            
 CLMA_171_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.632       4.878                          
 clock uncertainty                                       0.000       4.878                          

 Removal time                                           -0.061       4.817                          

 Data required time                                                  4.817                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.817                          
 Data arrival time                                                   5.180                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.363                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_ack_rst_ctrl/opit_0_inv_srl/RS
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.216  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.510
  Launch Clock Delay      :  4.662
  Clock Pessimism Removal :  -0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.399       4.662         _N132            
 CLMA_171_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_171_325/CR1                  tco                   0.183       4.845 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=48)       0.335       5.180         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_171_301/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_ack_rst_ctrl/opit_0_inv_srl/RS

 Data arrival time                                                   5.180         Logic Levels: 0  
                                                                                   Logic: 0.183ns(35.328%), Route: 0.335ns(64.672%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_8/CLKOUT
                                   net (fanout=11)       0.477       5.510         _N131            
 CLMA_171_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_ack_rst_ctrl/opit_0_inv_srl/CLK
 clock pessimism                                        -0.632       4.878                          
 clock uncertainty                                       0.000       4.878                          

 Removal time                                           -0.061       4.817                          

 Data required time                                                  4.817                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.817                          
 Data arrival time                                                   5.180                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.363                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv_srl/RS
Path Group  : rst_clk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.216  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.510
  Launch Clock Delay      :  4.662
  Clock Pessimism Removal :  -0.632

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.597       1.792         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.258       2.050 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.541       2.591         _N135            
 GPLL_7_157/CLKOUT0                td                    0.033       2.624 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       3.298         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.150       3.448 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       4.005         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.258       4.263 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.399       4.662         _N132            
 CLMA_171_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_171_325/CR1                  tco                   0.183       4.845 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=48)       0.335       5.180         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_171_301/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv_srl/RS

 Data arrival time                                                   5.180         Logic Levels: 0  
                                                                                   Logic: 0.183ns(35.328%), Route: 0.335ns(64.672%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.713       2.094         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.302       2.396 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.649       3.045         _N135            
 GPLL_7_157/CLKOUT0                td                    0.067       3.112 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       3.903         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.177       4.080 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       4.731         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.302       5.033 r       HCKBROUTE_8/CLKOUT
                                   net (fanout=11)       0.477       5.510         _N131            
 CLMA_171_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.632       4.878                          
 clock uncertainty                                       0.000       4.878                          

 Removal time                                           -0.061       4.817                          

 Data required time                                                  4.817                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.817                          
 Data arrival time                                                   5.180                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.363                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[70]/opit_0_inv_L6Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.203  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.333
  Launch Clock Delay      :  5.790
  Clock Pessimism Removal :  1.254

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.457       5.790         _N123            
 CLMA_171_187/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_171_187/CR0                  tco                   0.261       6.051 r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=410)      2.305       8.356         I_ips_ddr_top/ddrc_rstn
 CLMA_255_426/RSCO                 td                    0.093       8.449 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       8.449         ntR559           
 CLMA_255_432/RSCO                 td                    0.072       8.521 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=4)        0.000       8.521         ntR558           
 CLMA_255_438/RSCO                 td                    0.072       8.593 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       8.593         ntR557           
 CLMA_255_444/RSCI                                                         f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[70]/opit_0_inv_L6Q_perm/RS

 Data arrival time                                                   8.593         Logic Levels: 3  
                                                                                   Logic: 0.498ns(17.767%), Route: 2.305ns(82.233%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.392      11.952         _N124            
 CLMA_255_444/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[70]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         1.254      13.206                          
 clock uncertainty                                      -0.150      13.056                          

 Recovery time                                          -0.131      12.925                          

 Data required time                                                 12.925                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.925                          
 Data arrival time                                                   8.593                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.332                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[36]/opit_0_inv_L6Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.203  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.333
  Launch Clock Delay      :  5.790
  Clock Pessimism Removal :  1.254

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.457       5.790         _N123            
 CLMA_171_187/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_171_187/CR0                  tco                   0.261       6.051 r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=410)      2.305       8.356         I_ips_ddr_top/ddrc_rstn
 CLMA_255_426/RSCO                 td                    0.093       8.449 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       8.449         ntR559           
 CLMA_255_432/RSCO                 td                    0.072       8.521 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=4)        0.000       8.521         ntR558           
 CLMA_255_438/RSCO                 td                    0.072       8.593 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       8.593         ntR557           
 CLMA_255_444/RSCI                                                         f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[36]/opit_0_inv_L6Q_perm/RS

 Data arrival time                                                   8.593         Logic Levels: 3  
                                                                                   Logic: 0.498ns(17.767%), Route: 2.305ns(82.233%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.392      11.952         _N124            
 CLMA_255_444/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[36]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         1.254      13.206                          
 clock uncertainty                                      -0.150      13.056                          

 Recovery time                                          -0.131      12.925                          

 Data required time                                                 12.925                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.925                          
 Data arrival time                                                   8.593                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.332                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[38]/opit_0_inv_L6Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : max (slow corner)
Path Class  : async timing path
Clock Skew  :    -0.203  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.333
  Launch Clock Delay      :  5.790
  Clock Pessimism Removal :  1.254

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.457       5.790         _N123            
 CLMA_171_187/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_171_187/CR0                  tco                   0.261       6.051 r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=410)      2.305       8.356         I_ips_ddr_top/ddrc_rstn
 CLMA_255_426/RSCO                 td                    0.093       8.449 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       8.449         ntR559           
 CLMA_255_432/RSCO                 td                    0.072       8.521 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=4)        0.000       8.521         ntR558           
 CLMA_255_438/RSCO                 td                    0.072       8.593 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       8.593         ntR557           
 CLMA_255_444/RSCI                                                         f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[38]/opit_0_inv_L6Q_perm/RS

 Data arrival time                                                   8.593         Logic Levels: 3  
                                                                                   Logic: 0.498ns(17.767%), Route: 2.305ns(82.233%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    1.002       8.719 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.719         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       8.814 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       9.074         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       9.207 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       9.585         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       9.741 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402      10.143         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027      10.170 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      10.170         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106      10.276 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      10.276         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       9.921 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674      10.595         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150      10.745 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557      11.302         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258      11.560 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.392      11.952         _N124            
 CLMA_255_444/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[38]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         1.254      13.206                          
 clock uncertainty                                      -0.150      13.056                          

 Recovery time                                          -0.131      12.925                          

 Data required time                                                 12.925                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.925                          
 Data arrival time                                                   8.593                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.332                          
====================================================================================================

====================================================================================================

Startpoint  : u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK
Endpoint    : heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.214  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.810
  Launch Clock Delay      :  4.342
  Clock Pessimism Removal :  -1.254

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_220/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.401       4.342         _N124            
 CLMA_171_312/CLK                                                          r       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK

 CLMA_171_312/CR0                  tco                   0.182       4.524 f       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/L6QQ
                                   net (fanout=466)      0.358       4.882         core_clk_rst_n   
 CLMA_147_313/RS                                                           f       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/RS

 Data arrival time                                                   4.882         Logic Levels: 0  
                                                                                   Logic: 0.182ns(33.704%), Route: 0.358ns(66.296%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_200/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_3/CLKOUT
                                   net (fanout=29)       0.477       5.810         _N126            
 CLMA_147_313/CLK                                                          r       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/CLK
 clock pessimism                                        -1.254       4.556                          
 clock uncertainty                                       0.000       4.556                          

 Removal time                                           -0.061       4.495                          

 Data required time                                                  4.495                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.495                          
 Data arrival time                                                   4.882                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.387                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_lock/opit_0_inv_L6Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.209  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.807
  Launch Clock Delay      :  4.344
  Clock Pessimism Removal :  -1.254

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_160/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_2/CLKOUT
                                   net (fanout=171)      0.403       4.344         _N125            
 CLMS_153_283/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMS_153_283/CR0                  tco                   0.182       4.526 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=5)        0.363       4.889         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_rstn_synced
 CLMA_171_283/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_lock/opit_0_inv_L6Q_perm/RS

 Data arrival time                                                   4.889         Logic Levels: 0  
                                                                                   Logic: 0.182ns(33.394%), Route: 0.363ns(66.606%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.474       5.807         _N123            
 CLMA_171_283/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_lock/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                        -1.254       4.553                          
 clock uncertainty                                       0.000       4.553                          

 Removal time                                           -0.061       4.492                          

 Data required time                                                  4.492                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.492                          
 Data arrival time                                                   4.889                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.397                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/RS
Path Group  : ddrphy_sysclk
Path Type   : min (slow corner)
Path Class  : async timing path
Clock Skew  :    0.209  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  5.807
  Launch Clock Delay      :  4.344
  Clock Pessimism Removal :  -1.254

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.002       1.100 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.100         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.095       1.195 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.260       1.455         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.133       1.588 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.378       1.966         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.156       2.122 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.402       2.524         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.027       2.551 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.551         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.106       2.657 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       2.657         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                   -0.355       2.302 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.674       2.976         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.150       3.126 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.557       3.683         core_clk         
 HCKB_165_160/CLKOUT               td                    0.258       3.941 r       HCKBROUTE_2/CLKOUT
                                   net (fanout=171)      0.403       4.344         _N125            
 CLMS_153_283/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMS_153_283/CR0                  tco                   0.182       4.526 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd_rstn_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=5)        0.363       4.889         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_rstn_synced
 CLMA_171_283/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/RS

 Data arrival time                                                   4.889         Logic Levels: 0  
                                                                                   Logic: 0.182ns(33.394%), Route: 0.363ns(66.606%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.474       5.807         _N123            
 CLMA_171_283/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                        -1.254       4.553                          
 clock uncertainty                                       0.000       4.553                          

 Removal time                                           -0.061       4.492                          

 Data required time                                                  4.492                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.492                          
 Data arrival time                                                   4.889                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.397                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv/CLK
Endpoint    : err_flag_led (port)
Path Group  : **default**
Path Type   : max (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_220/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.486       5.819         _N124            
 CLMA_243_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv/CLK

 CLMA_243_318/CR1                  tco                   0.264       6.083 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv/Q
                                   net (fanout=5)        0.957       7.040         ddr_init_done    
 CLMA_213_295/Y3                   td                    0.113       7.153 r       N3_4/gateop_perm/L6
                                   net (fanout=1)        2.699       9.852         nt_err_flag_led  
 IOLHR_16_606/DO_P                 td                    0.641      10.493 r       err_flag_led_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000      10.493         err_flag_led_obuf/ntO
 IOBS_0_606/PAD                    td                    1.288      11.781 r       err_flag_led_obuf/opit_0/O
                                   net (fanout=1)        0.039      11.820         err_flag_led     
 J16                                                                       r       err_flag_led (port)

 Data arrival time                                                  11.820         Logic Levels: 3  
                                                                                   Logic: 2.306ns(38.427%), Route: 3.695ns(61.573%)
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/CLK
Endpoint    : mem_rst_n (port)
Path Group  : **default**
Path Type   : max (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_180/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.477       5.810         _N123            
 CLMA_243_229/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/CLK

 CLMA_243_229/CR1                  tco                   0.264       6.074 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/L6QQ
                                   net (fanout=1)        1.131       7.205         I_ips_ddr_top/u_ddrphy_top/calib_rst
 CLMA_255_312/Y2                   td                    0.097       7.302 f       u_axi_bist_top/u_test_rd_ctrl/axi_rdata_d1[0]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=1)        0.715       8.017         nt_mem_rst_n     
 IOLHR_292_300/DO_P                td                    0.641       8.658 f       mem_rst_n_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000       8.658         mem_rst_n_obuf/ntO
 IOBS_300_300/PAD                  td                    0.874       9.532 f       mem_rst_n_obuf/opit_0/O
                                   net (fanout=1)        0.092       9.624         mem_rst_n        
 T3                                                                        f       mem_rst_n (port) 

 Data arrival time                                                   9.624         Logic Levels: 3  
                                                                                   Logic: 1.876ns(49.187%), Route: 1.938ns(50.813%)
====================================================================================================

====================================================================================================

Startpoint  : heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/CLK
Endpoint    : heart_beat_led (port)
Path Group  : **default**
Path Type   : max (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    1.173       1.271 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       1.271         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.110       1.381 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.309       1.690         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.155       1.845 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.445       2.290         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.186       2.476 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.473       2.949         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       2.988 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       2.988         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.130       3.118 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.118         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.294       3.412 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.791       4.203         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.177       4.380 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.651       5.031         core_clk         
 HCKB_165_200/CLKOUT               td                    0.302       5.333 r       HCKBROUTE_3/CLKOUT
                                   net (fanout=29)       0.477       5.810         _N126            
 CLMA_147_313/CLK                                                          r       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/CLK

 CLMA_147_313/Q0                   tco                   0.213       6.023 r       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/L6Q
                                   net (fanout=3)        1.090       7.113         nt_heart_beat_led
 IOLHR_16_306/DO_P                 td                    0.641       7.754 r       heart_beat_led_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000       7.754         heart_beat_led_obuf/ntO
 IOBS_0_306/PAD                    td                    1.288       9.042 r       heart_beat_led_obuf/opit_0/O
                                   net (fanout=1)        0.053       9.095         heart_beat_led   
 M17                                                                       r       heart_beat_led (port)

 Data arrival time                                                   9.095         Logic Levels: 2  
                                                                                   Logic: 2.142ns(65.205%), Route: 1.143ns(34.795%)
====================================================================================================

====================================================================================================

Startpoint  : uart_rxd (port)
Endpoint    : u_ips2l_uart_ctrl/u_uart_top/u_ips2l_seu_uart_rx/rxd_d[0]/opit_0_inv_srl/D
Path Group  : **default**
Path Type   : min (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 M20                                                     0.000       0.000 f       uart_rxd (port)  
                                   net (fanout=1)        0.068       0.068         uart_rxd         
 IOBS_0_384/DIN                    td                    0.678       0.746 f       uart_rxd_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.746         uart_rxd_ibuf/ntD
 IOLHR_16_384/DI_TO_CLK            td                    0.095       0.841 f       uart_rxd_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=1)        0.855       1.696         nt_uart_rxd      
 CLMA_147_378/M0                                                           f       u_ips2l_uart_ctrl/u_uart_top/u_ips2l_seu_uart_rx/rxd_d[0]/opit_0_inv_srl/D

 Data arrival time                                                   1.696         Logic Levels: 2  
                                                                                   Logic: 0.773ns(45.578%), Route: 0.923ns(54.422%)
====================================================================================================

====================================================================================================

Startpoint  : rst_board (port)
Endpoint    : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/RS
Path Group  : **default**
Path Type   : min (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 M15                                                     0.000       0.000 f       rst_board (port) 
                                   net (fanout=1)        0.052       0.052         rst_board        
 IOBD_0_318/DIN                    td                    0.815       0.867 f       rst_board_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.867         rst_board_ibuf/ntD
 IOLHR_16_318/DI_TO_CLK            td                    0.095       0.962 f       rst_board_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=2)        0.825       1.787         nt_rst_board     
 CLMA_147_307/RS                                                           f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/RS

 Data arrival time                                                   1.787         Logic Levels: 2  
                                                                                   Logic: 0.910ns(50.923%), Route: 0.877ns(49.077%)
====================================================================================================

====================================================================================================

Startpoint  : mem_dq[7] (port)
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L6Q_perm/I5
Path Group  : **default**
Path Type   : min (slow corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 N4                                                      0.000       0.000 f       mem_dq[7] (port) 
                                   net (fanout=1)        0.079       0.079         nt_mem_dq[7]     
 IOBD_300_378/DIN                  td                    0.853       0.932 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_0/O
                                   net (fanout=1)        0.000       0.932         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/ntI
 IOLHR_292_378/DI_TO_CLK           td                    0.739       1.671 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/DI_TO_CLK
                                   net (fanout=2)        0.318       1.989         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_in_dly [7]
 CLMA_285_367/B5                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L6Q_perm/I5

 Data arrival time                                                   1.989         Logic Levels: 2  
                                                                                   Logic: 1.592ns(80.040%), Route: 0.397ns(19.960%)
====================================================================================================

{ref_clk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 19.800      20.000          0.200           High Pulse Width  CLMA_147_463/CLK        u_adc_ctrl/dbg_temp_rd_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_147_463/CLK        u_adc_ctrl/dbg_temp_rd_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           High Pulse Width  CLMA_147_462/CLK        u_adc_ctrl/dbg_temp_rd_pos_d[1]/opit_0_inv/CLK
====================================================================================================

{rst_clk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 19.800      20.000          0.200           High Pulse Width  CLMA_171_301/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_171_301/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_69_367/CLK         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[0]/opit_0_inv_L5Q_perm/CLK
====================================================================================================

{ddrphy_sysclk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 3.609       3.809           0.200           High Pulse Width  CLMA_171_187/CLK        I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
 3.609       3.809           0.200           High Pulse Width  CLMS_273_241/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_calib_mux/calib_address[0]/opit_0_inv_L6Q_perm/CLK
 3.609       3.809           0.200           High Pulse Width  CLMS_273_253/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_calib_mux/calib_address[1]/opit_0_inv_L6Q_perm/CLK
====================================================================================================

{phy_dq_clk_0} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 0.011       0.476           0.465           High Pulse Width  DDR_PHY_297_159/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst/CLKA
 0.011       0.476           0.465           Low Pulse Width   DDR_PHY_297_159/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst/CLKA
 0.011       0.476           0.465           High Pulse Width  TSERDES_299_159/SERCLK  I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_tserdes_ca0/oserdes_inst/SERCLK
====================================================================================================

{phy_dq_sysclk_0} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 1.659       3.809           2.150           Low Pulse Width   DDRPHY_CPD_297_4/PPLL_SYSCLK
                                                                                       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
 1.660       3.810           2.150           High Pulse Width  DDRPHY_CPD_297_4/PPLL_SYSCLK
                                                                                       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
 2.209       3.809           1.600           Low Pulse Width   TSERDES_299_159/OCLKDIV I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_tserdes_ca0/oserdes_inst/OCLKDIV
====================================================================================================

{phy_dq_clk_1} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 0.011       0.476           0.465           High Pulse Width  DDR_PHY_297_307/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY/CLKA
 0.011       0.476           0.465           Low Pulse Width   DDR_PHY_297_307/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY/CLKA
 0.011       0.476           0.465           Low Pulse Width   TSERDES_299_308/SERCLK  I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/SERCLK
====================================================================================================

{phy_dq_sysclk_1} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_318/ICLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_318/OCLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/OCLKDIV
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_324/ICLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV
====================================================================================================

====================================================================================================
Fast Corner
****************************************************************************************************
====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[0]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.134  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.124
  Launch Clock Delay      :  2.481
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.303       2.481         _N127            
 CLMS_159_355/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMS_159_355/CR1                  tco                   0.142       2.623 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      0.813       3.436         uart_read_addr[4]
 CLMA_231_313/Y0                   td                    0.070       3.506 f       u_uart_rd_lock/N214_37[9]_2/LUT6D_inst_perm/L6
                                   net (fanout=32)       0.725       4.231         _N41115          
 CLMA_171_372/CR0                  td                    0.182       4.413 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N364/LUT6D_inst_perm/L5
                                   net (fanout=32)       0.755       5.168         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N432
 CLMA_219_306/CE                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[0]/opit_0_inv/CE

 Data arrival time                                                   5.168         Logic Levels: 2  
                                                                                   Logic: 0.394ns(14.663%), Route: 2.293ns(85.337%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.270      42.124         _N129            
 CLMA_219_306/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[0]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.347                          
 clock uncertainty                                      -0.050      42.297                          

 Setup time                                             -0.072      42.225                          

 Data required time                                                 42.225                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.225                          
 Data arrival time                                                   5.168                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.057                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[2]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.134  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.124
  Launch Clock Delay      :  2.481
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.303       2.481         _N127            
 CLMS_159_355/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMS_159_355/CR1                  tco                   0.142       2.623 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      0.813       3.436         uart_read_addr[4]
 CLMA_231_313/Y0                   td                    0.070       3.506 f       u_uart_rd_lock/N214_37[9]_2/LUT6D_inst_perm/L6
                                   net (fanout=32)       0.725       4.231         _N41115          
 CLMA_171_372/CR0                  td                    0.182       4.413 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N364/LUT6D_inst_perm/L5
                                   net (fanout=32)       0.755       5.168         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N432
 CLMA_219_306/CE                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[2]/opit_0_inv/CE

 Data arrival time                                                   5.168         Logic Levels: 2  
                                                                                   Logic: 0.394ns(14.663%), Route: 2.293ns(85.337%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.270      42.124         _N129            
 CLMA_219_306/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[2]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.347                          
 clock uncertainty                                      -0.050      42.297                          

 Setup time                                             -0.072      42.225                          

 Data required time                                                 42.225                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.225                          
 Data arrival time                                                   5.168                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.057                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[3]/opit_0_inv/CE
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.134  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.124
  Launch Clock Delay      :  2.481
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.303       2.481         _N127            
 CLMS_159_355/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/CLK

 CLMS_159_355/CR1                  tco                   0.142       2.623 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/addrl[4]/opit_0_inv/Q
                                   net (fanout=256)      0.813       3.436         uart_read_addr[4]
 CLMA_231_313/Y0                   td                    0.070       3.506 f       u_uart_rd_lock/N214_37[9]_2/LUT6D_inst_perm/L6
                                   net (fanout=32)       0.725       4.231         _N41115          
 CLMA_171_372/CR0                  td                    0.182       4.413 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N364/LUT6D_inst_perm/L5
                                   net (fanout=32)       0.755       5.168         u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/N432
 CLMA_219_306/CE                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[3]/opit_0_inv/CE

 Data arrival time                                                   5.168         Logic Levels: 2  
                                                                                   Logic: 0.394ns(14.663%), Route: 2.293ns(85.337%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.270      42.124         _N129            
 CLMA_219_306/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[3]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.347                          
 clock uncertainty                                      -0.050      42.297                          

 Setup time                                             -0.072      42.225                          

 Data required time                                                 42.225                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.225                          
 Data arrival time                                                   5.168                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.057                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b0[2]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[2]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.158  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.498
  Launch Clock Delay      :  2.117
  Clock Pessimism Removal :  -0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.263       2.117         _N129            
 CLMA_195_324/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b0[2]/opit_0_inv/CLK

 CLMA_195_324/Q2                   tco                   0.103       2.220 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b0[2]/opit_0_inv/Q
                                   net (fanout=14)       0.200       2.420         u_ips2l_uart_ctrl/u_uart_ctrl/data [2]
 CLMA_213_301/BD                                                           r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[2]/opit_0_inv/D

 Data arrival time                                                   2.420         Logic Levels: 0  
                                                                                   Logic: 0.103ns(33.993%), Route: 0.200ns(66.007%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_190/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_5/CLKOUT
                                   net (fanout=57)       0.320       2.498         _N128            
 CLMA_213_301/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[2]/opit_0_inv/CLK
 clock pessimism                                        -0.223       2.275                          
 clock uncertainty                                       0.000       2.275                          

 Hold time                                               0.029       2.304                          

 Data required time                                                  2.304                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.304                          
 Data arrival time                                                   2.420                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.116                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b3[5]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[29]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.150  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.473
  Launch Clock Delay      :  2.100
  Clock Pessimism Removal :  -0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.246       2.100         _N129            
 CLMA_171_396/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b3[5]/opit_0_inv/CLK

 CLMA_171_396/Q1                   tco                   0.109       2.209 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b3[5]/opit_0_inv/Q
                                   net (fanout=14)       0.188       2.397         u_ips2l_uart_ctrl/u_uart_ctrl/data [29]
 CLMS_159_397/BD                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[29]/opit_0_inv/D

 Data arrival time                                                   2.397         Logic Levels: 0  
                                                                                   Logic: 0.109ns(36.700%), Route: 0.188ns(63.300%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.295       2.473         _N127            
 CLMS_159_397/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[29]/opit_0_inv/CLK
 clock pessimism                                        -0.223       2.250                          
 clock uncertainty                                       0.000       2.250                          

 Hold time                                               0.029       2.279                          

 Data required time                                                  2.279                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.279                          
 Data arrival time                                                   2.397                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.118                          
====================================================================================================

====================================================================================================

Startpoint  : u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[7]/opit_0_inv/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/D
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.150  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.475
  Launch Clock Delay      :  2.102
  Clock Pessimism Removal :  -0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.248       2.102         _N129            
 CLMA_171_384/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[7]/opit_0_inv/CLK

 CLMA_171_384/Q1                   tco                   0.109       2.211 f       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b1[7]/opit_0_inv/Q
                                   net (fanout=14)       0.188       2.399         u_ips2l_uart_ctrl/u_uart_ctrl/data [15]
 CLMS_159_385/BD                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/D

 Data arrival time                                                   2.399         Logic Levels: 0  
                                                                                   Logic: 0.109ns(36.700%), Route: 0.188ns(63.300%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.297       2.475         _N127            
 CLMS_159_385/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_8[15]/opit_0_inv/CLK
 clock pessimism                                        -0.223       2.252                          
 clock uncertainty                                       0.000       2.252                          

 Hold time                                               0.029       2.281                          

 Data required time                                                  2.281                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.281                          
 Data arrival time                                                   2.399                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.118                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[0]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/I1
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.165  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.956
  Launch Clock Delay      :  3.564
  Clock Pessimism Removal :  0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_8/CLKOUT
                                   net (fanout=11)       0.320       3.564         _N131            
 CLMA_231_282/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[0]/opit_0_inv_srl/CLK

 CLMA_231_282/CR1                  tco                   0.142       3.706 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[0]/opit_0_inv_srl/CR0
                                   net (fanout=4)        0.649       4.355         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d [1]
 CLMA_177_306/Y0                   td                    0.039       4.394 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_9/gateop_perm/L6
                                   net (fanout=3)        0.243       4.637         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N39912
 CLMA_171_319/Y0                   td                    0.125       4.762 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_106/gateop_perm/L6
                                   net (fanout=2)        0.665       5.427         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N41888
 CLMA_219_403/CR1                  td                    0.131       5.558 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/N260_8[6]/gateop_LUT6DL5_perm/L5
                                   net (fanout=1)        0.698       6.256         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N48
 CLMA_171_336/A1                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/I1

 Data arrival time                                                   6.256         Logic Levels: 3  
                                                                                   Logic: 0.437ns(16.233%), Route: 2.255ns(83.767%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.256      42.956         _N132            
 CLMA_171_336/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9]/opit_0_inv_L6QQ_perm/CLK
 clock pessimism                                         0.443      43.399                          
 clock uncertainty                                      -0.150      43.249                          

 Setup time                                             -0.133      43.116                          

 Data required time                                                 43.116                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.116                          
 Data arrival time                                                   6.256                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        36.860                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_L6Q_perm/I0
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.960
  Launch Clock Delay      :  3.552
  Clock Pessimism Removal :  0.592

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.308       3.552         _N134            
 CLMS_159_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_325/Q1                   tco                   0.125       3.677 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=7)        0.319       3.996         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [2]
 CLMS_159_319/Y2                   td                    0.122       4.118 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_111/LUT6_inst_perm/L6
                                   net (fanout=8)        0.407       4.525         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N41325
 CLMA_159_330/Y0                   td                    0.039       4.564 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N357_7/LUT6_inst_perm/L6
                                   net (fanout=1)        0.420       4.984         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N8214
 CLMS_159_319/Y1                   td                    0.125       5.109 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N357_11_3/gateop_perm/L6
                                   net (fanout=6)        0.160       5.269         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N8215
 CLMS_159_325/C0                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_L6Q_perm/I0

 Data arrival time                                                   5.269         Logic Levels: 3  
                                                                                   Logic: 0.411ns(23.937%), Route: 1.306ns(76.063%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.260      42.960         _N134            
 CLMS_159_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.592      43.552                          
 clock uncertainty                                      -0.150      43.402                          

 Setup time                                             -0.138      43.264                          

 Data required time                                                 43.264                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.264                          
 Data arrival time                                                   5.269                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        37.995                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_L6Q_perm/I2
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.000  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.960
  Launch Clock Delay      :  3.552
  Clock Pessimism Removal :  0.592

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.308       3.552         _N134            
 CLMS_159_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_325/Q1                   tco                   0.125       3.677 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=7)        0.319       3.996         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [2]
 CLMS_159_319/Y2                   td                    0.122       4.118 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_111/LUT6_inst_perm/L6
                                   net (fanout=8)        0.407       4.525         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N41325
 CLMA_159_330/Y0                   td                    0.039       4.564 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N357_7/LUT6_inst_perm/L6
                                   net (fanout=1)        0.420       4.984         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N8214
 CLMS_159_319/Y1                   td                    0.125       5.109 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N357_11_3/gateop_perm/L6
                                   net (fanout=6)        0.156       5.265         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N8215
 CLMS_159_325/D2                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_L6Q_perm/I2

 Data arrival time                                                   5.265         Logic Levels: 3  
                                                                                   Logic: 0.411ns(23.993%), Route: 1.302ns(76.007%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.260      42.960         _N134            
 CLMS_159_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.592      43.552                          
 clock uncertainty                                      -0.150      43.402                          

 Setup time                                             -0.117      43.285                          

 Data required time                                                 43.285                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.285                          
 Data arrival time                                                   5.265                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.020                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gate_start_d[2]/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L6Q_perm/I5
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.148  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.552
  Launch Clock Delay      :  2.961
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.261       2.961         _N134            
 CLMA_159_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gate_start_d[2]/opit_0_inv/CLK

 CLMA_159_318/Q1                   tco                   0.109       3.070 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gate_start_d[2]/opit_0_inv/Q
                                   net (fanout=2)        0.134       3.204         I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dbg_gate_start_d [2]
 CLMA_171_318/A5                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L6Q_perm/I5

 Data arrival time                                                   3.204         Logic Levels: 0  
                                                                                   Logic: 0.109ns(44.856%), Route: 0.134ns(55.144%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.308       3.552         _N132            
 CLMA_171_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                        -0.443       3.109                          
 clock uncertainty                                       0.000       3.109                          

 Hold time                                              -0.010       3.099                          

 Data required time                                                  3.099                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.099                          
 Data arrival time                                                   3.204                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.105                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/opit_0_inv_L6QL5Q_perm/I4
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.148  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.553
  Launch Clock Delay      :  2.962
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.262       2.962         _N134            
 CLMS_159_313/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_313/Q0                   tco                   0.103       3.065 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=5)        0.139       3.204         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg [1]
 CLMA_171_313/A4                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/opit_0_inv_L6QL5Q_perm/I4

 Data arrival time                                                   3.204         Logic Levels: 0  
                                                                                   Logic: 0.103ns(42.562%), Route: 0.139ns(57.438%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.309       3.553         _N132            
 CLMA_171_313/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                        -0.443       3.110                          
 clock uncertainty                                       0.000       3.110                          

 Hold time                                              -0.015       3.095                          

 Data required time                                                  3.095                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.095                          
 Data arrival time                                                   3.204                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.109                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[9]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/opit_0_inv_L6QL5Q_perm/I3
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.148  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.553
  Launch Clock Delay      :  2.962
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.262       2.962         _N134            
 CLMS_159_313/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[9]/opit_0_inv_L6QL5Q_perm/CLK

 CLMS_159_313/Q3                   tco                   0.103       3.065 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[9]/opit_0_inv_L6QL5Q_perm/L6Q
                                   net (fanout=6)        0.139       3.204         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg [7]
 CLMA_171_313/A3                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/opit_0_inv_L6QL5Q_perm/I3

 Data arrival time                                                   3.204         Logic Levels: 0  
                                                                                   Logic: 0.103ns(42.562%), Route: 0.139ns(57.438%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.309       3.553         _N132            
 CLMA_171_313/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/gpll_dps_en/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                        -0.443       3.110                          
 clock uncertainty                                       0.000       3.110                          

 Hold time                                              -0.021       3.089                          

 Data required time                                                  3.089                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.089                          
 Data arrival time                                                   3.204                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.115                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L6QL5Q_perm/I2
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.122  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.348
  Launch Clock Delay      :  4.413
  Clock Pessimism Removal :  0.943

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.294       4.413         _N124            
 CLMA_201_426/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK

 CLMA_201_426/CR1                  tco                   0.142       4.555 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/L5Q
                                   net (fanout=3)        0.956       5.511         I_ips_ddr_top/u_ddrphy_top/dbg_slice_status [31]
 CLMA_261_348/CR1                  td                    0.165       5.676 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_fsm[3:0]_37_or[1]_1/gateop_LUT6DL5_perm/L5
                                   net (fanout=4)        0.229       5.905         I_ips_ddr_top/u_ddrphy_top/wrlvl_dqs_resp
 CLMA_261_354/Y1                   td                    0.070       5.975 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/dbg_wrlvl_4_or[0]_4/LUT6_inst_perm/L6
                                   net (fanout=1)        0.432       6.407         I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N48291
 CLMA_261_306/Y1                   td                    0.100       6.507 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=7)        0.412       6.919         debug_calib_ctrl[18]
 CLMS_255_283/Y1                   td                    0.100       7.019 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[0]/opit_0_inv_L6Q_perm/L6
                                   net (fanout=8)        0.557       7.576         I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N144
 CLMA_285_235/A2                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L6QL5Q_perm/I2

 Data arrival time                                                   7.576         Logic Levels: 4  
                                                                                   Logic: 0.577ns(18.242%), Route: 2.586ns(81.758%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.273      10.967         _N123            
 CLMA_285_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                         0.943      11.910                          
 clock uncertainty                                      -0.150      11.760                          

 Setup time                                             -0.112      11.648                          

 Data required time                                                 11.648                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.648                          
 Data arrival time                                                   7.576                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.072                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CE
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.072  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.327
  Launch Clock Delay      :  4.443
  Clock Pessimism Removal :  1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.324       4.443         _N124            
 CLMA_261_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/CLK

 CLMA_261_318/Q3                   tco                   0.125       4.568 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=8)        0.960       5.528         I_ips_ddr_top/u_ddrphy_top/wrlvl_dqs_req
 CLMA_195_438/Y1                   td                    0.125       5.653 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L6Q_perm/L6
                                   net (fanout=2)        0.672       6.325         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/_N27
 CLMA_213_355/Y2                   td                    0.066       6.391 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=6)        0.416       6.807         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_next_state [1]
 CLMA_201_421/Y3                   td                    0.066       6.873 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/L6
                                   net (fanout=14)       0.440       7.313         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N370
 CLMA_201_397/Y2                   td                    0.062       7.375 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N478/LUT6_inst_perm/L6
                                   net (fanout=6)        0.220       7.595         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N478
 CLMA_207_396/CE                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CE

 Data arrival time                                                   7.595         Logic Levels: 4  
                                                                                   Logic: 0.444ns(14.086%), Route: 2.708ns(85.914%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.252      10.946         _N124            
 CLMA_207_396/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CLK
 clock pessimism                                         1.044      11.990                          
 clock uncertainty                                      -0.150      11.840                          

 Setup time                                             -0.116      11.724                          

 Data required time                                                 11.724                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.724                          
 Data arrival time                                                   7.595                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.129                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[2]/opit_0_inv_L6QL5Q_perm/CE
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -0.072  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.327
  Launch Clock Delay      :  4.443
  Clock Pessimism Removal :  1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.324       4.443         _N124            
 CLMA_261_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/CLK

 CLMA_261_318/Q3                   tco                   0.125       4.568 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L6Q_perm/L6Q
                                   net (fanout=8)        0.960       5.528         I_ips_ddr_top/u_ddrphy_top/wrlvl_dqs_req
 CLMA_195_438/Y1                   td                    0.125       5.653 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L6Q_perm/L6
                                   net (fanout=2)        0.672       6.325         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/_N27
 CLMA_213_355/Y2                   td                    0.066       6.391 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=6)        0.416       6.807         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_next_state [1]
 CLMA_201_421/Y3                   td                    0.066       6.873 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/L6
                                   net (fanout=14)       0.440       7.313         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N370
 CLMA_201_397/Y2                   td                    0.062       7.375 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N478/LUT6_inst_perm/L6
                                   net (fanout=6)        0.220       7.595         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/N478
 CLMS_207_397/CE                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[2]/opit_0_inv_L6QL5Q_perm/CE

 Data arrival time                                                   7.595         Logic Levels: 4  
                                                                                   Logic: 0.444ns(14.086%), Route: 2.708ns(85.914%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.252      10.946         _N124            
 CLMS_207_397/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/step_cnt[2]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                         1.044      11.990                          
 clock uncertainty                                      -0.150      11.840                          

 Setup time                                             -0.116      11.724                          

 Data required time                                                 11.724                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.724                          
 Data arrival time                                                   7.595                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.129                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[3]/opit_0_inv_32X2DL6QL5Q/WADDR[0]
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.045  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.422
  Launch Clock Delay      :  3.333
  Clock Pessimism Removal :  -1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.258       3.333         _N123            
 CLMA_213_222/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK

 CLMA_213_222/CR1                  tco                   0.124       3.457 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/L5Q
                                   net (fanout=23)       0.183       3.640         I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
 CLMS_207_211/D0                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[3]/opit_0_inv_32X2DL6QL5Q/WADDR[0]

 Data arrival time                                                   3.640         Logic Levels: 0  
                                                                                   Logic: 0.124ns(40.391%), Route: 0.183ns(59.609%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.303       4.422         _N123            
 CLMS_207_211/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[3]/opit_0_inv_32X2DL6QL5Q/CLK
 clock pessimism                                        -1.044       3.378                          
 clock uncertainty                                       0.000       3.378                          

 Hold time                                               0.161       3.539                          

 Data required time                                                  3.539                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.539                          
 Data arrival time                                                   3.640                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/WADDR[0]
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.045  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.422
  Launch Clock Delay      :  3.333
  Clock Pessimism Removal :  -1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.258       3.333         _N123            
 CLMA_213_222/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK

 CLMA_213_222/CR1                  tco                   0.124       3.457 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/L5Q
                                   net (fanout=23)       0.183       3.640         I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
 CLMS_207_211/D0                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/WADDR[0]

 Data arrival time                                                   3.640         Logic Levels: 0  
                                                                                   Logic: 0.124ns(40.391%), Route: 0.183ns(59.609%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.303       4.422         _N123            
 CLMS_207_211/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv_32X2DL6QL5Q/CLK
 clock pessimism                                        -1.044       3.378                          
 clock uncertainty                                       0.000       3.378                          

 Hold time                                               0.161       3.539                          

 Data required time                                                  3.539                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.539                          
 Data arrival time                                                   3.640                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[41]/opit_0_inv_32X2DL6QL5Q/WADDR[0]
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    0.045  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.422
  Launch Clock Delay      :  3.333
  Clock Pessimism Removal :  -1.044

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.258       3.333         _N123            
 CLMA_213_222/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/CLK

 CLMA_213_222/CR1                  tco                   0.124       3.457 f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[0]/opit_0_inv_L5Q_perm/L5Q
                                   net (fanout=23)       0.183       3.640         I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
 CLMS_207_211/D0                                                           f       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[41]/opit_0_inv_32X2DL6QL5Q/WADDR[0]

 Data arrival time                                                   3.640         Logic Levels: 0  
                                                                                   Logic: 0.124ns(40.391%), Route: 0.183ns(59.609%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.303       4.422         _N123            
 CLMS_207_211/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[41]/opit_0_inv_32X2DL6QL5Q/CLK
 clock pessimism                                        -1.044       3.378                          
 clock uncertainty                                       0.000       3.378                          

 Hold time                                               0.161       3.539                          

 Data required time                                                  3.539                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.539                          
 Data arrival time                                                   3.640                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[8]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    1.420  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.337
  Launch Clock Delay      :  2.076
  Clock Pessimism Removal :  0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.137       3.980         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_402/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_402/RX_DATA[0]          tco                   0.260       4.240 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/RX_DATA[0]
                                   net (fanout=1)        0.319       4.559         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [8]
 CLMA_285_390/CR2                  td                    0.066       4.625 f       CLKROUTE_93/CR   
                                   net (fanout=1)        1.644       6.269         _N99             
 CLMA_231_366/M0                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[8]/opit_0_inv_srl/D

 Data arrival time                                                   6.269         Logic Levels: 1  
                                                                                   Logic: 0.326ns(14.242%), Route: 1.963ns(85.758%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.262      10.956         _N124            
 CLMA_231_366/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[8]/opit_0_inv_srl/CLK
 clock pessimism                                         0.159      11.115                          
 clock uncertainty                                      -0.550      10.565                          

 Setup time                                             -0.074      10.491                          

 Data required time                                                 10.491                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.491                          
 Data arrival time                                                   6.269                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.222                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[14]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    1.426  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.343
  Launch Clock Delay      :  2.076
  Clock Pessimism Removal :  0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.137       3.980         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_324/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_324/RX_DATA[6]          tco                   0.260       4.240 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/RX_DATA[6]
                                   net (fanout=1)        0.481       4.721         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_rdata [14]
 CLMS_273_307/CR1                  td                    0.067       4.788 f       CLKROUTE_40/CR   
                                   net (fanout=1)        0.393       5.181         _N46             
 CLMS_273_319/CR3                  td                    0.065       5.246 f       CLKROUTE_41/CR   
                                   net (fanout=1)        1.005       6.251         _N47             
 CLMA_237_336/M1                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[14]/opit_0_inv_srl/D

 Data arrival time                                                   6.251         Logic Levels: 2  
                                                                                   Logic: 0.392ns(17.261%), Route: 1.879ns(82.739%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.268      10.962         _N124            
 CLMA_237_336/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[14]/opit_0_inv_srl/CLK
 clock pessimism                                         0.159      11.121                          
 clock uncertainty                                      -0.550      10.571                          

 Setup time                                             -0.074      10.497                          

 Data required time                                                 10.497                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.497                          
 Data arrival time                                                   6.251                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.246                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[2]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    1.423  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.340
  Launch Clock Delay      :  2.076
  Clock Pessimism Removal :  0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.137       3.980         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_396/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_396/RX_DATA[2]          tco                   0.260       4.240 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/RX_DATA[2]
                                   net (fanout=1)        0.382       4.622         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [2]
 CLMA_285_385/CR2                  td                    0.066       4.688 f       CLKROUTE_91/CR   
                                   net (fanout=1)        0.634       5.322         _N97             
 CLMA_267_372/CR1                  td                    0.067       5.389 f       CLKROUTE_92/CR   
                                   net (fanout=1)        0.826       6.215         _N98             
 CLMA_261_379/M0                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[2]/opit_0_inv_srl/D

 Data arrival time                                                   6.215         Logic Levels: 2  
                                                                                   Logic: 0.393ns(17.584%), Route: 1.842ns(82.416%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.265      10.959         _N124            
 CLMA_261_379/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[2]/opit_0_inv_srl/CLK
 clock pessimism                                         0.159      11.118                          
 clock uncertainty                                      -0.550      10.568                          

 Setup time                                             -0.074      10.494                          

 Data required time                                                 10.494                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.494                          
 Data arrival time                                                   6.215                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.279                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[9]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    2.525  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.436
  Launch Clock Delay      :  1.752
  Clock Pessimism Removal :  -0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    0.564      10.185 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.185         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      10.258 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      10.421         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      10.501 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      10.719         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      10.816 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      11.063         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      11.089 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      11.089         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      11.161 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.114      11.275         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_402/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_402/RX_DATA[1]          tco                   0.155      11.430 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/RX_DATA[1]
                                   net (fanout=1)        1.092      12.522         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [9]
 CLMA_267_366/M0                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[9]/opit_0_inv_srl/D

 Data arrival time                                                  12.522         Logic Levels: 0  
                                                                                   Logic: 0.155ns(12.430%), Route: 1.092ns(87.570%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.317      12.055         _N124            
 CLMA_267_366/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[9]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.159      11.896                          
 clock uncertainty                                       0.550      12.446                          

 Hold time                                              -0.025      12.421                          

 Data required time                                                 12.421                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.421                          
 Data arrival time                                                  12.522                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[3].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[26]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    2.519  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.430
  Launch Clock Delay      :  1.752
  Clock Pessimism Removal :  -0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    0.564      10.185 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.185         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      10.258 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      10.421         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      10.501 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      10.719         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      10.816 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      11.063         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      11.089 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      11.089         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      11.161 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.114      11.275         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_414/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[3].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_414/RX_DATA[2]          tco                   0.155      11.430 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[3].u_iobuf_dq/opit_1/RX_DATA[2]
                                   net (fanout=1)        1.086      12.516         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_rdata [26]
 CLMS_237_367/M0                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[26]/opit_0_inv_srl/D

 Data arrival time                                                  12.516         Logic Levels: 0  
                                                                                   Logic: 0.155ns(12.490%), Route: 1.086ns(87.510%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.311      12.049         _N124            
 CLMS_237_367/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[26]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.159      11.890                          
 clock uncertainty                                       0.550      12.440                          

 Hold time                                              -0.025      12.415                          

 Data required time                                                 12.415                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.415                          
 Data arrival time                                                  12.516                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/ICLKDIV
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[22]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    2.532  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.443
  Launch Clock Delay      :  1.752
  Clock Pessimism Removal :  -0.159

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    0.564      10.185 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.185         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      10.258 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      10.421         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      10.501 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      10.719         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      10.816 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      11.063         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      11.089 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      11.089         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      11.161 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.114      11.275         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_330/ICLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/ICLKDIV

 IOLHR_292_330/RX_DATA[6]          tco                   0.155      11.430 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1/RX_DATA[6]
                                   net (fanout=1)        1.102      12.532         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_rdata [22]
 CLMS_237_301/M0                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[22]/opit_0_inv_srl/D

 Data arrival time                                                  12.532         Logic Levels: 0  
                                                                                   Logic: 0.155ns(12.331%), Route: 1.102ns(87.669%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.324      12.062         _N123            
 CLMS_237_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rddata_r1[22]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.159      11.903                          
 clock uncertainty                                       0.550      12.453                          

 Hold time                                              -0.025      12.428                          

 Data required time                                                 12.428                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.428                          
 Data arrival time                                                  12.532                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.104                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
Endpoint    : I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    1.698  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.336
  Launch Clock Delay      :  1.939
  Clock Pessimism Removal :  0.301

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       3.843         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 DDRPHY_CPD_297_4/PPLL_SYSCLK                                              r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY

 DDRPHY_CPD_297_4/CPD_UP_DNB       tco                   0.069       3.912 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/FLAG_PD
                                   net (fanout=2)        1.372       5.284         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_up_dnb
 CLMA_153_300/CR3                  td                    0.068       5.352 f       CLKROUTE_1/CR    
                                   net (fanout=1)        0.302       5.654         _N7              
 CLMA_171_283/M2                                                           f       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D

 Data arrival time                                                   5.654         Logic Levels: 1  
                                                                                   Logic: 0.137ns(7.565%), Route: 1.674ns(92.435%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.261      10.955         _N123            
 CLMA_171_283/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                         0.301      11.256                          
 clock uncertainty                                      -0.550      10.706                          

 Setup time                                             -0.074      10.632                          

 Data required time                                                 10.632                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 10.632                          
 Data arrival time                                                   5.654                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         4.978                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
Endpoint    : I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    2.489  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.428
  Launch Clock Delay      :  1.638
  Clock Pessimism Removal :  -0.301

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         9.523       9.523 r                        
 V4                                                      0.000       9.523 r       free_clk (port)  
                                   net (fanout=1)        0.098       9.621         free_clk         
 IOBD_300_162/DIN                  td                    0.564      10.185 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      10.185         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      10.258 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      10.421         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      10.501 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      10.719         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097      10.816 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      11.063         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026      11.089 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      11.089         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072      11.161 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000      11.161         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 DDRPHY_CPD_297_4/PPLL_SYSCLK                                              r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY

 DDRPHY_CPD_297_4/CPD_UP_DNB       tco                   0.042      11.203 r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/FLAG_PD
                                   net (fanout=2)        0.994      12.197         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_up_dnb
 CLMA_153_300/CR3                  td                    0.057      12.254 r       CLKROUTE_1/CR    
                                   net (fanout=1)        0.209      12.463         _N7              
 CLMA_171_283/M2                                                           r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/D

 Data arrival time                                                  12.463         Logic Levels: 1  
                                                                                   Logic: 0.099ns(7.604%), Route: 1.203ns(92.396%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.309      12.047         _N123            
 CLMA_171_283/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ips2l_ddrphy_cpd_lock/ddrphy_cpd_up_dnb_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.301      11.746                          
 clock uncertainty                                       0.550      12.296                          

 Hold time                                              -0.025      12.271                          

 Data required time                                                 12.271                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 12.271                          
 Data arrival time                                                  12.463                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.192                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/TX_DATA[7]
Path Group  : phy_dq_sysclk_0
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.375  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.429
  Clock Pessimism Removal :  0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.310      12.048         _N123            
 CLMA_261_199/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_261_199/Q0                   tco                   0.125      12.173 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        0.756      12.929         debug_data[66]   
 CLMA_285_198/Y0                   td                    0.039      12.968 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       0.622      13.590         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_271/Y0                   td                    0.125      13.715 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_39:32_2[4]/LUT6D_inst_perm/L6
                                   net (fanout=1)        0.887      14.602         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [39]
 IOLHR_292_270/TX_DATA[7]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/TX_DATA[7]

 Data arrival time                                                  14.602         Logic Levels: 2  
                                                                                   Logic: 0.289ns(11.316%), Route: 2.265ns(88.684%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_270/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.301      19.196                          
 clock uncertainty                                      -0.550      18.646                          

 Setup time                                             -0.189      18.457                          

 Data required time                                                 18.457                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.457                          
 Data arrival time                                                  14.602                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.855                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[6].u_outbuft_addr0/opit_1/TX_DATA[7]
Path Group  : phy_dq_sysclk_0
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.375  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.429
  Clock Pessimism Removal :  0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.310      12.048         _N123            
 CLMA_261_199/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_261_199/Q0                   tco                   0.125      12.173 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        0.756      12.929         debug_data[66]   
 CLMA_285_198/Y0                   td                    0.039      12.968 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       0.497      13.465         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_259/Y2                   td                    0.122      13.587 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_55:48_2[4]/LUT6D_inst_perm/L6
                                   net (fanout=1)        1.009      14.596         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [55]
 IOLHR_292_258/TX_DATA[7]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[6].u_outbuft_addr0/opit_1/TX_DATA[7]

 Data arrival time                                                  14.596         Logic Levels: 2  
                                                                                   Logic: 0.286ns(11.224%), Route: 2.262ns(88.776%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_258/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[6].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.301      19.196                          
 clock uncertainty                                      -0.550      18.646                          

 Setup time                                             -0.189      18.457                          

 Data required time                                                 18.457                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.457                          
 Data arrival time                                                  14.596                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.861                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[2].u_outbuft_addr0/opit_1/TX_DATA[7]
Path Group  : phy_dq_sysclk_0
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.375  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.429
  Clock Pessimism Removal :  0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.310      12.048         _N123            
 CLMA_261_199/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/CLK

 CLMA_261_199/Q0                   tco                   0.125      12.173 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/this_group_ca_dly/opit_0_inv/Q
                                   net (fanout=3)        0.756      12.929         debug_data[66]   
 CLMA_285_198/Y0                   td                    0.039      12.968 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/all_group_ca_dly_r2/opit_0_inv_L6QQ_perm/L6
                                   net (fanout=49)       0.554      13.522         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/all_group_ca_dly
 CLMA_285_271/Y2                   td                    0.100      13.622 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_15:8_2[4]/LUT6D_inst_perm/L6
                                   net (fanout=6)        0.973      14.595         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [15]
 IOLHR_292_282/TX_DATA[7]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[2].u_outbuft_addr0/opit_1/TX_DATA[7]

 Data arrival time                                                  14.595         Logic Levels: 2  
                                                                                   Logic: 0.264ns(10.365%), Route: 2.283ns(89.635%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_282/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[2].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                         0.301      19.196                          
 clock uncertainty                                      -0.550      18.646                          

 Setup time                                             -0.189      18.457                          

 Data required time                                                 18.457                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.457                          
 Data arrival time                                                  14.595                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.862                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[7]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[1].u_outbuft_ba/opit_1/TX_DATA[5]
Path Group  : phy_dq_sysclk_0
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.570  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.346
  Clock Pessimism Removal :  -0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.271       3.346         _N123            
 CLMA_285_228/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[7]/opit_0_inv_srl/CLK

 CLMA_285_228/Q0                   tco                   0.103       3.449 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[7]/opit_0_inv_srl/Q0
                                   net (fanout=6)        0.330       3.779         I_ips_ddr_top/u_ddrphy_top/phy_ba [7]
 CLMA_285_181/CR0                  td                    0.144       3.923 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_ba_15:8_2[1]/LUT6D_inst_perm/L5
                                   net (fanout=2)        0.384       4.307         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_ba [13]
 IOLHR_292_186/TX_DATA[5]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[1].u_outbuft_ba/opit_1/TX_DATA[5]

 Data arrival time                                                   4.307         Logic Levels: 1  
                                                                                   Logic: 0.247ns(25.702%), Route: 0.714ns(74.298%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_186/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[1].u_outbuft_ba/opit_1/OCLKDIV
 clock pessimism                                        -0.301       3.680                          
 clock uncertainty                                       0.550       4.230                          

 Hold time                                              -0.024       4.206                          

 Data required time                                                  4.206                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.206                          
 Data arrival time                                                   4.307                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_casn/opit_1/TX_DATA[2]
Path Group  : phy_dq_sysclk_0
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.567  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.343
  Clock Pessimism Removal :  -0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.268       3.343         _N123            
 CLMA_273_222/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_273_222/CR1                  tco                   0.123       3.466 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=7)        0.336       3.802         I_ips_ddr_top/u_ddrphy_top/phy_cas_n [0]
 CLMA_285_157/Y1                   td                    0.052       3.854 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_cas_n_2[1]/LUT6D_inst_perm/L6
                                   net (fanout=2)        0.453       4.307         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_cas_n [1]
 IOLHR_292_108/TX_DATA[2]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_casn/opit_1/TX_DATA[2]

 Data arrival time                                                   4.307         Logic Levels: 1  
                                                                                   Logic: 0.175ns(18.154%), Route: 0.789ns(81.846%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_108/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_casn/opit_1/OCLKDIV
 clock pessimism                                        -0.301       3.680                          
 clock uncertainty                                       0.550       4.230                          

 Hold time                                              -0.024       4.206                          

 Data required time                                                  4.206                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.206                          
 Data arrival time                                                   4.307                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/calib_done_r/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[9].u_outbuft_addr0/opit_1/TX_DATA[2]
Path Group  : phy_dq_sysclk_0
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.570  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.346
  Clock Pessimism Removal :  -0.301
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_180/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.271       3.346         _N123            
 CLMA_285_229/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/calib_done_r/opit_0_inv_srl/CLK

 CLMA_285_229/CR0                  tco                   0.123       3.469 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/calib_done_r/opit_0_inv_srl/CR0
                                   net (fanout=20)       0.177       3.646         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/phy_addr_r [1]
 CLMA_285_247/Y0                   td                    0.052       3.698 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ddrphy_control_path_adj/adj_addr_79:72_2[1]/LUT6D_inst_perm/L6
                                   net (fanout=2)        0.610       4.308         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/adj_addr [73]
 IOLHR_292_240/TX_DATA[2]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[9].u_outbuft_addr0/opit_1/TX_DATA[2]

 Data arrival time                                                   4.308         Logic Levels: 1  
                                                                                   Logic: 0.175ns(18.191%), Route: 0.787ns(81.809%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_0 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 IOLHR_292_240/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[9].u_outbuft_addr0/opit_1/OCLKDIV
 clock pessimism                                        -0.301       3.680                          
 clock uncertainty                                       0.550       4.230                          

 Hold time                                              -0.024       4.206                          

 Data required time                                                  4.206                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.206                          
 Data arrival time                                                   4.308                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.102                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/TX_DATA[3]
Path Group  : phy_dq_sysclk_1
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.530  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.442
  Clock Pessimism Removal :  0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.323      12.061         _N124            
 CLMA_261_324/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/CLK

 CLMA_261_324/CR0                  tco                   0.141      12.202 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/L5Q
                                   net (fanout=82)       0.927      13.129         debug_data[67]   
 CLMA_279_444/Y3                   td                    0.100      13.229 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[71]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.178      13.407         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdq [59]
 CLMS_279_463/CR2                  td                    0.066      13.473 f       CLKROUTE_24/CR   
                                   net (fanout=1)        1.260      14.733         _N30             
 IOLHR_292_378/TX_DATA[3]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/TX_DATA[3]

 Data arrival time                                                  14.733         Logic Levels: 2  
                                                                                   Logic: 0.307ns(11.490%), Route: 2.365ns(88.510%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_378/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/OCLKDIV
 clock pessimism                                         0.159      19.054                          
 clock uncertainty                                      -0.550      18.504                          

 Setup time                                             -0.189      18.315                          

 Data required time                                                 18.315                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.315                          
 Data arrival time                                                  14.733                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.582                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/TX_DATA[2]
Path Group  : phy_dq_sysclk_1
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.530  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.442
  Clock Pessimism Removal :  0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.323      12.061         _N124            
 CLMA_261_324/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/CLK

 CLMA_261_324/Q0                   tco                   0.125      12.186 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/L6Q
                                   net (fanout=85)       0.843      13.029         debug_data[68]   
 CLMA_285_439/Y0                   td                    0.125      13.154 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[46]/LUT6_inst_perm/L6
                                   net (fanout=1)        1.502      14.656         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdq [34]
 IOLHR_292_342/TX_DATA[2]                                                  f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/TX_DATA[2]

 Data arrival time                                                  14.656         Logic Levels: 1  
                                                                                   Logic: 0.250ns(9.634%), Route: 2.345ns(90.366%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_342/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/OCLKDIV
 clock pessimism                                         0.159      19.054                          
 clock uncertainty                                      -0.550      18.504                          

 Setup time                                             -0.189      18.315                          

 Data required time                                                 18.315                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.315                          
 Data arrival time                                                  14.656                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.659                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[7]
Path Group  : phy_dq_sysclk_1
Path Type   : max (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -2.520  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  1.753
  Launch Clock Delay      :  4.432
  Clock Pessimism Removal :  0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.660       8.377 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.377         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       8.464 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       8.661         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       8.756 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       9.016         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       9.131 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       9.431         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       9.470 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.470         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       9.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.558         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934      10.492 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501      10.993         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115      11.108 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397      11.505         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233      11.738 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.313      12.051         _N124            
 CLMA_279_396/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/CLK

 CLMA_279_396/Q1                   tco                   0.125      12.176 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv_L6QQ_perm/L6Q
                                   net (fanout=4)        0.826      13.002         I_ips_ddr_top/u_ddrphy_top/phy_wrdata_en [3]
 CLMS_279_403/Y1                   td                    0.100      13.102 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/N28[7]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.395      13.497         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdq_en [7]
 CLMA_267_402/CR1                  td                    0.067      13.564 f       CLKROUTE_90/CR   
                                   net (fanout=1)        1.149      14.713         _N96             
 TSERDES_299_309/TS_CTRL[7]                                                f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/TS_CTRL[7]

 Data arrival time                                                  14.713         Logic Levels: 2  
                                                                                   Logic: 0.292ns(10.969%), Route: 2.370ns(89.031%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                        17.142      17.142 r                        
 V4                                                      0.000      17.142 r       free_clk (port)  
                                   net (fanout=1)        0.098      17.240         free_clk         
 IOBD_300_162/DIN                  td                    0.564      17.804 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      17.804         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      17.877 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163      18.040         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080      18.120 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218      18.338         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.097      18.435 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247      18.682         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.026      18.708 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000      18.708         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.072      18.780 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.115      18.895         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 TSERDES_299_309/OCLKDIV                                                   r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes1_dq/oserdes_inst/OCLKDIV
 clock pessimism                                         0.159      19.054                          
 clock uncertainty                                      -0.550      18.504                          

 Setup time                                             -0.128      18.376                          

 Data required time                                                 18.376                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 18.376                          
 Data arrival time                                                  14.713                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         3.663                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_outbuft_dm/opit_1/TX_DATA[0]
Path Group  : phy_dq_sysclk_1
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.428  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.346
  Clock Pessimism Removal :  -0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.271       3.346         _N124            
 CLMA_285_366/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_srl/CLK

 CLMA_285_366/CR3                  tco                   0.122       3.468 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_srl/CR0
                                   net (fanout=4)        0.256       3.724         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_mask_r [0]
 CLMA_285_342/Y1                   td                    0.035       3.759 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[0]/gateop_perm/L6
                                   net (fanout=1)        0.690       4.449         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdata_mask [0]
 IOLHR_292_312/TX_DATA[0]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_outbuft_dm/opit_1/TX_DATA[0]

 Data arrival time                                                   4.449         Logic Levels: 1  
                                                                                   Logic: 0.157ns(14.234%), Route: 0.946ns(85.766%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_312/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_outbuft_dm/opit_1/OCLKDIV
 clock pessimism                                        -0.159       3.822                          
 clock uncertainty                                       0.550       4.372                          

 Hold time                                              -0.024       4.348                          

 Data required time                                                  4.348                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.348                          
 Data arrival time                                                   4.449                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.101                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[35]/opit_0_inv_L6QQ_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/TX_DATA[6]
Path Group  : phy_dq_sysclk_1
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.416  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.334
  Clock Pessimism Removal :  -0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.259       3.334         _N124            
 CLMA_285_438/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[35]/opit_0_inv_L6QQ_perm/CLK

 CLMA_285_438/Q2                   tco                   0.109       3.443 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/phy_wrdata_r[35]/opit_0_inv_L6QQ_perm/L6Q
                                   net (fanout=4)        0.168       3.611         I_ips_ddr_top/u_ddrphy_top/phy_wrdata [52]
 CLMS_279_439/Y1                   td                    0.052       3.663 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_wdata_path_adj/adj_wrdata_mask_3[50]/LUT6_inst_perm/L6
                                   net (fanout=1)        0.790       4.453         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/adj_wrdq [38]
 IOLHR_292_342/TX_DATA[6]                                                  r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/TX_DATA[6]

 Data arrival time                                                   4.453         Logic Levels: 1  
                                                                                   Logic: 0.161ns(14.388%), Route: 0.958ns(85.612%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 IOLHR_292_342/OCLKDIV                                                     r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1/OCLKDIV
 clock pessimism                                        -0.159       3.822                          
 clock uncertainty                                       0.550       4.372                          

 Hold time                                              -0.024       4.348                          

 Data required time                                                  4.348                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.348                          
 Data arrival time                                                   4.453                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.105                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/TS_CTRL[3]
Path Group  : phy_dq_sysclk_1
Path Type   : min (fast corner)
Path Class  : sequential timing path
Clock Skew  :    -1.425  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.077
  Launch Clock Delay      :  3.343
  Clock Pessimism Removal :  -0.159
Timing Exception  :  MultiCycle Path Setup -end 2

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.268       3.343         _N124            
 CLMS_273_373/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/CLK

 CLMS_273_373/Q0                   tco                   0.109       3.452 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/ck_dqs_diff[1]/opit_0_inv_L6QL5Q1_perm/L6Q
                                   net (fanout=85)       0.257       3.709         debug_data[137]  
 CLMA_285_408/Y0                   td                    0.102       3.811 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_wdata_path_adj/N659[2]/LUT6_inst_perm/L6
                                   net (fanout=2)        0.660       4.471         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/adj_wrdqs_en [2]
 TSERDES_299_310/TS_CTRL[3]                                                r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/TS_CTRL[3]

 Data arrival time                                                   4.471         Logic Levels: 1  
                                                                                   Logic: 0.211ns(18.706%), Route: 0.917ns(81.294%)
----------------------------------------------------------------------------------------------------

 Clock phy_dq_sysclk_1 (rising edge)
                                                         1.904       1.904 r                        
 V4                                                      0.000       1.904 r       free_clk (port)  
                                   net (fanout=1)        0.098       2.002         free_clk         
 IOBD_300_162/DIN                  td                    0.660       2.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       2.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       2.749 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       2.946         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       3.041 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       3.301         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_456/CLKOUT               td                    0.115       3.416 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       3.716         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [1]
 PPLL_295_307/CLKOUTPHY            td                    0.039       3.755 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=43)       0.000       3.755         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_clk_p [1]
 DDRPHY_IOCLK_DIV_296_310/CLKOUT   td                    0.088       3.843 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=42)       0.138       3.981         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/phy_sysclk_p [1]
 TSERDES_299_310/OCLKDIV                                                   r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/OCLKDIV
 clock pessimism                                        -0.159       3.822                          
 clock uncertainty                                       0.550       4.372                          

 Hold time                                              -0.007       4.365                          

 Data required time                                                  4.365                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  4.365                          
 Data arrival time                                                   4.471                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.106                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[9]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.166  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.102
  Launch Clock Delay      :  2.491
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.313       2.491         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.141       2.632 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      0.796       3.428         free_clk_rst_n   
 CLMA_201_373/RSCO                 td                    0.052       3.480 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[8]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.480         ntR405           
 CLMA_201_379/RSCO                 td                    0.049       3.529 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[9]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.529         ntR404           
 CLMA_201_385/RSCO                 td                    0.049       3.578 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[8]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.578         ntR403           
 CLMA_201_391/RSCO                 td                    0.049       3.627 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[9]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.627         ntR402           
 CLMA_201_397/RSCO                 td                    0.049       3.676 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[11]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.676         ntR401           
 CLMA_201_403/RSCO                 td                    0.049       3.725 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_1[11]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.725         ntR400           
 CLMA_201_409/RSCO                 td                    0.049       3.774 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[30]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.774         ntR399           
 CLMA_201_415/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[9]/opit_0_inv/RS

 Data arrival time                                                   3.774         Logic Levels: 7  
                                                                                   Logic: 0.487ns(37.958%), Route: 0.796ns(62.042%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.248      42.102         _N129            
 CLMA_201_415/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[9]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.325                          
 clock uncertainty                                      -0.050      42.275                          

 Recovery time                                          -0.116      42.159                          

 Data required time                                                 42.159                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.159                          
 Data arrival time                                                   3.774                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.385                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[30]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.165  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.103
  Launch Clock Delay      :  2.491
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.313       2.491         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.141       2.632 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      0.796       3.428         free_clk_rst_n   
 CLMA_201_373/RSCO                 td                    0.052       3.480 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[8]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.480         ntR405           
 CLMA_201_379/RSCO                 td                    0.049       3.529 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[9]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.529         ntR404           
 CLMA_201_385/RSCO                 td                    0.049       3.578 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[8]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.578         ntR403           
 CLMA_201_391/RSCO                 td                    0.049       3.627 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[9]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.627         ntR402           
 CLMA_201_397/RSCO                 td                    0.049       3.676 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[11]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.676         ntR401           
 CLMA_201_403/RSCO                 td                    0.049       3.725 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_1[11]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.725         ntR400           
 CLMA_201_409/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[30]/opit_0_inv/RS

 Data arrival time                                                   3.725         Logic Levels: 6  
                                                                                   Logic: 0.438ns(35.494%), Route: 0.796ns(64.506%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.249      42.103         _N129            
 CLMA_201_409/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[30]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.326                          
 clock uncertainty                                      -0.050      42.276                          

 Recovery time                                          -0.116      42.160                          

 Data required time                                                 42.160                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.160                          
 Data arrival time                                                   3.725                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.435                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[27]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.173  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.095
  Launch Clock Delay      :  2.491
  Clock Pessimism Removal :  0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.313       2.491         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.141       2.632 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      0.421       3.053         free_clk_rst_n   
 CLMS_177_349/RSCO                 td                    0.052       3.105 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_5[23]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.105         ntR236           
 CLMS_177_355/RSCO                 td                    0.049       3.154 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_4[13]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.154         ntR235           
 CLMS_177_361/RSCO                 td                    0.049       3.203 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/rd_data[15]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=1)        0.000       3.203         ntR234           
 CLMS_177_367/RSCO                 td                    0.049       3.252 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_9[13]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.252         ntR233           
 CLMS_177_373/RSCO                 td                    0.049       3.301 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_11[15]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.301         ntR232           
 CLMS_177_379/RSCO                 td                    0.049       3.350 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[15]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.350         ntR231           
 CLMS_177_385/RSCO                 td                    0.049       3.399 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_9[15]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.399         ntR230           
 CLMS_177_391/RSCO                 td                    0.049       3.448 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[30]/opit_0_inv/RSCO
                                   net (fanout=3)        0.000       3.448         ntR229           
 CLMS_177_397/RSCO                 td                    0.049       3.497 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_10[30]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.497         ntR228           
 CLMS_177_403/RSCO                 td                    0.049       3.546 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_cmd_parser/data_b3[6]/opit_0_inv/RSCO
                                   net (fanout=4)        0.000       3.546         ntR227           
 CLMS_177_409/RSCO                 td                    0.049       3.595 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_13[30]/opit_0_inv/RSCO
                                   net (fanout=2)        0.000       3.595         ntR226           
 CLMS_177_415/RSCO                 td                    0.049       3.644 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_3[27]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.644         ntR225           
 CLMS_177_421/RSCO                 td                    0.049       3.693 r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_6[27]/opit_0_inv/RSCO
                                   net (fanout=1)        0.000       3.693         ntR224           
 CLMS_177_427/RSCI                                                         r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[27]/opit_0_inv/RS

 Data arrival time                                                   3.693         Logic Levels: 13 
                                                                                   Logic: 0.781ns(64.975%), Route: 0.421ns(35.025%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493      41.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097      41.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      41.659         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.195      41.854 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.241      42.095         _N129            
 CLMS_177_427/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_12[27]/opit_0_inv/CLK
 clock pessimism                                         0.223      42.318                          
 clock uncertainty                                      -0.050      42.268                          

 Recovery time                                          -0.116      42.152                          

 Data required time                                                 42.152                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 42.152                          
 Data arrival time                                                   3.693                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.459                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[19]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.150  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.492
  Launch Clock Delay      :  2.119
  Clock Pessimism Removal :  -0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.265       2.119         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.123       2.242 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      0.223       2.465         free_clk_rst_n   
 CLMA_147_295/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[19]/opit_0_inv/RS

 Data arrival time                                                   2.465         Logic Levels: 0  
                                                                                   Logic: 0.123ns(35.549%), Route: 0.223ns(64.451%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_170/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_7/CLKOUT
                                   net (fanout=4)        0.314       2.492         _N130            
 CLMA_147_295/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[19]/opit_0_inv/CLK
 clock pessimism                                        -0.223       2.269                          
 clock uncertainty                                       0.000       2.269                          

 Removal time                                           -0.038       2.231                          

 Data required time                                                  2.231                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.231                          
 Data arrival time                                                   2.465                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.234                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[6]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.146  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.488
  Launch Clock Delay      :  2.119
  Clock Pessimism Removal :  -0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.265       2.119         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.123       2.242 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      0.222       2.464         free_clk_rst_n   
 CLMA_177_312/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[6]/opit_0_inv/RS

 Data arrival time                                                   2.464         Logic Levels: 0  
                                                                                   Logic: 0.123ns(35.652%), Route: 0.222ns(64.348%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_230/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_6/CLKOUT
                                   net (fanout=285)      0.310       2.488         _N129            
 CLMA_177_312/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_0[6]/opit_0_inv/CLK
 clock pessimism                                        -0.223       2.265                          
 clock uncertainty                                       0.000       2.265                          

 Removal time                                           -0.038       2.227                          

 Data required time                                                  2.227                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.227                          
 Data arrival time                                                   2.464                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.237                          
====================================================================================================

====================================================================================================

Startpoint  : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK
Endpoint    : u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_13[19]/opit_0_inv/RS
Path Group  : ref_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.149  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.491
  Launch Clock Delay      :  2.119
  Clock Pessimism Removal :  -0.223

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.493       1.228         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.097       1.325 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       1.659         free_clk_g       
 HCKB_165_210/CLKOUT               td                    0.195       1.854 r       HCKBROUTE_4/CLKOUT
                                   net (fanout=242)      0.265       2.119         _N127            
 CLMA_147_307/CLK                                                          r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CLK

 CLMA_147_307/CR0                  tco                   0.123       2.242 f       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/CR0
                                   net (fanout=169)      0.236       2.478         free_clk_rst_n   
 CLMA_153_294/RS                                                           f       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_13[19]/opit_0_inv/RS

 Data arrival time                                                   2.478         Logic Levels: 0  
                                                                                   Logic: 0.123ns(34.262%), Route: 0.236ns(65.738%)
----------------------------------------------------------------------------------------------------

 Clock ref_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.588       1.433         nt_free_clk      
 USCM_167_273/CLKOUT               td                    0.115       1.548 r       free_clk_ibufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       1.945         free_clk_g       
 HCKB_165_170/CLKOUT               td                    0.233       2.178 r       HCKBROUTE_7/CLKOUT
                                   net (fanout=4)        0.313       2.491         _N130            
 CLMA_153_294/CLK                                                          r       u_ips2l_uart_ctrl/u_uart_ctrl/u_ver_ctrl/ctrl_bus_13[19]/opit_0_inv/CLK
 clock pessimism                                        -0.223       2.268                          
 clock uncertainty                                       0.000       2.268                          

 Removal time                                           -0.038       2.230                          

 Data required time                                                  2.230                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  2.230                          
 Data arrival time                                                   2.478                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.248                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv/RS
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.132  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.973
  Launch Clock Delay      :  3.548
  Clock Pessimism Removal :  0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_171/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=17)       0.304       3.548         _N133            
 CLMA_147_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_147_235/CR0                  tco                   0.141       3.689 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=42)       1.220       4.909         I_ips_ddr_top/u_ddrphy_top/rst_seq_rstn
 CLMA_285_54/RS                                                            f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv/RS

 Data arrival time                                                   4.909         Logic Levels: 0  
                                                                                   Logic: 0.141ns(10.360%), Route: 1.220ns(89.640%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_8/CLKOUT
                                   net (fanout=11)       0.273      42.973         _N131            
 CLMA_285_54/CLK                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv/CLK
 clock pessimism                                         0.443      43.416                          
 clock uncertainty                                      -0.150      43.266                          

 Recovery time                                          -0.072      43.194                          

 Data required time                                                 43.194                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.194                          
 Data arrival time                                                   4.909                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.285                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv/RS
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.132  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.973
  Launch Clock Delay      :  3.548
  Clock Pessimism Removal :  0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_171/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_10/CLKOUT
                                   net (fanout=17)       0.304       3.548         _N133            
 CLMA_147_235/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_147_235/CR0                  tco                   0.141       3.689 f       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_rst_seq_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=42)       1.109       4.798         I_ips_ddr_top/u_ddrphy_top/rst_seq_rstn
 CLMA_285_360/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv/RS

 Data arrival time                                                   4.798         Logic Levels: 0  
                                                                                   Logic: 0.141ns(11.280%), Route: 1.109ns(88.720%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.273      42.973         _N132            
 CLMA_285_360/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv/CLK
 clock pessimism                                         0.443      43.416                          
 clock uncertainty                                      -0.150      43.266                          

 Recovery time                                          -0.072      43.194                          

 Data required time                                                 43.194                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.194                          
 Data arrival time                                                   4.798                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.396                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[9]/opit_0_inv_AQ_perm/RS
Path Group  : rst_clk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.143  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  2.965
  Launch Clock Delay      :  3.551
  Clock Pessimism Removal :  0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.307       3.551         _N132            
 CLMA_171_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_171_325/CR1                  tco                   0.142       3.693 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=48)       0.780       4.473         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_69_367/RSCO                  td                    0.052       4.525 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[0]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=4)        0.000       4.525         ntR786           
 CLMA_69_373/RSCO                  td                    0.049       4.574 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[4]/opit_0_inv_AQ_perm/RSCO
                                   net (fanout=4)        0.000       4.574         ntR785           
 CLMA_69_379/RSCO                  td                    0.049       4.623 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[8]/opit_0_inv_AQ_perm/RSCO
                                   net (fanout=1)        0.000       4.623         ntR784           
 CLMA_69_385/RSCI                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[9]/opit_0_inv_AQ_perm/RS

 Data arrival time                                                   4.623         Logic Levels: 3  
                                                                                   Logic: 0.292ns(27.239%), Route: 0.780ns(72.761%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                            40.000      40.000 r                        
 V4                                                      0.000      40.000 r       free_clk (port)  
                                   net (fanout=1)        0.098      40.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564      40.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000      40.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073      40.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351      41.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195      41.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344      41.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029      41.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      42.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097      42.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      42.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_211/CLKOUT               td                    0.195      42.700 r       HCKBROUTE_11/CLKOUT
                                   net (fanout=74)       0.265      42.965         _N134            
 CLMA_69_385/CLK                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[9]/opit_0_inv_AQ_perm/CLK
 clock pessimism                                         0.443      43.408                          
 clock uncertainty                                      -0.150      43.258                          

 Recovery time                                          -0.116      43.142                          

 Data required time                                                 43.142                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 43.142                          
 Data arrival time                                                   4.623                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                        38.519                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/RS
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.154  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.556
  Launch Clock Delay      :  2.959
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.259       2.959         _N132            
 CLMA_171_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_171_325/CR1                  tco                   0.124       3.083 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=48)       0.224       3.307         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_171_301/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/RS

 Data arrival time                                                   3.307         Logic Levels: 0  
                                                                                   Logic: 0.124ns(35.632%), Route: 0.224ns(64.368%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_8/CLKOUT
                                   net (fanout=11)       0.312       3.556         _N131            
 CLMA_171_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.443       3.113                          
 clock uncertainty                                       0.000       3.113                          

 Removal time                                           -0.038       3.075                          

 Data required time                                                  3.075                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.075                          
 Data arrival time                                                   3.307                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.232                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_ack_rst_ctrl/opit_0_inv_srl/RS
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.154  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.556
  Launch Clock Delay      :  2.959
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.259       2.959         _N132            
 CLMA_171_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_171_325/CR1                  tco                   0.124       3.083 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=48)       0.224       3.307         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_171_301/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_ack_rst_ctrl/opit_0_inv_srl/RS

 Data arrival time                                                   3.307         Logic Levels: 0  
                                                                                   Logic: 0.124ns(35.632%), Route: 0.224ns(64.368%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_8/CLKOUT
                                   net (fanout=11)       0.312       3.556         _N131            
 CLMA_171_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_ack_rst_ctrl/opit_0_inv_srl/CLK
 clock pessimism                                        -0.443       3.113                          
 clock uncertainty                                       0.000       3.113                          

 Removal time                                           -0.038       3.075                          

 Data required time                                                  3.075                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.075                          
 Data arrival time                                                   3.307                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.232                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv_srl/RS
Path Group  : rst_clk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.154  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.556
  Launch Clock Delay      :  2.959
  Clock Pessimism Removal :  -0.443

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.351       1.086         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.195       1.281 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.344       1.625         _N135            
 GPLL_7_157/CLKOUT0                td                    0.029       1.654 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.074         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.097       2.171 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.505         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_231/CLKOUT               td                    0.195       2.700 r       HCKBROUTE_9/CLKOUT
                                   net (fanout=59)       0.259       2.959         _N132            
 CLMA_171_325/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/CLK

 CLMA_171_325/CR1                  tco                   0.124       3.083 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L6QL5Q_perm/L5Q
                                   net (fanout=48)       0.224       3.307         I_ips_ddr_top/u_ddrphy_top/logic_rstn
 CLMA_171_301/RS                                                           f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv_srl/RS

 Data arrival time                                                   3.307         Logic Levels: 0  
                                                                                   Logic: 0.124ns(35.632%), Route: 0.224ns(64.368%)
----------------------------------------------------------------------------------------------------

 Clock rst_clk (rising edge)                             0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.429       1.274         nt_free_clk      
 HCKB_165_162/CLKOUT               td                    0.233       1.507 r       HCKBROUTE_12/CLKOUT
                                   net (fanout=1)        0.428       1.935         _N135            
 GPLL_7_157/CLKOUT0                td                    0.063       1.998 r       I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       2.499         I_ips_ddr_top/u_ddrphy_top/rst_gpll_clkout0
 USCM_167_276/CLKOUT               td                    0.115       2.614 r       I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.011         I_ips_ddr_top/u_ddrphy_top/rst_clk
 HCKB_165_191/CLKOUT               td                    0.233       3.244 r       HCKBROUTE_8/CLKOUT
                                   net (fanout=11)       0.312       3.556         _N131            
 CLMA_171_301/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv_srl/CLK
 clock pessimism                                        -0.443       3.113                          
 clock uncertainty                                       0.000       3.113                          

 Removal time                                           -0.038       3.075                          

 Data required time                                                  3.075                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.075                          
 Data arrival time                                                   3.307                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.232                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[70]/opit_0_inv_L6Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.141  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.327
  Launch Clock Delay      :  4.411
  Clock Pessimism Removal :  0.943

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.292       4.411         _N123            
 CLMA_171_187/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_171_187/CR0                  tco                   0.141       4.552 f       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=410)      1.356       5.908         I_ips_ddr_top/ddrc_rstn
 CLMA_255_426/RSCO                 td                    0.052       5.960 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       5.960         ntR559           
 CLMA_255_432/RSCO                 td                    0.049       6.009 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=4)        0.000       6.009         ntR558           
 CLMA_255_438/RSCO                 td                    0.049       6.058 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       6.058         ntR557           
 CLMA_255_444/RSCI                                                         r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[70]/opit_0_inv_L6Q_perm/RS

 Data arrival time                                                   6.058         Logic Levels: 3  
                                                                                   Logic: 0.291ns(17.668%), Route: 1.356ns(82.332%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.252      10.946         _N124            
 CLMA_255_444/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[70]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.943      11.889                          
 clock uncertainty                                      -0.150      11.739                          

 Recovery time                                          -0.116      11.623                          

 Data required time                                                 11.623                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.623                          
 Data arrival time                                                   6.058                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         5.565                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[36]/opit_0_inv_L6Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.141  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.327
  Launch Clock Delay      :  4.411
  Clock Pessimism Removal :  0.943

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.292       4.411         _N123            
 CLMA_171_187/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_171_187/CR0                  tco                   0.141       4.552 f       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=410)      1.356       5.908         I_ips_ddr_top/ddrc_rstn
 CLMA_255_426/RSCO                 td                    0.052       5.960 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       5.960         ntR559           
 CLMA_255_432/RSCO                 td                    0.049       6.009 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=4)        0.000       6.009         ntR558           
 CLMA_255_438/RSCO                 td                    0.049       6.058 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       6.058         ntR557           
 CLMA_255_444/RSCI                                                         r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[36]/opit_0_inv_L6Q_perm/RS

 Data arrival time                                                   6.058         Logic Levels: 3  
                                                                                   Logic: 0.291ns(17.668%), Route: 1.356ns(82.332%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.252      10.946         _N124            
 CLMA_255_444/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[36]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.943      11.889                          
 clock uncertainty                                      -0.150      11.739                          

 Recovery time                                          -0.116      11.623                          

 Data required time                                                 11.623                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.623                          
 Data arrival time                                                   6.058                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         5.565                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
Endpoint    : I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[38]/opit_0_inv_L6Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : max (fast corner)
Path Class  : async timing path
Clock Skew  :    -0.141  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  3.327
  Launch Clock Delay      :  4.411
  Clock Pessimism Removal :  0.943

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.292       4.411         _N123            
 CLMA_171_187/CLK                                                          r       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK

 CLMA_171_187/CR0                  tco                   0.141       4.552 f       I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CR0
                                   net (fanout=410)      1.356       5.908         I_ips_ddr_top/ddrc_rstn
 CLMA_255_426/RSCO                 td                    0.052       5.960 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       5.960         ntR559           
 CLMA_255_432/RSCO                 td                    0.049       6.009 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm/RSCO
                                   net (fanout=4)        0.000       6.009         ntR558           
 CLMA_255_438/RSCO                 td                    0.049       6.058 r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_L6Q_perm/RSCO
                                   net (fanout=4)        0.000       6.058         ntR557           
 CLMA_255_444/RSCI                                                         r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[38]/opit_0_inv_L6Q_perm/RS

 Data arrival time                                                   6.058         Logic Levels: 3  
                                                                                   Logic: 0.291ns(17.668%), Route: 1.356ns(82.332%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       7.619       7.619 r                        
 V4                                                      0.000       7.619 r       free_clk (port)  
                                   net (fanout=1)        0.098       7.717         free_clk         
 IOBD_300_162/DIN                  td                    0.564       8.281 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       8.281         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       8.354 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       8.517         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       8.597 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       8.815         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       8.912 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       9.159         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       9.185 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       9.185         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       9.257 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       9.257         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       9.648 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420      10.068         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097      10.165 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334      10.499         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195      10.694 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.252      10.946         _N124            
 CLMA_255_444/CLK                                                          r       I_ips_ddr_top/u_ips_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[38]/opit_0_inv_L6Q_perm/CLK
 clock pessimism                                         0.943      11.889                          
 clock uncertainty                                      -0.150      11.739                          

 Recovery time                                          -0.116      11.623                          

 Data required time                                                 11.623                          
----------------------------------------------------------------------------------------------------
 Data required time                                                 11.623                          
 Data arrival time                                                   6.058                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         5.565                          
====================================================================================================

====================================================================================================

Startpoint  : u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK
Endpoint    : heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.152  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.431
  Launch Clock Delay      :  3.336
  Clock Pessimism Removal :  -0.943

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.261       3.336         _N124            
 CLMA_171_312/CLK                                                          r       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK

 CLMA_171_312/CR0                  tco                   0.123       3.459 f       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/L6QQ
                                   net (fanout=466)      0.244       3.703         core_clk_rst_n   
 CLMA_147_313/RS                                                           f       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/RS

 Data arrival time                                                   3.703         Logic Levels: 0  
                                                                                   Logic: 0.123ns(33.515%), Route: 0.244ns(66.485%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_200/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_3/CLKOUT
                                   net (fanout=29)       0.312       4.431         _N126            
 CLMA_147_313/CLK                                                          r       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/CLK
 clock pessimism                                        -0.943       3.488                          
 clock uncertainty                                       0.000       3.488                          

 Removal time                                           -0.038       3.450                          

 Data required time                                                  3.450                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.450                          
 Data arrival time                                                   3.703                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.253                          
====================================================================================================

====================================================================================================

Startpoint  : u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK
Endpoint    : u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[36]/opit_0_inv_L6QL5Q_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.152  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.431
  Launch Clock Delay      :  3.336
  Clock Pessimism Removal :  -0.943

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.261       3.336         _N124            
 CLMA_171_312/CLK                                                          r       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK

 CLMA_171_312/CR0                  tco                   0.123       3.459 f       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/L6QQ
                                   net (fanout=466)      0.250       3.709         core_clk_rst_n   
 CLMA_183_288/RS                                                           f       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[36]/opit_0_inv_L6QL5Q_perm/RS

 Data arrival time                                                   3.709         Logic Levels: 0  
                                                                                   Logic: 0.123ns(32.976%), Route: 0.250ns(67.024%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.312       4.431         _N123            
 CLMA_183_288/CLK                                                          r       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[36]/opit_0_inv_L6QL5Q_perm/CLK
 clock pessimism                                        -0.943       3.488                          
 clock uncertainty                                       0.000       3.488                          

 Removal time                                           -0.038       3.450                          

 Data required time                                                  3.450                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.450                          
 Data arrival time                                                   3.709                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.259                          
====================================================================================================

====================================================================================================

Startpoint  : u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK
Endpoint    : u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[98]/opit_0_inv_L6QL5Q1_perm/RS
Path Group  : ddrphy_sysclk
Path Type   : min (fast corner)
Path Class  : async timing path
Clock Skew  :    0.152  (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
  Capture Clock Delay     :  4.431
  Launch Clock Delay      :  3.336
  Clock Pessimism Removal :  -0.943

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.564       0.662 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.662         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.073       0.735 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.163       0.898         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.080       0.978 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.218       1.196         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.097       1.293 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.247       1.540         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.026       1.566 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.566         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.072       1.638 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.638         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.391       2.029 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.420       2.449         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.097       2.546 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.334       2.880         core_clk         
 HCKB_165_220/CLKOUT               td                    0.195       3.075 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.261       3.336         _N124            
 CLMA_171_312/CLK                                                          r       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/CLK

 CLMA_171_312/CR0                  tco                   0.123       3.459 f       u_core_clk_rst_sync/sig_async_r2[0]/opit_0_L6QQ_perm/L6QQ
                                   net (fanout=466)      0.250       3.709         core_clk_rst_n   
 CLMA_183_288/RS                                                           f       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[98]/opit_0_inv_L6QL5Q1_perm/RS

 Data arrival time                                                   3.709         Logic Levels: 0  
                                                                                   Logic: 0.123ns(32.976%), Route: 0.250ns(67.024%)
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.312       4.431         _N123            
 CLMA_183_288/CLK                                                          r       u_axi_bist_top/u_test_main_ctrl/I_prbs31_128bit/latch_y[98]/opit_0_inv_L6QL5Q1_perm/CLK
 clock pessimism                                        -0.943       3.488                          
 clock uncertainty                                       0.000       3.488                          

 Removal time                                           -0.038       3.450                          

 Data required time                                                  3.450                          
----------------------------------------------------------------------------------------------------
 Data required time                                                  3.450                          
 Data arrival time                                                   3.709                          
----------------------------------------------------------------------------------------------------
 Slack (MET)                                                         0.259                          
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv/CLK
Endpoint    : err_flag_led (port)
Path Group  : **default**
Path Type   : max (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_220/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_1/CLKOUT
                                   net (fanout=1813)     0.321       4.440         _N124            
 CLMA_243_318/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv/CLK

 CLMA_243_318/CR1                  tco                   0.142       4.582 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv/Q
                                   net (fanout=5)        0.551       5.133         ddr_init_done    
 CLMA_213_295/Y3                   td                    0.070       5.203 f       N3_4/gateop_perm/L6
                                   net (fanout=1)        1.694       6.897         nt_err_flag_led  
 IOLHR_16_606/DO_P                 td                    0.353       7.250 f       err_flag_led_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000       7.250         err_flag_led_obuf/ntO
 IOBS_0_606/PAD                    td                    1.098       8.348 f       err_flag_led_obuf/opit_0/O
                                   net (fanout=1)        0.039       8.387         err_flag_led     
 J16                                                                       f       err_flag_led (port)

 Data arrival time                                                   8.387         Logic Levels: 3  
                                                                                   Logic: 1.663ns(42.133%), Route: 2.284ns(57.867%)
====================================================================================================

====================================================================================================

Startpoint  : I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/CLK
Endpoint    : mem_rst_n (port)
Path Group  : **default**
Path Type   : max (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_180/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_0/CLKOUT
                                   net (fanout=1602)     0.312       4.431         _N123            
 CLMA_243_229/CLK                                                          r       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/CLK

 CLMA_243_229/CR1                  tco                   0.142       4.573 f       I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv_L6QQ_perm/L6QQ
                                   net (fanout=1)        0.703       5.276         I_ips_ddr_top/u_ddrphy_top/calib_rst
 CLMA_255_312/Y2                   td                    0.066       5.342 f       u_axi_bist_top/u_test_rd_ctrl/axi_rdata_d1[0]/opit_0_inv_L5Q_perm/L6
                                   net (fanout=1)        0.435       5.777         nt_mem_rst_n     
 IOLHR_292_300/DO_P                td                    0.353       6.130 f       mem_rst_n_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000       6.130         mem_rst_n_obuf/ntO
 IOBS_300_300/PAD                  td                    0.753       6.883 f       mem_rst_n_obuf/opit_0/O
                                   net (fanout=1)        0.092       6.975         mem_rst_n        
 T3                                                                        f       mem_rst_n (port) 

 Data arrival time                                                   6.975         Logic Levels: 3  
                                                                                   Logic: 1.314ns(51.651%), Route: 1.230ns(48.349%)
====================================================================================================

====================================================================================================

Startpoint  : heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/CLK
Endpoint    : heart_beat_led (port)
Path Group  : **default**
Path Type   : max (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------

 Clock ddrphy_sysclk (rising edge)                       0.000       0.000 r                        
 V4                                                      0.000       0.000 r       free_clk (port)  
                                   net (fanout=1)        0.098       0.098         free_clk         
 IOBD_300_162/DIN                  td                    0.660       0.758 r       free_clk_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.758         free_clk_ibuf/ntD
 IOLHR_292_162/DI_TO_CLK           td                    0.087       0.845 r       free_clk_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=4)        0.197       1.042         nt_free_clk      
 MRCKB_289_150/CLKOUT_U_P          td                    0.095       1.137 r       I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst/CLKOUT_P
                                   net (fanout=2)        0.260       1.397         I_ips_ddr_top/u_ddrphy_top/pll_refclk
 RCKB_291_150/CLKOUT               td                    0.115       1.512 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk/CLKOUT
                                   net (fanout=1)        0.300       1.812         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/ppll_clkin [0]
 PPLL_295_1/CLKOUTPHY              td                    0.039       1.851 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst/CLKOUTPHY
                                   net (fanout=36)       0.000       1.851         I_ips_ddr_top/u_ddrphy_top/phy_ioclk_fb
 DDRPHY_IOCLK_DIV_296_4/CLKOUT     td                    0.088       1.939 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst/CLKOUT
                                   net (fanout=35)       0.000       1.939         I_ips_ddr_top/u_ddrphy_top/phy_sysclk_fb
 GPLL_295_157/CLKOUT0                                    0.934       2.873 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst/CLKOUT0
                                   net (fanout=1)        0.501       3.374         I_ips_ddr_top/u_ddrphy_top/gpll_clkout0
 USCM_167_270/CLKOUT               td                    0.115       3.489 r       I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg/CLKOUT
                                   net (fanout=4)        0.397       3.886         core_clk         
 HCKB_165_200/CLKOUT               td                    0.233       4.119 r       HCKBROUTE_3/CLKOUT
                                   net (fanout=29)       0.312       4.431         _N126            
 CLMA_147_313/CLK                                                          r       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/CLK

 CLMA_147_313/Q0                   tco                   0.119       4.550 r       heart_beat_led/opit_0_inv_L6Q_LUT6DQL5_perm/L6Q
                                   net (fanout=3)        0.641       5.191         nt_heart_beat_led
 IOLHR_16_306/DO_P                 td                    0.353       5.544 r       heart_beat_led_obuf/opit_1/DO_P
                                   net (fanout=1)        0.000       5.544         heart_beat_led_obuf/ntO
 IOBS_0_306/PAD                    td                    1.145       6.689 r       heart_beat_led_obuf/opit_0/O
                                   net (fanout=1)        0.053       6.742         heart_beat_led   
 M17                                                                       r       heart_beat_led (port)

 Data arrival time                                                   6.742         Logic Levels: 2  
                                                                                   Logic: 1.617ns(69.970%), Route: 0.694ns(30.030%)
====================================================================================================

====================================================================================================

Startpoint  : uart_rxd (port)
Endpoint    : u_ips2l_uart_ctrl/u_uart_top/u_ips2l_seu_uart_rx/rxd_d[0]/opit_0_inv_srl/D
Path Group  : **default**
Path Type   : min (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 M20                                                     0.000       0.000 r       uart_rxd (port)  
                                   net (fanout=1)        0.068       0.068         uart_rxd         
 IOBS_0_384/DIN                    td                    0.445       0.513 r       uart_rxd_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.513         uart_rxd_ibuf/ntD
 IOLHR_16_384/DI_TO_CLK            td                    0.073       0.586 r       uart_rxd_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=1)        0.546       1.132         nt_uart_rxd      
 CLMA_147_378/M0                                                           r       u_ips2l_uart_ctrl/u_uart_top/u_ips2l_seu_uart_rx/rxd_d[0]/opit_0_inv_srl/D

 Data arrival time                                                   1.132         Logic Levels: 2  
                                                                                   Logic: 0.518ns(45.760%), Route: 0.614ns(54.240%)
====================================================================================================

====================================================================================================

Startpoint  : rst_board (port)
Endpoint    : u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/RS
Path Group  : **default**
Path Type   : min (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 M15                                                     0.000       0.000 r       rst_board (port) 
                                   net (fanout=1)        0.052       0.052         rst_board        
 IOBD_0_318/DIN                    td                    0.532       0.584 r       rst_board_ibuf/opit_0/O
                                   net (fanout=1)        0.000       0.584         rst_board_ibuf/ntD
 IOLHR_16_318/DI_TO_CLK            td                    0.073       0.657 r       rst_board_ibuf/opit_1/DI_TO_CLK
                                   net (fanout=2)        0.494       1.151         nt_rst_board     
 CLMA_147_307/RS                                                           r       u_free_clk_rst_sync/sig_async_r1[0]/opit_0_inv_srl/RS

 Data arrival time                                                   1.151         Logic Levels: 2  
                                                                                   Logic: 0.605ns(52.563%), Route: 0.546ns(47.437%)
====================================================================================================

====================================================================================================

Startpoint  : mem_dq[7] (port)
Endpoint    : I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L6Q_perm/I5
Path Group  : **default**
Path Type   : min (fast corner)
Path Class  : combinational timing path

 Location                          Delay Type             Incr        Path         Logical Resource 
----------------------------------------------------------------------------------------------------


 N4                                                      0.000       0.000 r       mem_dq[7] (port) 
                                   net (fanout=1)        0.079       0.079         nt_mem_dq[7]     
 IOBD_300_378/DIN                  td                    0.479       0.558 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_0/O
                                   net (fanout=1)        0.000       0.558         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/ntI
 IOLHR_292_378/DI_TO_CLK           td                    0.516       1.074 r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1/DI_TO_CLK
                                   net (fanout=2)        0.221       1.295         I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_in_dly [7]
 CLMA_285_367/B5                                                           r       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L6Q_perm/I5

 Data arrival time                                                   1.295         Logic Levels: 2  
                                                                                   Logic: 0.995ns(76.834%), Route: 0.300ns(23.166%)
====================================================================================================

{ref_clk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 19.800      20.000          0.200           High Pulse Width  CLMA_147_463/CLK        u_adc_ctrl/dbg_temp_rd_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_147_463/CLK        u_adc_ctrl/dbg_temp_rd_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           High Pulse Width  CLMA_147_462/CLK        u_adc_ctrl/dbg_temp_rd_pos_d[1]/opit_0_inv/CLK
====================================================================================================

{rst_clk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 19.800      20.000          0.200           High Pulse Width  CLMA_171_301/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_171_301/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_lock_d[0]/opit_0_inv_srl/CLK
 19.800      20.000          0.200           Low Pulse Width   CLMA_69_367/CLK         I_ips_ddr_top/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_offset_cnt[0]/opit_0_inv_L5Q_perm/CLK
====================================================================================================

{ddrphy_sysclk} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 3.609       3.809           0.200           High Pulse Width  CLMA_171_187/CLK        I_ips_ddr_top/u_ddrc_rstn_sync/sig_async_r1[0]/opit_0_srl/CLK
 3.609       3.809           0.200           High Pulse Width  CLMS_273_241/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_calib_mux/calib_address[0]/opit_0_inv_L6Q_perm/CLK
 3.609       3.809           0.200           High Pulse Width  CLMS_273_253/CLK        I_ips_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_calib_mux/calib_address[1]/opit_0_inv_L6Q_perm/CLK
====================================================================================================

{phy_dq_clk_0} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 0.011       0.476           0.465           High Pulse Width  DDR_PHY_297_159/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst/CLKA
 0.011       0.476           0.465           Low Pulse Width   DDR_PHY_297_159/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst/CLKA
 0.011       0.476           0.465           High Pulse Width  TSERDES_299_159/SERCLK  I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_tserdes_ca0/oserdes_inst/SERCLK
====================================================================================================

{phy_dq_sysclk_0} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 1.659       3.809           2.150           Low Pulse Width   DDRPHY_CPD_297_4/PPLL_SYSCLK
                                                                                       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
 1.660       3.810           2.150           High Pulse Width  DDRPHY_CPD_297_4/PPLL_SYSCLK
                                                                                       I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst/CLK_PHY
 2.209       3.809           1.600           Low Pulse Width   TSERDES_299_159/OCLKDIV I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_tserdes_ca0/oserdes_inst/OCLKDIV
====================================================================================================

{phy_dq_clk_1} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 0.011       0.476           0.465           High Pulse Width  DDR_PHY_297_307/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY/CLKA
 0.011       0.476           0.465           Low Pulse Width   DDR_PHY_297_307/PHY_CLK_B_N
                                                                                       I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY/CLKA
 0.011       0.476           0.465           Low Pulse Width   TSERDES_299_308/SERCLK  I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_tserdes0_dqs/oserdes_inst/SERCLK
====================================================================================================

{phy_dq_sysclk_1} Minimum Pulse Width :
****************************************************************************************************
 Slack       Actual Width    Require Width   Type              Location                Pin          
----------------------------------------------------------------------------------------------------
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_318/ICLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/ICLKDIV
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_318/OCLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1/OCLKDIV
 2.209       3.809           1.600           Low Pulse Width   IOLHR_292_324/ICLKDIV   I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1/ICLKDIV
====================================================================================================

====================================================================================================

Inputs and Outputs :
+--------------------------------------------------------------------------------------------------+
| Type       | File Name                                                                          
+--------------------------------------------------------------------------------------------------+
| Input      | D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/place_route/test_ddr_pnr.adf       
| Output     | D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/report_timing/test_ddr_rtp.adf     
|            | D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/report_timing/test_ddr.rtr         
|            | D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/report_timing/rtr.db               
+--------------------------------------------------------------------------------------------------+


Flow Command: report_timing -configuration 
Peak memory: 1,117 MB
Total CPU time to report_timing completion : 0h:0m:3s
Process Total CPU time to report_timing completion : 0h:0m:3s
Total real time to report_timing completion : 0h:0m:12s
