(_flow fab_demo "2016.2-SP1"
    (_comment "Compiler (version on 2016.2-SP1<build 13674>) at Sat Aug 27 11:19:56 2016")
    (_version "1.0.2")
    (_status "initial")
    (_project
        (_option prj_work_dir (_string ""))
        (_option prj_impl_dir (_string ""))
    )
    (_task tsk_setup
        (_widget wgt_select_arch
            (_input
                (_part
                    (_family Logos2)
                    (_device PG2L50H)
                    (_speedgrade -6)
                    (_package FBG484)
                )
            )
        )
        (_command cmd_load_arch
        (_gci_state (_integer 0))
        )
        (_widget wgt_my_design_src
            (_input
                (_file "../../rtl/ips2l_pcie_apb_cross_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/ips2l_pcie_apb_mux_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/ips2l_pcie_top_v1_8.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/ips2l_pcie_hard_ctrl_v1_8.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/ips2l_pcie_seio_intf_v1_2.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/ips2l_pcie_cfg_init_v1_7.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/ips2l_pcie_apb2dbi_v1_1.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/ips2l_pcie_pll_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/external_ram/rcv_data_ram/rcv_data_ram.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/external_ram/rcv_data_ram/rtl/ipm2l_sdpram_v1_0_rcv_data_ram.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/external_ram/rcv_header_ram/rcv_header_ram.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/external_ram/rcv_header_ram/rtl/ipm2l_sdpram_v1_0_rcv_header_ram.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/external_ram/retry_data_ram/retry_data_ram.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/external_ram/retry_data_ram/rtl/ipm2l_spram_v1_0_retry_data_ram.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/ips2l_pcie_soft_phy_v1_3.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsst_rst_cross_sync_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsst_rst_debounce_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsst_rst_sync_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsst_rst_wtchdg_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsstl_phy_mac_rdata_proc.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsstl_rst4mcrsw_rx_init_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_fsm_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsstl_rst4mcrsw_rx_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsstl_rst4mcrsw_tx_rst_fsm_v1_1.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsstl_rst4mcrsw_tx_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/hsstl_rst4mcrsw_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsst_pipe/ips_hsst_rst_sync_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/ipm2l_pcie_hsstlp_x1_top.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/ipm2l_pcie_hsstlp_x2_top.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/ipm2l_pcie_hsstlp_x4_top.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_apb_bridge_v1_2.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_pcie_hsstlp_wrapper_v1_6.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_fifo_clr_v1_3.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_pll_rst_fsm_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_debounce_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_pll_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_rx_v1_6.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_sync_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_tx_v1_6.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_v1_6.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rst_wtchdg_v1_0.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_rxlane_rst_fsm_v1_6.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../rtl/hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_hsstlp_txlane_rst_fsm_v1_6.v"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
                (_file "../../pcie_test.v" + "pcie_test"
                    (_format verilog)
                    (_timespec "2016-07-28T16:05:13")
                )
            )
        )
        (_widget wgt_my_ips_src
        )
        (_widget wgt_import_logic_con_file
            (_input
                (_file "pcie_test.fdc"
                    (_format fdc)
                    (_timespec "2016-07-28T16:05:13")
                )
            )
        )
        (_widget wgt_edit_user_cons
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_synthesis
        (_command cmd_synthesize
            (_gci_state (_integer 4))
            (_option ads (_switch ON))
            (_option selected_syn_tool_opt (_integer 2))
        )
    )
    (_task tsk_devmap
        (_command cmd_devmap
        (_gci_state (_integer 4))
        )
        (_widget wgt_edit_placement_cons
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_pnr
        (_command cmd_pnr
        (_gci_state (_integer 4))
        )
        (_command cmd_report_post_pnr_timing
        (_gci_state (_integer 4))
            (_attribute _auto_exe_lock (_switch OFF))
            (_option configuration (_switch ON))
        )
        (_widget wgt_arch_browser
            (_attribute _click_to_run (_switch ON))
        )
    )
    (_task tsk_gen_bitstream
        (_command cmd_gen_bitstream
        (_gci_state (_integer 4))
        )
    )
)
