file delete -force work
vlib  work
vmap  work

vlog -v work +nospecify +define+IPS2L_PCIE_SPEEDUP_SIM +define+IPM_HSST_SPEEDUP_SIM +define+DWC_DISABLE_CDC_METHOD_REPORTING -override_timescale 1ns/10ps \
     -sv -mfcu                                                                                                                                            \
     +incdir+D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/DWC_pcie_ctl_cc_constants.svh              \
     +incdir+D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include/pcie_defs.svh              \
     +incdir+D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include/cxpl_defs.svh              \
     +incdir+D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include/adm_defs.svh               \
     +incdir+D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include/radm_defs.svh              \
     +incdir+D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include/port_cfg.svh               \
     +incdir+D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include/cap_port_cfg.svh           \
     +incdir+D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include/pipe_defines.svh           \
     +incdir+D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/include/DWC_pcie_ctl_all_defs.svh  \
     +incdir+D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/power_management D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/pciegen2_source_codes/rtl/power_management/DWC_pcie_pm_pkg.svh \
     -f ./filelist_pciegen2_gtp.f                         \
     -f ./pango_pcie_top_filelist.f                       \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/hsstlp_lane_source_codes/*.vp \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/hsstlp_pll_source_codes/*.vp  \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/modelsim10.2c/common_lib/*.vp               \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/GTP_DRM18K_E1.v                             \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/GTP_CLKBUFG.v                               \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/GTP_CLKBUFGMUX.v                            \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/GTP_GPLL.v                                  \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/GTP_IOBUF.v                                 \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/GTP_HSSTLP_LANE.v                           \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/GTP_HSSTLP_PLL.v                            \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/GTP_PCIEGEN2.v                              \
     D:/DMYWdownloadsoftware/PDS/pango/PDS_2022.2-SP6.4/ip/system_ip/ips2l_pcie_gen2/ips2l_pcie_gen2_eval/ips2l_pcie_gen2/../../../../../arch/vendor/pango/verilog/simulation/GTP_GRS.v                                   \
     -l vlog.log
vopt +acc +nospecify +define+IPS2L_PCIE_SPEEDUP_SIM +define+IPM_HSST_SPEEDUP_SIM +define+DWC_DISABLE_CDC_METHOD_REPORTING work.pango_pcie_top_tb -o voptsim
vsim -c +nospecify +define+IPS2L_PCIE_SPEEDUP_SIM +define+IPM_HSST_SPEEDUP_SIM +define+DWC_DISABLE_CDC_METHOD_REPORTING voptsim -l vsim.log
do pango_pcie_top_wave.do
run -all
