#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: D:\DMYWdownloadsoftware\PDS\pango\PDS_2022.2-SP6.4\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.26100
#Hostname: LAPTOP-E50OTCNR
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Wed Nov  5 00:15:51 2025
License checkout: fabric_ads from D:\DMYWdownloadsoftware\PDS\license\new_pds_F4A80DA47D72.lic
Compiling verification operator library.
Compiling common defs.
Loading technology operator library.
Compiling technology operator library.
Compiling technology operator (valence) library.
Reading design from compile DB
Reading design from compile DB successfully.
Constraint check start.
Compiling prim grid devices.
Building architecture model.
Loading device packaging model.
Building architecture floorplan logic view.
Executing : get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY.pclk
Executing : get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY.pclk successfully.
Executing : create_clock -name pclk [get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY.pclk] -period 4.000 -waveform {0.000 2.000}
Executing : create_clock -name pclk [get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY.pclk] -period 4.000 -waveform {0.000 2.000} successfully.
Executing : get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY.pclk_div2
Executing : get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY.pclk_div2 successfully.
Executing : create_clock -name pclk_div2 [get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY.pclk_div2] -period 8.000 -waveform {0.000 4.000}
Executing : create_clock -name pclk_div2 [get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY.pclk_div2] -period 8.000 -waveform {0.000 4.000} successfully.
Executing : get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_REFCK2CORE_0
Executing : get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_REFCK2CORE_0 successfully.
Executing : create_clock -name ref_clk [get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_REFCK2CORE_0] -period 10.000 -waveform {0.000 5.000}
Executing : create_clock -name ref_clk [get_pins u_ips2l_pcie_wrap.U_IPS2L_PCIE_TOP.U_IPS2L_HSSTLP_PCIE_SOFT_PHY/P_REFCK2CORE_0] -period 10.000 -waveform {0.000 5.000} successfully.
Executing : get_clocks pclk
Executing : get_clocks pclk successfully.
Executing : set_clock_groups -name group_1 -asynchronous -group [get_clocks pclk]
Executing : set_clock_groups -name group_1 -asynchronous -group [get_clocks pclk] successfully.
Executing : get_clocks pclk_div2
Executing : get_clocks pclk_div2 successfully.
Executing : set_clock_groups -name group_2 -asynchronous -group [get_clocks pclk_div2]
Executing : set_clock_groups -name group_2 -asynchronous -group [get_clocks pclk_div2] successfully.
Executing : get_clocks ref_clk
Executing : get_clocks ref_clk successfully.
Executing : set_clock_groups -name group_3 -asynchronous -group [get_clocks ref_clk]
Executing : set_clock_groups -name group_3 -asynchronous -group [get_clocks ref_clk] successfully.
Executing : get_ports sys_clk
Executing : get_ports sys_clk successfully.
Executing : create_clock -name sys_clk [get_ports sys_clk] -period 40.000 -waveform {0.000 20.000}
Executing : create_clock -name sys_clk [get_ports sys_clk] -period 40.000 -waveform {0.000 20.000} successfully.
Executing : get_ports cmos1_pclk
Executing : get_ports cmos1_pclk successfully.
Executing : create_clock -name cmos1_pclk [get_ports cmos1_pclk] -period 23.810 -waveform {0.000 11.905}
Executing : create_clock -name cmos1_pclk [get_ports cmos1_pclk] -period 23.810 -waveform {0.000 11.905} successfully.
Executing : get_ports cmos2_pclk
Executing : get_ports cmos2_pclk successfully.
Executing : create_clock -name cmos2_pclk [get_ports cmos2_pclk] -period 23.810 -waveform {0.000 11.905}
Executing : create_clock -name cmos2_pclk [get_ports cmos2_pclk] -period 23.810 -waveform {0.000 11.905} successfully.
Executing : get_ports sys_clk
Executing : get_ports sys_clk successfully.
Executing : get_pins u_ddr3.u_ddrphy_top.rst_clk_gpll/clkout0
Executing : get_pins u_ddr3.u_ddrphy_top.rst_clk_gpll/clkout0 successfully.
Executing : get_clocks sys_clk
Executing : get_clocks sys_clk successfully.
Executing : create_generated_clock -name rst_clk -source [get_ports sys_clk] [get_pins u_ddr3.u_ddrphy_top.rst_clk_gpll/clkout0] -master_clock [get_clocks sys_clk] -multiply_by 84 -divide_by 84
Executing : create_generated_clock -name rst_clk -source [get_ports sys_clk] [get_pins u_ddr3.u_ddrphy_top.rst_clk_gpll/clkout0] -master_clock [get_clocks sys_clk] -multiply_by 84 -divide_by 84 successfully.
Executing : get_ports sys_clk
Executing : get_ports sys_clk successfully.
Executing : get_pins u_ddr3.u_ddrphy_top.ddrphy_gpll/clkout0
Executing : get_pins u_ddr3.u_ddrphy_top.ddrphy_gpll/clkout0 successfully.
Executing : get_clocks sys_clk
Executing : get_clocks sys_clk successfully.
Executing : create_generated_clock -name ddrphy_sysclk -source [get_ports sys_clk] [get_pins u_ddr3.u_ddrphy_top.ddrphy_gpll/clkout0] -master_clock [get_clocks sys_clk] -multiply_by 84 -divide_by 16
Executing : create_generated_clock -name ddrphy_sysclk -source [get_ports sys_clk] [get_pins u_ddr3.u_ddrphy_top.ddrphy_gpll/clkout0] -master_clock [get_clocks sys_clk] -multiply_by 84 -divide_by 16 successfully.
Executing : get_ports sys_clk
Executing : get_ports sys_clk successfully.
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy} successfully.
Executing : get_clocks sys_clk
Executing : get_clocks sys_clk successfully.
Executing : create_generated_clock -name phy_dq_clk_0 -source [get_ports sys_clk] [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks sys_clk] -multiply_by 84 -divide_by 2
Executing : create_generated_clock -name phy_dq_clk_0 -source [get_ports sys_clk] [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks sys_clk] -multiply_by 84 -divide_by 2 successfully.
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy} successfully.
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT}
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT} successfully.
Executing : get_clocks phy_dq_clk_0
Executing : get_clocks phy_dq_clk_0 successfully.
Executing : create_generated_clock -name phy_dq_sysclk_0 -source [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_0] -edges {5 13 21} -edge_shift {0 0 0}
Executing : create_generated_clock -name phy_dq_sysclk_0 -source [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_0] -edges {5 13 21} -edge_shift {0 0 0} successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_0
Executing : get_clocks phy_dq_sysclk_0 successfully.
Executing : set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0]
Executing : set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0] successfully.
Executing : get_ports sys_clk
Executing : get_ports sys_clk successfully.
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy} successfully.
Executing : get_clocks sys_clk
Executing : get_clocks sys_clk successfully.
Executing : create_generated_clock -name phy_dq_clk_1 -source [get_ports sys_clk] [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks sys_clk] -multiply_by 84 -divide_by 2
Executing : create_generated_clock -name phy_dq_clk_1 -source [get_ports sys_clk] [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks sys_clk] -multiply_by 84 -divide_by 2 successfully.
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy} successfully.
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT}
Executing : get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT} successfully.
Executing : get_clocks phy_dq_clk_1
Executing : get_clocks phy_dq_clk_1 successfully.
Executing : create_generated_clock -name phy_dq_sysclk_1 -source [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_1] -edges {5 13 21} -edge_shift {0 0 0}
Executing : create_generated_clock -name phy_dq_sysclk_1 -source [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] [get_pins {u_ddr3.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_1] -edges {5 13 21} -edge_shift {0 0 0} successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_1
Executing : get_clocks phy_dq_sysclk_1 successfully.
Executing : set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1]
Executing : set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1] successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_0
Executing : get_clocks phy_dq_sysclk_0 successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0] -setup -hold
Executing : set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0] -setup -hold successfully.
Executing : get_clocks phy_dq_sysclk_0
Executing : get_clocks phy_dq_sysclk_0 successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_0] -to [get_clocks ddrphy_sysclk] -setup -hold
Executing : set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_0] -to [get_clocks ddrphy_sysclk] -setup -hold successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_1
Executing : get_clocks phy_dq_sysclk_1 successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1] -setup -hold
Executing : set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1] -setup -hold successfully.
Executing : get_clocks phy_dq_sysclk_1
Executing : get_clocks phy_dq_sysclk_1 successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_1] -to [get_clocks ddrphy_sysclk] -setup -hold
Executing : set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_1] -to [get_clocks ddrphy_sysclk] -setup -hold successfully.
Executing : get_clocks rst_clk
Executing : get_clocks rst_clk successfully.
Executing : set_clock_groups -name rst_clk -asynchronous -group [get_clocks rst_clk]
Executing : set_clock_groups -name rst_clk -asynchronous -group [get_clocks rst_clk] successfully.
Executing : get_clocks phy_dq_clk_0
Executing : get_clocks phy_dq_clk_0 successfully.
Executing : set_clock_groups -name phy_dq_clk_0 -asynchronous -group [get_clocks phy_dq_clk_0]
Executing : set_clock_groups -name phy_dq_clk_0 -asynchronous -group [get_clocks phy_dq_clk_0] successfully.
Executing : get_clocks phy_dq_clk_1
Executing : get_clocks phy_dq_clk_1 successfully.
Executing : set_clock_groups -name phy_dq_clk_1 -asynchronous -group [get_clocks phy_dq_clk_1]
Executing : set_clock_groups -name phy_dq_clk_1 -asynchronous -group [get_clocks phy_dq_clk_1] successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : set_clock_groups -name ddrphy_sysclk -asynchronous -group [get_clocks ddrphy_sysclk]
Executing : set_clock_groups -name ddrphy_sysclk -asynchronous -group [get_clocks ddrphy_sysclk] successfully.
Executing : get_ports cmos1_pclk
Executing : get_ports cmos1_pclk successfully.
Executing : get_pins cmos1_8_16bit/pixel_clk
Executing : get_pins cmos1_8_16bit/pixel_clk successfully.
Executing : get_clocks cmos1_pclk
Executing : get_clocks cmos1_pclk successfully.
Executing : create_generated_clock -name cmos1_pclk_16bit -source [get_ports cmos1_pclk] [get_pins cmos1_8_16bit/pixel_clk] -master_clock [get_clocks cmos1_pclk] -multiply_by 1 -divide_by 2
Executing : create_generated_clock -name cmos1_pclk_16bit -source [get_ports cmos1_pclk] [get_pins cmos1_8_16bit/pixel_clk] -master_clock [get_clocks cmos1_pclk] -multiply_by 1 -divide_by 2 successfully.
Executing : get_ports cmos2_pclk
Executing : get_ports cmos2_pclk successfully.
Executing : get_pins cmos2_8_16bit/pixel_clk
Executing : get_pins cmos2_8_16bit/pixel_clk successfully.
Executing : get_clocks cmos2_pclk
Executing : get_clocks cmos2_pclk successfully.
Executing : create_generated_clock -name cmos2_pclk_16bit -source [get_ports cmos2_pclk] [get_pins cmos2_8_16bit/pixel_clk] -master_clock [get_clocks cmos2_pclk] -multiply_by 1 -divide_by 2
Executing : create_generated_clock -name cmos2_pclk_16bit -source [get_ports cmos2_pclk] [get_pins cmos2_8_16bit/pixel_clk] -master_clock [get_clocks cmos2_pclk] -multiply_by 1 -divide_by 2 successfully.
Executing : get_clocks cmos1_pclk
Executing : get_clocks cmos1_pclk successfully.
Executing : set_clock_groups -name cmos1_pclk -asynchronous -group [get_clocks cmos1_pclk]
Executing : set_clock_groups -name cmos1_pclk -asynchronous -group [get_clocks cmos1_pclk] successfully.
Executing : get_clocks cmos1_pclk_16bit
Executing : get_clocks cmos1_pclk_16bit successfully.
Executing : set_clock_groups -name cmos1_pclk_16bit -asynchronous -group [get_clocks cmos1_pclk_16bit]
Executing : set_clock_groups -name cmos1_pclk_16bit -asynchronous -group [get_clocks cmos1_pclk_16bit] successfully.
Executing : get_clocks cmos2_pclk
Executing : get_clocks cmos2_pclk successfully.
Executing : set_clock_groups -name cmos2_pclk -asynchronous -group [get_clocks cmos2_pclk]
Executing : set_clock_groups -name cmos2_pclk -asynchronous -group [get_clocks cmos2_pclk] successfully.
Executing : get_clocks cmos2_pclk_16bit
Executing : get_clocks cmos2_pclk_16bit successfully.
Executing : set_clock_groups -name cmos2_pclk_16bit -asynchronous -group [get_clocks cmos2_pclk_16bit]
Executing : set_clock_groups -name cmos2_pclk_16bit -asynchronous -group [get_clocks cmos2_pclk_16bit] successfully.
Executing : get_clocks cmos1_pclk_16bit
Executing : get_clocks cmos1_pclk_16bit successfully.
Executing : set_clock_uncertainty 0.200 [get_clocks cmos1_pclk_16bit] -setup -hold
Executing : set_clock_uncertainty 0.200 [get_clocks cmos1_pclk_16bit] -setup -hold successfully.
Executing : get_clocks cmos2_pclk_16bit
Executing : get_clocks cmos2_pclk_16bit successfully.
Executing : set_clock_uncertainty 0.200 [get_clocks cmos2_pclk_16bit] -setup -hold
Executing : set_clock_uncertainty 0.200 [get_clocks cmos2_pclk_16bit] -setup -hold successfully.
Executing : get_clocks cmos1_pclk
Executing : get_clocks cmos1_pclk successfully.
Executing : set_clock_uncertainty 0.200 [get_clocks cmos1_pclk] -setup -hold
Executing : set_clock_uncertainty 0.200 [get_clocks cmos1_pclk] -setup -hold successfully.
Executing : get_clocks cmos2_pclk
Executing : get_clocks cmos2_pclk successfully.
Executing : set_clock_uncertainty 0.200 [get_clocks cmos2_pclk] -setup -hold
Executing : set_clock_uncertainty 0.200 [get_clocks cmos2_pclk] -setup -hold successfully.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 46)] | Port button_rst_n has been placed at location M15, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 68)] | Port perst_n has been placed at location M16, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 77)] | Port i2c_sda has been placed at location R19, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 84)] | Port i2c_scl has been placed at location P19, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 94)] | Port cmos1_data[7] has been placed at location AB21, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 104)] | Port cmos1_data[5] has been placed at location AB22, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 109)] | Port cmos1_data[4] has been placed at location L13, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 119)] | Port cmos1_data[2] has been placed at location AB20, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 124)] | Port cmos1_data[1] has been placed at location AA19, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 134)] | Port cmos2_data[7] has been placed at location AB18, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 139)] | Port cmos2_data[6] has been placed at location P17, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 154)] | Port cmos2_data[3] has been placed at location P15, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 159)] | Port cmos2_data[2] has been placed at location R16, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 169)] | Port cmos2_data[0] has been placed at location U17, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 174)] | Port cmos1_scl has been placed at location R14, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 181)] | Port cmos1_sda has been placed at location P14, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 209)] | Port cmos2_reset has been placed at location AA21, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 221)] | Port cmos1_pclk has been placed at location T18, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 226)] | Port cmos1_vsync has been placed at location W17, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 231)] | Port cmos2_href has been placed at location U18, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 236)] | Port cmos2_pclk has been placed at location P16, whose type is share pin.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 241)] | Port cmos2_vsync has been placed at location R17, whose type is share pin.
W: ConstraintEditor-4019: Port Bus 'rxn' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'rxp' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'txn' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'txp' unspecified I/O constraint.
Constraint check end.

C: SDC-2025: Clock source 'n:u_PLL/clkout0' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
Executing : get_ports sys_clk
Executing : get_ports sys_clk successfully.
Executing : get_pins u_PLL/u_gpll:CLKOUT0
Executing : get_pins u_PLL/u_gpll:CLKOUT0 successfully.
Executing : create_generated_clock -name sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred -source [get_ports sys_clk] [get_pins u_PLL/u_gpll:CLKOUT0] -master_clock sys_clk -edges {1 2 3} -edge_shift {0.000000 -15.000000 -30.000000} -add
Executing : create_generated_clock -name sys_clk|u_PLL/u_gpll/CLKOUT0_Inferred -source [get_ports sys_clk] [get_pins u_PLL/u_gpll:CLKOUT0] -master_clock sys_clk -edges {1 2 3} -edge_shift {0.000000 -15.000000 -30.000000} -add successfully.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg0[0]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg0[1]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg0[2]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg0[3]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg0[4]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg0[5]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg0[6]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg0[7]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg1[0]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg1[1]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg1[2]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg1[3]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg1[4]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg1[5]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg1[6]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:i2cSlave_u/u_registerInterface/myReg1[7]' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: DRC-2018: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 678)] The waveform of clock "phy_dq_clk_0" is {0.000, 0.476, 0.952} in sdc, but according config of instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll(GTP_PPLL) and reference clock "sys_clk", the waveform of clock "phy_dq_clk_0" should be {0.000, 0.625, 1.250}, please check the constraint.
C: DRC-2018: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 684)] The waveform of clock "phy_dq_clk_1" is {0.000, 0.476, 0.952} in sdc, but according config of instance u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll(GTP_PPLL) and reference clock "sys_clk", the waveform of clock "phy_dq_clk_1" should be {0.000, 0.625, 1.250}, please check the constraint.
C: DRC-2018: [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/fdc/pcie_dma_test.fdc(line number: 676)] The waveform of clock "ddrphy_sysclk" is {0.000, 3.809, 7.619} in sdc, but according config of instance u_ddr3/u_ddrphy_top/ddrphy_gpll/u_gpll(GTP_GPLL) and reference clock "sys_clk", the waveform of clock "ddrphy_sysclk" should be {0.000, 5.000, 10.000}, please check the constraint.
C: SDC-2025: Clock source 'n:u_PLL/clkout1' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
Executing : get_ports sys_clk
Executing : get_ports sys_clk successfully.
Executing : get_pins u_PLL/u_gpll:CLKOUT1
Executing : get_pins u_PLL/u_gpll:CLKOUT1 successfully.
Executing : create_generated_clock -name sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred -source [get_ports sys_clk] [get_pins u_PLL/u_gpll:CLKOUT1] -master_clock sys_clk -edges {1 2 3} -edge_shift {0.000000 -10.000000 -20.000000} -add
Executing : create_generated_clock -name sys_clk|u_PLL/u_gpll/CLKOUT1_Inferred -source [get_ports sys_clk] [get_pins u_PLL/u_gpll:CLKOUT1] -master_clock sys_clk -edges {1 2 3} -edge_shift {0.000000 -10.000000 -20.000000} -add successfully.
C: SDC-2025: Clock source 'n:coms2_reg_config/clock_20k' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:coms1_reg_config/clock_20k' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:cmos2_8_16bit/pclk_IOCLKBUF' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
C: SDC-2025: Clock source 'n:cmos1_8_16bit/pclk_IOCLKBUF' need a clock constraint, please use 'create_clock' or 'create_generate_clock' to generate.
Start pre-mapping.
W: Removed bmsWIDEDFFCPE inst buf_cnt[2:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst buf_cnt[2:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst buf_cnt[2:0] at 2 that is stuck at constant 0.
I: Constant propagation done on buf_cnt[2:0] (bmsWIDEDFFCPE).
W: Removed bmsWIDEDFFCPE inst cmos1_vsync_d1 that is stuck at constant 0.
I: Constant propagation done on cmos1_vsync_d1 (bmsWIDEDFFCPE).
W: Removed bmsWIDEDFFCPE inst cmos1_vsync_neg that is stuck at constant 0.
I: Constant propagation done on cmos1_vsync_neg (bmsWIDEDFFCPE).
W: Removed bmsWIDEDFFCPE inst cmos1_vsync_pos that is stuck at constant 0.
I: Constant propagation done on cmos1_vsync_pos (bmsWIDEDFFCPE).
W: Removed bmsWIDEDFFCPE inst cmos1_vsync_pos_1_dly that is stuck at constant 0.
I: Constant propagation done on cmos1_vsync_pos_1_dly (bmsWIDEDFFCPE).
W: Removed bmsWIDEDFFCPE inst cmos1_vsync_pos_cnt[3:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst cmos1_vsync_pos_cnt[3:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst cmos1_vsync_pos_cnt[3:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst cmos1_vsync_pos_cnt[3:0] at 3 that is stuck at constant 0.
I: Constant propagation done on cmos1_vsync_pos_cnt[3:0] (bmsWIDEDFFCPE).
W: Removed bmsWIDEDFFCPE inst cmos1_vsync_start_en that is stuck at constant 0.
I: Constant propagation done on cmos1_vsync_start_en (bmsWIDEDFFCPE).
W: Removed bmsWIDEDFFRSE inst counter_24bit_end that is stuck at constant 0.
I: Constant propagation done on counter_24bit_end (bmsWIDEDFFRSE).
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 9 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 11 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 12 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 13 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 14 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 15 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 16 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 17 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 18 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 19 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 20 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 21 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 22 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[23:0] at 23 that is stuck at constant 0.
I: Constant propagation done on data_buf_128[23:0] (bmsWIDEDFFCPE).
W: Removed bmsWIDEDFFCPE inst data_buf_128[31:24] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[31:24] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[31:24] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[31:24] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[31:24] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[31:24] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[31:24] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[31:24] at 7 that is stuck at constant 0.
I: Constant propagation done on data_buf_128[31:24] (bmsWIDEDFFCPE).
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 9 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 11 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 12 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 13 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 14 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 15 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 16 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 17 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 18 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 19 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 20 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 21 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 22 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[55:32] at 23 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[63:56] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[63:56] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[63:56] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[63:56] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[63:56] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[63:56] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[63:56] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[63:56] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 9 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 11 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 12 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 13 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 14 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 15 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 16 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 17 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 18 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 19 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 20 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 21 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 22 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[87:64] at 23 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[95:88] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[95:88] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[95:88] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[95:88] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[95:88] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[95:88] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[95:88] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[95:88] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 9 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 11 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 12 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 13 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 14 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 15 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 16 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 17 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 18 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 19 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 20 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 21 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 22 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[119:96] at 23 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[127:120] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[127:120] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[127:120] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[127:120] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[127:120] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[127:120] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[127:120] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst data_buf_128[127:120] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_axi_arvalid_en that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst ddr_axi_awvalid_en that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst ddr_axi_awvalid_en_end that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_axi_awvalid_en_neg that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 9 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 11 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 12 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 13 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 14 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 15 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 16 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 17 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 18 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 19 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 20 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 21 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 22 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 23 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 24 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_rd_cnt_26[25:0] at 25 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 9 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 11 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 12 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 13 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_trans_cnt[14:0] at 14 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 9 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 11 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 12 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 13 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 14 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 15 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 16 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 17 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 18 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 19 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 20 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 21 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 22 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 23 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 24 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst ddr_wr_cnt_26[25:0] at 25 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst fifo_fill_byte[7:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst fifo_fill_byte[7:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst fifo_fill_byte[7:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst fifo_fill_byte[7:0] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst fifo_fill_byte[7:0] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst fifo_fill_byte[7:0] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst fifo_fill_byte[7:0] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst fifo_fill_byte[7:0] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst fifo_rd_en_early that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst fifo_rd_en_early_reg that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst sync_cmos1_vsync_pos_1[1:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst sync_cmos1_vsync_pos_1[1:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst wr_flag[3:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst wr_flag[3:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst wr_flag[3:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst wr_flag[3:0] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst wr_rst_sync[1:0] at 0 that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst wr_rst_sync[1:0] at 1 that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst ddr_axi_awvalid_en_d1 that is stuck at constant 0.
W: pmux inst 'N825_1' has no active select, tie output to 0
W: Adm-4019: Unable to further flatten instance 'U_IPM2L_HSSTLP_RST'. The design is empty.
W: Public-4008: Instance 'cmos1_vsync_pos_1' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
I: Removed bmsSUB inst N70 that is redundant to N69
I: Removed bmsSUB inst N61 that is redundant to N60
I: Removed bmsSUB inst N61 that is redundant to N60
I: Removed bmsSUB inst N70 that is redundant to N69
I: Removed bmsSUB inst N70 that is redundant to N69
I: Removed bmsSUB inst N61 that is redundant to N60
I: Removed bmsSUB inst N70 that is redundant to N69
I: Removed bmsSUB inst N61 that is redundant to N60
I: Removed bmsSUB inst N70 that is redundant to N69
I: Removed bmsSUB inst N61 that is redundant to N60
I: Removed bmsSUB inst N70 that is redundant to N69
I: Removed bmsSUB inst N61 that is redundant to N60
I: Encoding type of FSM 'blk_state_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'blk_state_fsm[1:0]':
I: from  blk_state[1] blk_state[0]
I: to  blk_state_reg[3] blk_state_reg[2] blk_state_reg[1] blk_state_reg[0]
I: 00 => 0001
I: 01 => 0010
I: 10 => 0100
I: 11 => 1000
I: Encoding type of FSM 'curr_rd_reg_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'curr_rd_reg_fsm[1:0]':
I: from  curr_rd_reg[1] curr_rd_reg[0]
I: to  curr_rd_reg_reg[3] curr_rd_reg_reg[2] curr_rd_reg_reg[1] curr_rd_reg_reg[0]
I: 00 => 0001
I: 01 => 0010
I: 10 => 0100
I: 11 => 1000
I: Encoding type of FSM 'init_state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'init_state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[0]
I: 0000 => 0000000001
I: 0001 => 0000000010
I: 0010 => 0000000100
I: 0011 => 0000001000
I: 0100 => 0000010000
I: 0101 => 0000100000
I: 0110 => 0001000000
I: 0111 => 0010000000
I: 1000 => 0100000000
I: 1001 => 1000000000
I: Encoding type of FSM 'error_status_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'error_status_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg[0]
I: 0000 => 0000001
I: 0001 => 0000010
I: 0010 => 0000100
I: 0011 => 0001000
I: 0100 => 0010000
I: 0101 => 0100000
I: 0110 => 1000000
I: Encoding type of FSM 'main_state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'main_state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[0]
I: 0000 => 00000001
I: 0001 => 00000010
I: 0010 => 00000100
I: 0011 => 00001000
I: 0100 => 00010000
I: 0101 => 00100000
I: 0110 => 01000000
I: 0111 => 10000000
I: Encoding type of FSM 'genblk1.rdcal_state_fsm[4:0]' is: onehot.
I: Encoding table of FSM 'genblk1.rdcal_state_fsm[4:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[19] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[18] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[17] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[16] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[15] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[14] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[13] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[12] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[11] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_rdcal/genblk1.rdcal_state_reg[0]
I: 00000 => 00000000000000000001
I: 00001 => 00000000000000000010
I: 00010 => 00000000000000000100
I: 00011 => 00000000000000001000
I: 00100 => 00000000000000010000
I: 00101 => 00000000000000100000
I: 00110 => 00000000000001000000
I: 00111 => 00000000000010000000
I: 01000 => 00000000000100000000
I: 01001 => 00000000001000000000
I: 01010 => 00000000010000000000
I: 01011 => 00000000100000000000
I: 01100 => 00000001000000000000
I: 01101 => 00000010000000000000
I: 01110 => 00000100000000000000
I: 01111 => 00001000000000000000
I: 10000 => 00010000000000000000
I: 10001 => 00100000000000000000
I: 10010 => 01000000000000000000
I: 10011 => 10000000000000000000
I: Encoding type of FSM 'upcal_state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'upcal_state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_upcal/upcal_state_reg[0]
I: 0000 => 001
I: 0001 => 010
I: 0010 => 100
I: Encoding type of FSM 'wrcal_state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'wrcal_state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_state_reg[0]
I: 0000 => 00000001
I: 0001 => 00000010
I: 0010 => 00000100
I: 0011 => 00001000
I: 0100 => 00010000
I: 0101 => 00100000
I: 1001 => 01000000
I: 1010 => 10000000
I: Encoding type of FSM 'wrlvl_state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'wrlvl_state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]
I: 0000 => 000000001
I: 0001 => 000000010
I: 0010 => 000000100
I: 0011 => 000001000
I: 0100 => 000010000
I: 0101 => 000100000
I: 0110 => 001000000
I: 0111 => 010000000
I: 1000 => 100000000
I: Encoding type of FSM 'eyecal_state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'eyecal_state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_state_reg[0]
I: 0000 => 0000000001
I: 0001 => 0000000010
I: 0010 => 0000000100
I: 0011 => 0000001000
I: 0100 => 0000010000
I: 0101 => 0000100000
I: 0110 => 0001000000
I: 0111 => 0010000000
I: 1000 => 0100000000
I: 1001 => 1000000000
I: Encoding type of FSM 'cpd_state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'cpd_state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state[3] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state[2] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state[1] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/cpd_state_reg[0]
I: 0000 => 0000000001
I: 0001 => 0000000010
I: 0010 => 0000000100
I: 0011 => 0000001000
I: 0100 => 0000010000
I: 0101 => 0000100000
I: 0110 => 0001000000
I: 0111 => 0010000000
I: 1000 => 0100000000
I: 1001 => 1000000000
I: Encoding type of FSM 'state_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[1:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state[1] u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]
I: 00 => 0001
I: 01 => 0010
I: 10 => 0100
I: 11 => 1000
I: Encoding type of FSM 'state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state[3] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state[2] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state[1] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]
I: 0000 => 00000000001
I: 0001 => 00000000010
I: 0010 => 00000000100
I: 0011 => 00000001000
I: 0100 => 00000010000
I: 0101 => 00000100000
I: 0110 => 00001000000
I: 0111 => 00010000000
I: 1000 => 00100000000
I: 1001 => 01000000000
I: 1010 => 10000000000
I: Encoding type of FSM 'gate_state_fsm[2:0]' is: onehot.
I: Encoding table of FSM 'gate_state_fsm[2:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[0]
I: 000 => 000001
I: 001 => 000010
I: 010 => 000100
I: 011 => 001000
I: 100 => 010000
I: 101 => 100000
I: Encoding type of FSM 'state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[13] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[12] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[11] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[0]
I: 0000 => 00000000000001
I: 0001 => 00000000000010
I: 0010 => 00000000000100
I: 0011 => 00000000001000
I: 0100 => 00000000010000
I: 0101 => 00000000100000
I: 0110 => 00000001000000
I: 0111 => 00000010000000
I: 1000 => 00000100000000
I: 1001 => 00001000000000
I: 1010 => 00010000000000
I: 1011 => 00100000000000
I: 1100 => 01000000000000
I: 1101 => 10000000000000
I: Encoding type of FSM 'wl_state_fsm[2:0]' is: onehot.
I: Encoding table of FSM 'wl_state_fsm[2:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[0]
I: 000 => 0000001
I: 001 => 0000010
I: 010 => 0000100
I: 011 => 0001000
I: 100 => 0010000
I: 101 => 0100000
I: 110 => 1000000
I: Encoding type of FSM 'gdet_state_fsm[2:0]' is: onehot.
I: Encoding table of FSM 'gdet_state_fsm[2:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[0]
I: 000 => 00001
I: 001 => 00010
I: 010 => 00100
I: 011 => 01000
I: 100 => 10000
I: Encoding type of FSM 'rdchk_state1_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'rdchk_state1_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[0]
I: 0000 => 0000001
I: 0001 => 0000010
I: 0010 => 0000100
I: 0011 => 0001000
I: 0100 => 0010000
I: 0101 => 0100000
I: 0110 => 1000000
I: Encoding type of FSM 'rdchk_state0_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'rdchk_state0_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[0]
I: 0000 => 0000001
I: 0001 => 0000010
I: 0010 => 0000100
I: 0011 => 0001000
I: 0100 => 0010000
I: 0101 => 0100000
I: 0110 => 1000000
I: Encoding type of FSM 'state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[11] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[0]
I: 0000 => 000000000001
I: 0001 => 000000000010
I: 0010 => 000000000100
I: 0011 => 000000001000
I: 0100 => 000000010000
I: 0101 => 000000100000
I: 0110 => 000001000000
I: 0111 => 000010000000
I: 1000 => 000100000000
I: 1001 => 001000000000
I: 1010 => 010000000000
I: 1011 => 100000000000
I: Encoding type of FSM 'gate_state_fsm[2:0]' is: onehot.
I: Encoding table of FSM 'gate_state_fsm[2:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_state_reg[0]
I: 000 => 000001
I: 001 => 000010
I: 010 => 000100
I: 011 => 001000
I: 100 => 010000
I: 101 => 100000
I: Encoding type of FSM 'state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[13] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[12] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[11] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/state_reg[0]
I: 0000 => 00000000000001
I: 0001 => 00000000000010
I: 0010 => 00000000000100
I: 0011 => 00000000001000
I: 0100 => 00000000010000
I: 0101 => 00000000100000
I: 0110 => 00000001000000
I: 0111 => 00000010000000
I: 1000 => 00000100000000
I: 1001 => 00001000000000
I: 1010 => 00010000000000
I: 1011 => 00100000000000
I: 1100 => 01000000000000
I: 1101 => 10000000000000
I: Encoding type of FSM 'wl_state_fsm[2:0]' is: onehot.
I: Encoding table of FSM 'wl_state_fsm[2:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/wl_state_reg[0]
I: 000 => 0000001
I: 001 => 0000010
I: 010 => 0000100
I: 011 => 0001000
I: 100 => 0010000
I: 101 => 0100000
I: 110 => 1000000
I: Encoding type of FSM 'gdet_state_fsm[2:0]' is: onehot.
I: Encoding table of FSM 'gdet_state_fsm[2:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/gdet_state_reg[0]
I: 000 => 00001
I: 001 => 00010
I: 010 => 00100
I: 011 => 01000
I: 100 => 10000
I: Encoding type of FSM 'rdchk_state1_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'rdchk_state1_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state1_reg[0]
I: 0000 => 0000001
I: 0001 => 0000010
I: 0010 => 0000100
I: 0011 => 0001000
I: 0100 => 0010000
I: 0101 => 0100000
I: 0110 => 1000000
I: Encoding type of FSM 'rdchk_state0_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'rdchk_state0_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqs_rddata_align/rdchk_state0_reg[0]
I: 0000 => 0000001
I: 0001 => 0000010
I: 0010 => 0000100
I: 0011 => 0001000
I: 0100 => 0010000
I: 0101 => 0100000
I: 0110 => 1000000
I: Encoding type of FSM 'state_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[3:0]':
I: from  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state[0]
I: to  u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[11] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[10] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[9] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[8] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[7] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[6] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[5] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[4] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[3] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[2] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[1] u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_dqsi_rdel_cal/state_reg[0]
I: 0000 => 000000000001
I: 0001 => 000000000010
I: 0010 => 000000000100
I: 0011 => 000000001000
I: 0100 => 000000010000
I: 0101 => 000000100000
I: 0110 => 000001000000
I: 0111 => 000010000000
I: 1000 => 000100000000
I: 1001 => 001000000000
I: 1010 => 010000000000
I: 1011 => 100000000000
I: Encoding type of FSM 'cpd_state_fsm[2:0]' is: onehot.
I: Encoding table of FSM 'cpd_state_fsm[2:0]':
I: from  u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state[2] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state[1] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state[0]
I: to  u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state_reg[4] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state_reg[3] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state_reg[2] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state_reg[1] u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/cpd_state_reg[0]
I: 000 => 00001
I: 001 => 00010
I: 010 => 00100
I: 011 => 01000
I: 100 => 10000
I: Encoding type of FSM 'cstate_fsm[5:0]' is: onehot.
I: Encoding table of FSM 'cstate_fsm[5:0]':
I: from  u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[5] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[4] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[3] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[2] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[1] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate[0]
I: to  u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[5] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[4] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[3] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[2] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/cstate_reg[0]
I: 000001 => 000001
I: 000010 => 000010
I: 000100 => 000100
I: 001000 => 001000
I: 010000 => 010000
I: 100000 => 100000
I: Encoding type of FSM 'mode_state_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'mode_state_fsm[1:0]':
I: from  u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state[1] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state[0]
I: to  u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state_reg[3] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state_reg[2] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state_reg[0]
I: 00 => 0001
I: 01 => 0010
I: 10 => 0100
I: 11 => 1000
I: Encoding type of FSM 'dcp2dfi_odt_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'dcp2dfi_odt_fsm[1:0]':
I: from  u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt[1] u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt[0]
I: to  u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]
I: 00 => 01
I: 11 => 10
I: Encoding type of FSM 'dcp2dfi_odt_fsm[3:2]' is: onehot.
I: Encoding table of FSM 'dcp2dfi_odt_fsm[3:2]':
I: from  u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt[3] u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt[2]
I: to  u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]
I: 00 => 01
I: 11 => 10
I: Encoding type of FSM 'state_fsm[9:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[9:0]':
I: from  u_ddr3/u_ips_ddrc_top/mcdq_lp/state[9] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[8] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[7] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[6] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[5] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[4] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[3] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[2] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[1] u_ddr3/u_ips_ddrc_top/mcdq_lp/state[0]
I: to  u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[9] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[8] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[7] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[6] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[5] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[4] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[3] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[2] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_lp/state_reg[0]
I: 0000000001 => 0000000001
I: 0000000010 => 0000000010
I: 0000000100 => 0000000100
I: 0000001000 => 0000001000
I: 0000010000 => 0000010000
I: 0000100000 => 0000100000
I: 0001000000 => 0001000000
I: 0010000000 => 0010000000
I: 0100000000 => 0100000000
I: 1000000000 => 1000000000
I: Encoding type of FSM 'state_fsm[6:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[6:0]':
I: from  u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[6] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[5] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[4] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[3] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[2] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[1] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state[0]
I: to  u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[6] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[5] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[4] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[3] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[2] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_mrs/state_reg[0]
I: 0000001 => 0000001
I: 0000010 => 0000010
I: 0000100 => 0000100
I: 0001000 => 0001000
I: 0010000 => 0010000
I: 0100000 => 0100000
I: 1000000 => 1000000
I: Encoding type of FSM 'state_fsm[2:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[2:0]':
I: from  u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state[2] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state[1] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state[0]
I: to  u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[6] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[3] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1] u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]
I: 000 => 0000001
I: 001 => 0000010
I: 010 => 0000100
I: 011 => 0001000
I: 100 => 0010000
I: 101 => 0100000
I: 110 => 1000000
I: Encoding type of FSM 'rx_main_fsm_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'rx_main_fsm_fsm[3:0]':
I: from  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm[0]
I: to  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/rx_main_fsm_reg[0]
I: 0000 => 000000001
I: 0001 => 000000010
I: 0010 => 000000100
I: 0011 => 000001000
I: 0100 => 000010000
I: 0101 => 000100000
I: 0110 => 001000000
I: 0111 => 010000000
I: 1000 => 100000000
I: Encoding type of FSM 'main_done_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'main_done_fsm[3:0]':
I: from  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done[0]
I: to  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/rx_rst_fsm_multi_sw_lane/main_done_reg[0]
I: 0000 => 0001
I: 0001 => 0010
I: 0011 => 0100
I: 1111 => 1000
I: Encoding type of FSM 'rx_init_fsm_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'rx_init_fsm_fsm[3:0]':
I: from  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[0]
I: to  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[9] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[0]
I: 0000 => 0000000001
I: 0001 => 0000000010
I: 0010 => 0000000100
I: 0011 => 0000001000
I: 0100 => 0000010000
I: 0101 => 0000100000
I: 0110 => 0001000000
I: 0111 => 0010000000
I: 1000 => 0100000000
I: 1001 => 1000000000
I: Encoding type of FSM 'rx_init_fsm_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'rx_init_fsm_fsm[3:0]':
I: from  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[0]
I: to  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[9] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[0]
I: 0000 => 0000000001
I: 0001 => 0000000010
I: 0010 => 0000000100
I: 0011 => 0000001000
I: 0100 => 0000010000
I: 0101 => 0000100000
I: 0110 => 0001000000
I: 0111 => 0010000000
I: 1000 => 0100000000
I: 1001 => 1000000000
I: Encoding type of FSM 'rx_init_fsm_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'rx_init_fsm_fsm[3:0]':
I: from  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[0]
I: to  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[9] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[0]
I: 0000 => 0000000001
I: 0001 => 0000000010
I: 0010 => 0000000100
I: 0011 => 0000001000
I: 0100 => 0000010000
I: 0101 => 0000100000
I: 0110 => 0001000000
I: 0111 => 0010000000
I: 1000 => 0100000000
I: 1001 => 1000000000
I: Encoding type of FSM 'rx_init_fsm_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'rx_init_fsm_fsm[3:0]':
I: from  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm[0]
I: to  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[9] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/rx_init_fsm_reg[0]
I: 0000 => 0000000001
I: 0001 => 0000000010
I: 0010 => 0000000100
I: 0011 => 0000001000
I: 0100 => 0000010000
I: 0101 => 0000100000
I: 0110 => 0001000000
I: 0111 => 0010000000
I: 1000 => 0100000000
I: 1001 => 1000000000
I: Encoding type of FSM 'hsst_fsm_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'hsst_fsm_fsm[3:0]':
I: from  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm[0]
I: to  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[8] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[7] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[6] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[5] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[4] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[3] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/hsst_fsm_reg[0]
I: 0000 => 000000001
I: 0001 => 000000010
I: 0010 => 000000100
I: 0011 => 000001000
I: 0100 => 000010000
I: 0101 => 000100000
I: 0110 => 001000000
I: 0111 => 010000000
I: 1000 => 100000000
I: Removed bmsREDAND inst hsst_fsm_fsm[3:0]_4 that is redundant to N293
I: Removed bmsREDAND inst hsst_fsm_fsm[3:0]_22 that is redundant to N301
I: Removed bmsREDAND inst hsst_fsm_fsm[3:0]_2 that is redundant to N282
I: Encoding type of FSM 'seio_state_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'seio_state_fsm[1:0]':
I: from  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_pcie_seio/seio_state[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_pcie_seio/seio_state[0]
I: to  u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_pcie_seio/seio_state_reg[2] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_pcie_seio/seio_state_reg[1] u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/u_pcie_seio/seio_state_reg[0]
I: 00 => 001
I: 01 => 010
I: 10 => 100
I: Encoding type of FSM 'config_step_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'config_step_fsm[1:0]':
I: from  coms1_reg_config/config_step[1] coms1_reg_config/config_step[0]
I: to  coms1_reg_config/config_step_reg[2] coms1_reg_config/config_step_reg[1] coms1_reg_config/config_step_reg[0]
I: 00 => 001
I: 01 => 010
I: 10 => 100
I: Encoding type of FSM 'config_step_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'config_step_fsm[1:0]':
I: from  coms2_reg_config/config_step[1] coms2_reg_config/config_step[0]
I: to  coms2_reg_config/config_step_reg[2] coms2_reg_config/config_step_reg[1] coms2_reg_config/config_step_reg[0]
I: 00 => 001
I: 01 => 010
I: 10 => 100
I: Encoding type of FSM 'CurrState_SISt_fsm[3:0]' is: onehot.
I: Encoding table of FSM 'CurrState_SISt_fsm[3:0]':
I: from  i2cSlave_u/u_serialInterface/CurrState_SISt[3] i2cSlave_u/u_serialInterface/CurrState_SISt[2] i2cSlave_u/u_serialInterface/CurrState_SISt[1] i2cSlave_u/u_serialInterface/CurrState_SISt[0]
I: to  i2cSlave_u/u_serialInterface/CurrState_SISt_reg[15] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[14] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[13] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[12] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[11] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[10] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[9] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[8] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[7] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[6] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[5] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[4] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[3] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[2] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[1] i2cSlave_u/u_serialInterface/CurrState_SISt_reg[0]
I: 0000 => 0000000000000001
I: 0001 => 0000000000000010
I: 0010 => 0000000000000100
I: 0011 => 0000000000001000
I: 0100 => 0000000000010000
I: 0101 => 0000000000100000
I: 0110 => 0000000001000000
I: 0111 => 0000000010000000
I: 1000 => 0000000100000000
I: 1001 => 0000001000000000
I: 1010 => 0000010000000000
I: 1011 => 0000100000000000
I: 1100 => 0001000000000000
I: 1101 => 0010000000000000
I: 1110 => 0100000000000000
I: 1111 => 1000000000000000
I: Encoding type of FSM 'streamSt_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'streamSt_fsm[1:0]':
I: from  i2cSlave_u/u_serialInterface/streamSt[1] i2cSlave_u/u_serialInterface/streamSt[0]
I: to  i2cSlave_u/u_serialInterface/streamSt_reg[3] i2cSlave_u/u_serialInterface/streamSt_reg[2] i2cSlave_u/u_serialInterface/streamSt_reg[1] i2cSlave_u/u_serialInterface/streamSt_reg[0]
I: 00 => 0001
I: 01 => 0010
I: 10 => 0100
I: 11 => 1000
I: Encoding type of FSM 'state_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[1:0]':
I: from  u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/state[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/state[0]
I: to  u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/state_reg[2] u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/state_reg[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/state_reg[0]
I: 00 => 001
I: 01 => 010
I: 10 => 100
I: Encoding type of FSM 'state_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[1:0]':
I: from  u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/state[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/state[0]
I: to  u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/state_reg[2] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/state_reg[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/state_reg[0]
I: 00 => 001
I: 01 => 010
I: 10 => 100
I: Encoding type of FSM 'state_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[1:0]':
I: from  u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/state[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/state[0]
I: to  u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/state_reg[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/state_reg[0]
I: 00 => 01
I: 01 => 10
I: Encoding type of FSM 'state_fsm[1:0]' is: onehot.
I: Encoding table of FSM 'state_fsm[1:0]':
I: from  u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/state[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/state[0]
I: to  u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/state_reg[2] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/state_reg[1] u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/state_reg[0]
I: 00 => 001
I: 01 => 010
I: 10 => 100
I: Encoding type of FSM 'crt_st_fsm[8:0]' is: onehot.
I: Encoding table of FSM 'crt_st_fsm[8:0]':
I: from  u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[8] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[7] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[6] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[5] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[4] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[3] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[2] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[1] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st[0]
I: to  u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[13] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[12] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[11] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[10] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[9] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[8] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[7] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[6] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[5] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[4] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[3] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[2] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[1] u_uart2apb_top/u_apb_ctr/u_cmd_parser/crt_st_reg[0]
I: 000000000 => 00000000000001
I: 000000001 => 00000000000010
I: 000000010 => 00000000000100
I: 000000011 => 00000000001000
I: 000000100 => 00000000010000
I: 000000101 => 00000000100000
I: 000000110 => 00000001000000
I: 000000111 => 00000010000000
I: 000001000 => 00000100000000
I: 000001001 => 00001000000000
I: 000001010 => 00010000000000
I: 000001011 => 00100000000000
I: 000001100 => 01000000000000
I: 000001101 => 10000000000000
W: Removed bmsWIDEDFFPATCE inst blk_state_reg at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst curr_rd_reg_reg at 0 that is stuck at constant 1.
W: Removed bmsWIDEDFFPATCE inst curr_rd_reg_reg at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst curr_rd_reg_reg at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst curr_rd_reg_reg at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_byte_en[15:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 9 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 11 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 12 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 13 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 14 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 15 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 16 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 17 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 18 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 19 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 20 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 21 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 22 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 23 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 24 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 25 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 26 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 27 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 28 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 29 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 30 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 31 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 32 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 33 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 34 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 35 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 36 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 37 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 38 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 39 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 40 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 41 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 42 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 43 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 44 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 45 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 46 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 47 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 48 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 49 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 50 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 51 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 52 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 53 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 54 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 55 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 56 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 57 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 58 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 59 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 60 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 61 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 62 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 63 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 64 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 65 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 66 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 67 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 68 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 69 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 70 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 71 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 72 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 73 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 74 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 75 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 76 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 77 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 78 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 79 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 80 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 81 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 82 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 83 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 84 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 85 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 86 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 87 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 88 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 89 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 90 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 91 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 92 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 93 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 94 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 95 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 96 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 97 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 98 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 99 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 100 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 101 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 102 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 103 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 104 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 105 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 106 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 107 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 108 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 109 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 110 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 111 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 112 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 113 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 114 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 115 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 116 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 117 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 118 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 119 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 120 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 121 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 122 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 123 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 124 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 125 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 126 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_data[127:0] at 127 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst blk_state_reg at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst Reg0_wr_en that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst Reg1_wr_en that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst Reg_wr_state that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst blk_state_reg at 0 that is stuck at constant 1.
W: Removed bmsWIDEDFFPATCE inst blk_state_reg at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 9 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst next_wr_addr[11:0] at 11 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 4 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 6 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 7 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 9 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_addr[11:0] at 11 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst bar0_wr_en that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst genblk2.init_ba[2:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst rdcal_address[14:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst rdcal_ba[2:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst wrcal_address[14:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst wrlvl_address[14:0] at 13 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst wrlvl_ba[2:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst eyecal_address[14:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst phy_ck[3:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst mr0[15:0] at 15 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst mr1[15:0] at 15 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst mr2[15:0] at 15 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst mr3[15:0] at 15 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst dqs_gate_pulse_src_nxt_r[3:0] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst dqs_gate_pulse_src_nxt_r[3:0] at 3 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst norm_addr_m[14:0] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst norm_cmd_m[7:0] at 5 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst mux_dfi_cas_n[3:0] at 3 that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst mux_dfi_cs_n[3:0] at 3 that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst mux_dfi_ras_n[3:0] at 3 that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst mux_dfi_we_n[3:0] at 3 that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst lp_we_n[1:0] at 1 that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst mrs_bank[2:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_0[45:0] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_0[45:0] at 19 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_0[45:0] at 20 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_0[45:0] at 30 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_0[45:0] at 31 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_0[45:0] at 41 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_0[45:0] at 42 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_1[45:0] at 8 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_1[45:0] at 19 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_1[45:0] at 20 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_1[45:0] at 30 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_1[45:0] at 31 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_1[45:0] at 41 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_TDATA_X2.P_TDATA_1[45:0] at 42 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst lx_deemph[1:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst phy_mac_phystatus_misc[3:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst phy_mac_phystatus_pm[3:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_LX_RX_CKDIV[1:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFPATCE inst P_PMA_TX_RATE[2:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst dbi_addr[31:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst dbi_addr[31:0] at 1 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst dbi_din[31:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFRSE inst i2c_data[31:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFRSE inst i2c_data[31:0] at 27 that is stuck at constant 1.
W: Removed bmsWIDEDFFRSE inst i2c_data[31:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFRSE inst i2c_data[31:0] at 27 that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst o_cpld_byte_cnt[11:0] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst o_mrd_addr[63:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst o_mwr_addr[63:0] at 0 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst o_trgt1_radm_pkt_halt[2:0] at 2 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst o_axis_slave1_tdata[127:0] at 10 that is stuck at constant 0.
W: Removed bmsWIDEDFFCPE inst shift_reg[11:0] at 11 that is stuck at constant 1.
W: Removed bmsWIDEDFFCPE inst shift_reg[11:0] at 10 that is stuck at constant 1.
Executing : pre-mapping successfully. Time elapsed: 1.493s wall, 1.859s user + 0.328s system = 2.188s CPU (146.5%)

Start mod-gen.
W: Public-4008: Instance 'i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrlvl/ck_dly_set_bin_tra[7:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.syn_almost_empty' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.syn_almost_full' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/wr_water_level[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'ips_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/rd_water_level[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.syn_almost_empty' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.syn_almost_full' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/rd_water_level[5:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/wr_water_level[5:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'timing_prea_pass/r_cnt_almost_pass' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.syn_almost_empty' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/wr_water_level[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'B_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/rd_water_level[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'A_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/SYN_CTRL.syn_almost_empty' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'A_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/wr_water_level[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'A_ips2l_distributed_fifo/u_ips2l_distributed_fifo_distributed_fifo_v1_0/u_ips2l_distributed_fifo_ctr/rd_water_level[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/rise_cnt[11:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_b_ff' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_b_neg' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_deb_pre' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_deb_pre' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/rise_cnt[11:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_b_ff' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_b_neg' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/rise_cnt[11:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_b_ff' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_b_neg' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_deb_pre' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_deb_pre' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/rise_cnt[11:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_b_ff' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_b_neg' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/rise_cnt[11:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_b_ff' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_b_neg' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_deb_pre' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_deb_pre' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/rise_cnt[11:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_b_ff' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_b_neg' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/rise_cnt[11:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_b_ff' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_b_neg' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/cdr_align_multi_sw_deb/signal_deb_pre' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_deb_pre' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/rise_cnt[11:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_b_ff' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/loss_signal_multi_sw_deb/signal_b_neg' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_HSST_RST' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_LANE_SYNC_EN' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u1/ack1' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u1/ack2' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u1/ack3' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u1/ack1' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u1/ack2' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u1/ack3' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_mwr_wr_ctrl/ips2l_pcie_dma_mwr_wr_ctrl/wr_addr[63:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_cpld_wr_ctrl/ips2l_pcie_dma_cpld_wr_ctrl/o_wr_bar_hit[1:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma_tlp_rcv/o_mwr_dw_vld[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_mwr_wr_ctrl/ips2l_pcie_dma_mwr_wr_ctrl/byte_en_ff[15:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_mwr_wr_ctrl/ips2l_pcie_dma_mwr_wr_ctrl/dw_vld[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_mwr_wr_ctrl/ips2l_pcie_dma_mwr_wr_ctrl/dwbe[7:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_mwr_wr_ctrl/ips2l_pcie_dma_mwr_wr_ctrl/last_dw_position[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_mwr_wr_ctrl/ips2l_pcie_dma_mwr_wr_ctrl/length[9:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_mwr_wr_ctrl/ips2l_pcie_dma_mwr_wr_ctrl/o_wr_addr[11:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_mwr_wr_ctrl/ips2l_pcie_dma_mwr_wr_ctrl/o_wr_be[15:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/SYN_CTRL.syn_almost_empty' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/SYN_CTRL.syn_almost_full' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/wr_water_level[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/rd_water_level[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/SYN_CTRL.syn_almost_empty' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/SYN_CTRL.syn_almost_full' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/wr_water_level[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/rd_water_level[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart_top/u_pgr_uart_rx/rx_chk_err' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart_top/u_pgr_uart_rx/rx_overrun' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/error_status_reg' of 'bmsWIDEDFFPATCE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir0[9:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/debug_dps_cnt_dir1[9:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_cpd_ctrl/dps_timeout' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/ddrphy_slice_rddata_align/align_error' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/ddrphy_dgts_r[2:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dgts_cnt[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dgts_latch' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dgts_vld' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dgts_vld_cnt[2:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_win_size[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/wrcal_error' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/ddrphy_dgts_r[2:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dgts_cnt[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dgts_latch' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dgts_vld' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dgts_vld_cnt[2:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/gate_win_size[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/wrcal_error' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/u_ddrphy_gpll_phase/gpll_dps_done_pos' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/u_ddrphy_gpll_phase/gpll_dps_phase[8:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ddrphy_top/u_ddrphy_gpll_phase/gpll_dps_done_d[2:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/wusro_id[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/o_wid[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wid_d0[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wid_d1[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wid_d2[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wid_d3[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wid_d4[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wid_d5[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/des_p_rdata_hold[15:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_src_p_rdata[15:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/o_src_p_rdy' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_apb_cross_v1_2/src_p_enable' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mode_state_reg' of 'bmsWIDEDFFPATCE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/busy' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/core_apb_rdata[15:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/ddr_init_dly1' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/ddr_init_dly2' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/sr_en_dly1' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/sr_en_dly2' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/sr_status' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mrs_en_dly1' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/mrs_en_dly2' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/pd_en_dly1' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/pd_en_dly2' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_cfg_apb/pd_status' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wid[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ddr3/u_ips_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/ddr_zqcs_ack' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_PCIE_HARD_CTRL/U_APB2DBI/p_rdata[31:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/u_pcie_apb_mux/u_pcie_apb_cross/des_p_rdata_hold[31:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/u_pcie_apb_mux/u_pcie_apb_cross/o_src_p_rdata[31:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'power_on_delay_inst/initial_en' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'power_on_delay_inst/cnt3[19:0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/o_cross_4kb_boundary' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/apb_cmd_h_addr[31:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/apb_cmd_h_addr_vld' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/apb_cmd_l_addr[31:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/apb_cmd_l_addr_vld' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/apb_cmd_length[31:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/apb_cmd_length_vld' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/apb_cmd_reg[31:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/apb_cmd_reg_vld' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/o_apb_prdata[31:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_rx_top/u_ips2l_pcie_dma_tlp_rcv/o_trgt1_radm_pkt_halt[2:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/fifo_data_cnt[6:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_expd_apb_mux/u_pcie_expd_apb_cross/des_p_rdata_hold[31:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_ips2l_pcie_expd_apb_mux/u_pcie_expd_apb_cross/o_src_p_rdata[31:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_pgr_uart_tx/clken' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_pgr_uart_tx/cnt[2:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_pgr_uart_tx/shift_reg[11:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_pgr_uart_tx/tx_cnt[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_pgr_uart_tx/tx_req' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo/fifo_vld' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/SYN_CTRL.rptr[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo/rd_data_ff1[7:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/SYN_CTRL.syn_rempty' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/SYN_CTRL.waddr_msb' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/SYN_CTRL.wptr[4:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/SYN_CTRL.syn_wfull' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_uart_top/u_tx_fifo/FIFO_PG30.u_prefetch_fifo/pgm_distributed_fifo_v1_0/u_pgm_distributed_fifo_ctr_v1_0/SYN_CTRL.raddr_msb' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_apb_ctr/u_apb_mif/trans_cnt[3:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_apb_ctr/u_apb_mif/clk_cnt[15:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_apb_ctr/u_apb_mif/clk_cnt_start1' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_apb_ctr/u_apb_mif/fifo_data[7:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
W: Public-4008: Instance 'u_uart2apb_top/u_apb_ctr/u_apb_mif/fifo_data_req' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned.
E: Net _$$_GND_$$_ has multiple drivers in module pcie_dma_test (see run.log for details).
    module 'bmsGND' inst '_$$_GND_$$_' out pin 'Z'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg0[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[0]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg0[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[1]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg0[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[2]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg0[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[3]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg0[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[4]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg0[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[5]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg0[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[6]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg0[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[7]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg1[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[0]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg1[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[1]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg1[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[2]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg1[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[3]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg1[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[4]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg1[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[5]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg1[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[6]'
    module 'bmsWIDEDFFCPE' inst 'i2cSlave_u/u_registerInterface/myReg1[7:0] [D:/DMYWdownloadsoftware/PDS/project/project_bs/PCIe_IIc_SXT_DDR_3_LC_TP_4_2/pcie_dma_test/my_code_file/IIc_text/registerInterface.v(line number:87)]' out pin 'Q[7]'

Program Error Out.
Action synthesize: Real time elapsed is 0h:0m:10s
Action synthesize: CPU time elapsed is 0h:0m:9s
Action synthesize: Process CPU time elapsed is 0h:0m:9s
Current time: Wed Nov  5 00:15:59 2025
Action synthesize: Peak memory pool usage is 477 MB
