#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: D:\pds2022_sp6_4\PDS_2022.2-SP6.4\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.22631
#Hostname: DESKTOP-50P54KS
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Wed Jan  8 10:12:34 2025
License checkout: fabric_ads from D:\pds_2022_1\PDS_2022.1\license\new_pds_F4A80DA47D72.lic
Compiling verification operator library.
Compiling common defs.
Loading technology operator library.
Compiling technology operator library.
Compiling technology operator (valence) library.
Reading design from compile DB
Reading design from compile DB successfully.
Constraint check start.
Compiling prim grid devices.
Building architecture model.
Loading device packaging model.
Building architecture floorplan logic view.
Executing : get_ports free_clk
Executing : get_ports free_clk successfully.
Executing : create_clock -name ref_clk [get_ports free_clk] -period 40.000 -waveform {0.000 20.000}
Executing : create_clock -name ref_clk [get_ports free_clk] -period 40.000 -waveform {0.000 20.000} successfully.
Executing : get_ports ref_clk_p
C: Timing-4002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 6)] Port 'ref_clk_p' is not found in current design.
Executing : get_ports ref_clk_p successfully.
Executing : get_pins I_ips_ddr_top.u_ddrphy_top.rst_clk_gpll/clkout0
Executing : get_pins I_ips_ddr_top.u_ddrphy_top.rst_clk_gpll/clkout0 successfully.
Executing : get_clocks ref_clk
Executing : get_clocks ref_clk successfully.
Executing : create_generated_clock -name rst_clk -source [get_ports ref_clk_p] [get_pins I_ips_ddr_top.u_ddrphy_top.rst_clk_gpll/clkout0] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 84
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 6)] Nothing matched for 'source', command 'create_generated_clock' is aborted.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 6)] Failed to import constraint "create_generated_clock -name rst_clk -source [get_ports ref_clk_p] [get_pins I_ips_ddr_top.u_ddrphy_top.rst_clk_gpll/clkout0] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 84".
Executing : get_ports ref_clk_p
C: Timing-4002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 7)] Port 'ref_clk_p' is not found in current design.
Executing : get_ports ref_clk_p successfully.
Executing : get_pins I_ips_ddr_top.u_ddrphy_top.ddrphy_gpll/clkout0
Executing : get_pins I_ips_ddr_top.u_ddrphy_top.ddrphy_gpll/clkout0 successfully.
Executing : get_clocks ref_clk
Executing : get_clocks ref_clk successfully.
Executing : create_generated_clock -name ddrphy_sysclk -source [get_ports ref_clk_p] [get_pins I_ips_ddr_top.u_ddrphy_top.ddrphy_gpll/clkout0] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 16
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 7)] Nothing matched for 'source', command 'create_generated_clock' is aborted.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 7)] Failed to import constraint "create_generated_clock -name ddrphy_sysclk -source [get_ports ref_clk_p] [get_pins I_ips_ddr_top.u_ddrphy_top.ddrphy_gpll/clkout0] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 16".
Executing : get_ports ref_clk_p
C: Timing-4002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 8)] Port 'ref_clk_p' is not found in current design.
Executing : get_ports ref_clk_p successfully.
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy} successfully.
Executing : get_clocks ref_clk
Executing : get_clocks ref_clk successfully.
Executing : create_generated_clock -name phy_dq_clk_0 -source [get_ports ref_clk_p] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 2
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 8)] Nothing matched for 'source', command 'create_generated_clock' is aborted.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 8)] Failed to import constraint "create_generated_clock -name phy_dq_clk_0 -source [get_ports ref_clk_p] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 2".
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy} successfully.
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT} successfully.
Executing : get_clocks phy_dq_clk_0
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 9)] Nothing implicitly matched 'phy_dq_clk_0'.
Executing : get_clocks phy_dq_clk_0 successfully.
Executing : create_generated_clock -name phy_dq_sysclk_0 -source [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_0] -edges {5 13 21} -edge_shift {0 0 0}
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 9)] Nothing matched for 'master_clock', command 'create_generated_clock' is aborted.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 9)] Failed to import constraint "create_generated_clock -name phy_dq_sysclk_0 -source [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_0] -edges {5 13 21} -edge_shift {0 0 0}".
Executing : get_clocks ddrphy_sysclk
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 10)] Nothing implicitly matched 'ddrphy_sysclk'.
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_0
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 10)] Nothing implicitly matched 'phy_dq_sysclk_0'.
Executing : get_clocks phy_dq_sysclk_0 successfully.
Executing : set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0]
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 10)] Nothing matched for 'from_list', command 'set_multicycle_path' is aborted.
C: SDC-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 10)] Failed to parse the val of the option 'from' for command 'set_multicycle_path'.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 10)] Failed to import constraint "set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0]".
Executing : get_ports ref_clk_p
C: Timing-4002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 11)] Port 'ref_clk_p' is not found in current design.
Executing : get_ports ref_clk_p successfully.
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy} successfully.
Executing : get_clocks ref_clk
Executing : get_clocks ref_clk successfully.
Executing : create_generated_clock -name phy_dq_clk_1 -source [get_ports ref_clk_p] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 2
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 11)] Nothing matched for 'source', command 'create_generated_clock' is aborted.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 11)] Failed to import constraint "create_generated_clock -name phy_dq_clk_1 -source [get_ports ref_clk_p] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 2".
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy} successfully.
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT} successfully.
Executing : get_clocks phy_dq_clk_1
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 12)] Nothing implicitly matched 'phy_dq_clk_1'.
Executing : get_clocks phy_dq_clk_1 successfully.
Executing : create_generated_clock -name phy_dq_sysclk_1 -source [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_1] -edges {5 13 21} -edge_shift {0 0 0}
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 12)] Nothing matched for 'master_clock', command 'create_generated_clock' is aborted.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 12)] Failed to import constraint "create_generated_clock -name phy_dq_sysclk_1 -source [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_1] -edges {5 13 21} -edge_shift {0 0 0}".
Executing : get_clocks ddrphy_sysclk
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 13)] Nothing implicitly matched 'ddrphy_sysclk'.
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_1
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 13)] Nothing implicitly matched 'phy_dq_sysclk_1'.
Executing : get_clocks phy_dq_sysclk_1 successfully.
Executing : set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1]
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 13)] Nothing matched for 'from_list', command 'set_multicycle_path' is aborted.
C: SDC-2023: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 13)] Failed to parse the val of the option 'from' for command 'set_multicycle_path'.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 13)] Failed to import constraint "set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1]".
Executing : get_clocks ddrphy_sysclk
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 14)] Nothing implicitly matched 'ddrphy_sysclk'.
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_0
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 14)] Nothing implicitly matched 'phy_dq_sysclk_0'.
Executing : get_clocks phy_dq_sysclk_0 successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0] -setup -hold
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 14)] Nothing matched for 'from_list', command 'set_clock_uncertainty' is aborted.
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 14)] Nothing matched for 'to_list', command 'set_clock_uncertainty' is aborted.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 14)] Failed to import constraint "set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0] -setup -hold".
Executing : get_clocks phy_dq_sysclk_0
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 15)] Nothing implicitly matched 'phy_dq_sysclk_0'.
Executing : get_clocks phy_dq_sysclk_0 successfully.
Executing : get_clocks ddrphy_sysclk
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 15)] Nothing implicitly matched 'ddrphy_sysclk'.
Executing : get_clocks ddrphy_sysclk successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_0] -to [get_clocks ddrphy_sysclk] -setup -hold
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 15)] Nothing matched for 'from_list', command 'set_clock_uncertainty' is aborted.
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 15)] Nothing matched for 'to_list', command 'set_clock_uncertainty' is aborted.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 15)] Failed to import constraint "set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_0] -to [get_clocks ddrphy_sysclk] -setup -hold".
Executing : get_clocks ddrphy_sysclk
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 16)] Nothing implicitly matched 'ddrphy_sysclk'.
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_1
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 16)] Nothing implicitly matched 'phy_dq_sysclk_1'.
Executing : get_clocks phy_dq_sysclk_1 successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1] -setup -hold
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 16)] Nothing matched for 'from_list', command 'set_clock_uncertainty' is aborted.
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 16)] Nothing matched for 'to_list', command 'set_clock_uncertainty' is aborted.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 16)] Failed to import constraint "set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1] -setup -hold".
Executing : get_clocks phy_dq_sysclk_1
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 17)] Nothing implicitly matched 'phy_dq_sysclk_1'.
Executing : get_clocks phy_dq_sysclk_1 successfully.
Executing : get_clocks ddrphy_sysclk
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 17)] Nothing implicitly matched 'ddrphy_sysclk'.
Executing : get_clocks ddrphy_sysclk successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_1] -to [get_clocks ddrphy_sysclk] -setup -hold
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 17)] Nothing matched for 'from_list', command 'set_clock_uncertainty' is aborted.
E: CommandTiming-0057: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 17)] Nothing matched for 'to_list', command 'set_clock_uncertainty' is aborted.
E: ConstraintEditor-0046: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 17)] Failed to import constraint "set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_1] -to [get_clocks ddrphy_sysclk] -setup -hold".
Executing : get_clocks ref_clk
Executing : get_clocks ref_clk successfully.
Executing : set_clock_groups -name ref_clk -asynchronous -group [get_clocks ref_clk]
Executing : set_clock_groups -name ref_clk -asynchronous -group [get_clocks ref_clk] successfully.
Executing : get_clocks rst_clk
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 19)] Nothing implicitly matched 'rst_clk'.
Executing : get_clocks rst_clk successfully.
Executing : set_clock_groups -name rst_clk -asynchronous -group [get_clocks rst_clk]
C: SDC-2027: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 19)] One or more clocks can not find in the group '[get_clocks rst_clk]', command 'set_clock_groups' is ignored.
Executing : set_clock_groups -name rst_clk -asynchronous -group [get_clocks rst_clk] successfully.
Executing : get_clocks phy_dq_clk_0
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 20)] Nothing implicitly matched 'phy_dq_clk_0'.
Executing : get_clocks phy_dq_clk_0 successfully.
Executing : set_clock_groups -name phy_dq_clk_0 -asynchronous -group [get_clocks phy_dq_clk_0]
C: SDC-2027: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 20)] One or more clocks can not find in the group '[get_clocks phy_dq_clk_0]', command 'set_clock_groups' is ignored.
Executing : set_clock_groups -name phy_dq_clk_0 -asynchronous -group [get_clocks phy_dq_clk_0] successfully.
Executing : get_clocks phy_dq_clk_1
C: SDC-2017: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 21)] Nothing implicitly matched 'phy_dq_clk_1'.
Executing : get_clocks phy_dq_clk_1 successfully.
Executing : set_clock_groups -name phy_dq_clk_1 -asynchronous -group [get_clocks phy_dq_clk_1]
C: SDC-2027: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 21)] One or more clocks can not find in the group '[get_clocks phy_dq_clk_1]', command 'set_clock_groups' is ignored.
Executing : set_clock_groups -name phy_dq_clk_1 -asynchronous -group [get_clocks phy_dq_clk_1] successfully.
C: ConstraintEditor-2002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 480)] | Port rst_board has been placed at location M15, whose type is share pin.
W: ConstraintEditor-4019: Port 'uart_rxd' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'uart_txd' unspecified I/O constraint.
Constraint check end.

Action synthesize: Real time elapsed is 0h:0m:7s
Action synthesize: CPU time elapsed is 0h:0m:0s
Action synthesize: Process CPU time elapsed is 0h:0m:0s
Current time: Wed Jan  8 10:12:39 2025
Action synthesize: Peak memory pool usage is 272 MB
