#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: D:\DMYWdownloadsoftware\PDS\pango\PDS_2022.2-SP6.4\bin
#Application name: pds.exe
#OS: Windows 10 10.0.26100
#Hostname: LAPTOP-E50OTCNR
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Sat Oct 18 19:57:12 2025
Parse module hierarchy of project 'D:/DMYWdownloadsoftware/PDS/project/ddr3_test/ddr3_test/ip_core/ddr3/pnr/temp_projects/Main_Flow/Main_Flow.pds' (ADS Parser)
Compiling common defs.
Compiling technology operator (valence) library.
Compiling prim grid devices.
Compiling prim grid device symbols.
Compiling gate devices.
Compiling gate operators.
Compiling tech operator impls.
Building architecture model.
Loading device packaging model.
Building architecture floorplan logic view.
Building architecture floorplan schematic view.
Total time(hh:mm:ss) of open UCE: 00:00:08
Loading the device ...
Executing : get_ports free_clk
Executing : get_ports free_clk successfully.
Executing : create_clock -name ref_clk [get_ports free_clk] -period 40.000 -waveform {0.000 20.000}
Executing : create_clock -name ref_clk [get_ports free_clk] -period 40.000 -waveform {0.000 20.000} successfully.
Executing : get_ports free_clk
Executing : get_ports free_clk successfully.
Executing : get_pins I_ips_ddr_top.u_ddrphy_top.rst_clk_gpll/clkout0
Executing : get_pins I_ips_ddr_top.u_ddrphy_top.rst_clk_gpll/clkout0 successfully.
Executing : get_clocks ref_clk
Executing : get_clocks ref_clk successfully.
Executing : create_generated_clock -name rst_clk -source [get_ports free_clk] [get_pins I_ips_ddr_top.u_ddrphy_top.rst_clk_gpll/clkout0] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 84
Executing : create_generated_clock -name rst_clk -source [get_ports free_clk] [get_pins I_ips_ddr_top.u_ddrphy_top.rst_clk_gpll/clkout0] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 84 successfully.
Executing : get_ports free_clk
Executing : get_ports free_clk successfully.
Executing : get_pins I_ips_ddr_top.u_ddrphy_top.ddrphy_gpll/clkout0
Executing : get_pins I_ips_ddr_top.u_ddrphy_top.ddrphy_gpll/clkout0 successfully.
Executing : get_clocks ref_clk
Executing : get_clocks ref_clk successfully.
Executing : create_generated_clock -name ddrphy_sysclk -source [get_ports free_clk] [get_pins I_ips_ddr_top.u_ddrphy_top.ddrphy_gpll/clkout0] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 16
Executing : create_generated_clock -name ddrphy_sysclk -source [get_ports free_clk] [get_pins I_ips_ddr_top.u_ddrphy_top.ddrphy_gpll/clkout0] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 16 successfully.
Executing : get_ports free_clk
Executing : get_ports free_clk successfully.
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy} successfully.
Executing : get_clocks ref_clk
Executing : get_clocks ref_clk successfully.
Executing : create_generated_clock -name phy_dq_clk_0 -source [get_ports free_clk] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 2
Executing : create_generated_clock -name phy_dq_clk_0 -source [get_ports free_clk] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 2 successfully.
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy} successfully.
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT} successfully.
Executing : get_clocks phy_dq_clk_0
Executing : get_clocks phy_dq_clk_0 successfully.
Executing : create_generated_clock -name phy_dq_sysclk_0 -source [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_0] -edges {5 13 21} -edge_shift {0 0 0}
Executing : create_generated_clock -name phy_dq_sysclk_0 -source [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].ddrphy_ppll/clkoutphy}] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[0].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_0] -edges {5 13 21} -edge_shift {0 0 0} successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_0
Executing : get_clocks phy_dq_sysclk_0 successfully.
Executing : set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0]
Executing : set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0] successfully.
Executing : get_ports free_clk
Executing : get_ports free_clk successfully.
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy} successfully.
Executing : get_clocks ref_clk
Executing : get_clocks ref_clk successfully.
Executing : create_generated_clock -name phy_dq_clk_1 -source [get_ports free_clk] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 2
Executing : create_generated_clock -name phy_dq_clk_1 -source [get_ports free_clk] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] -master_clock [get_clocks ref_clk] -multiply_by 84 -divide_by 2 successfully.
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy} successfully.
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT}
Executing : get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT} successfully.
Executing : get_clocks phy_dq_clk_1
Executing : get_clocks phy_dq_clk_1 successfully.
Executing : create_generated_clock -name phy_dq_sysclk_1 -source [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_1] -edges {5 13 21} -edge_shift {0 0 0}
Executing : create_generated_clock -name phy_dq_sysclk_1 -source [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].ddrphy_ppll/clkoutphy}] [get_pins {I_ips_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_bank[1].u_ddrphy_ioclkdiv/CLKDIVOUT}] -master_clock [get_clocks phy_dq_clk_1] -edges {5 13 21} -edge_shift {0 0 0} successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_1
Executing : get_clocks phy_dq_sysclk_1 successfully.
Executing : set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1]
Executing : set_multicycle_path 2 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1] successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_0
Executing : get_clocks phy_dq_sysclk_0 successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0] -setup -hold
Executing : set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_0] -setup -hold successfully.
Executing : get_clocks phy_dq_sysclk_0
Executing : get_clocks phy_dq_sysclk_0 successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_0] -to [get_clocks ddrphy_sysclk] -setup -hold
Executing : set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_0] -to [get_clocks ddrphy_sysclk] -setup -hold successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : get_clocks phy_dq_sysclk_1
Executing : get_clocks phy_dq_sysclk_1 successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1] -setup -hold
Executing : set_clock_uncertainty 0.4 -from [get_clocks ddrphy_sysclk] -to [get_clocks phy_dq_sysclk_1] -setup -hold successfully.
Executing : get_clocks phy_dq_sysclk_1
Executing : get_clocks phy_dq_sysclk_1 successfully.
Executing : get_clocks ddrphy_sysclk
Executing : get_clocks ddrphy_sysclk successfully.
Executing : set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_1] -to [get_clocks ddrphy_sysclk] -setup -hold
Executing : set_clock_uncertainty 0.4 -from [get_clocks phy_dq_sysclk_1] -to [get_clocks ddrphy_sysclk] -setup -hold successfully.
Executing : get_clocks ref_clk
Executing : get_clocks ref_clk successfully.
Executing : set_clock_groups -name ref_clk -asynchronous -group [get_clocks ref_clk]
Executing : set_clock_groups -name ref_clk -asynchronous -group [get_clocks ref_clk] successfully.
Executing : get_clocks rst_clk
Executing : get_clocks rst_clk successfully.
Executing : set_clock_groups -name rst_clk -asynchronous -group [get_clocks rst_clk]
Executing : set_clock_groups -name rst_clk -asynchronous -group [get_clocks rst_clk] successfully.
Executing : get_clocks phy_dq_clk_0
Executing : get_clocks phy_dq_clk_0 successfully.
Executing : set_clock_groups -name phy_dq_clk_0 -asynchronous -group [get_clocks phy_dq_clk_0]
Executing : set_clock_groups -name phy_dq_clk_0 -asynchronous -group [get_clocks phy_dq_clk_0] successfully.
Executing : get_clocks phy_dq_clk_1
Executing : get_clocks phy_dq_clk_1 successfully.
Executing : set_clock_groups -name phy_dq_clk_1 -asynchronous -group [get_clocks phy_dq_clk_1]
Executing : set_clock_groups -name phy_dq_clk_1 -asynchronous -group [get_clocks phy_dq_clk_1] successfully.
C: ConstraintEditor-2002: [D:/DMYWdownloadsoftware/PDS/project/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 480)] | Port rst_board has been placed at location M15, whose type is share pin.
W: ConstraintEditor-4019: Port 'uart_rxd' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'uart_txd' unspecified I/O constraint.
W: UserConstraintEditor-4001: [D:/DMYWdownloadsoftware/PDS/project/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 32)] Wide inst editing is temporarily not supported.
W: UserConstraintEditor-4001: [D:/DMYWdownloadsoftware/PDS/project/ddr3_test/ddr3_test/ip_core/ddr3/pnr/ddr_test.fdc(line number: 33)] Wide inst editing is temporarily not supported.
Open UCE successfully.
Current device : PG2L50H-6FBG484
