#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: D:\pds2022_sp6_4\PDS_2022.2-SP6.4\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.22631
#Hostname: DESKTOP-50P54KS
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Wed Jan  8 10:13:58 2025
Compiling verification operator library.
Compiling common defs.
Compiling prim grid devices.
Compiling gate devices.
Compiling gate operators.
Building architecture model.
Loading device packaging model.
pnr strategy configuration : 
strategy name : 0
Building architecture floorplan logic view.
Constraint check start.
Executing : def_port {mem_dq[0]} LOC=P6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[0]} LOC=P6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[1]} LOC=M5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[1]} LOC=M5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[2]} LOC=M6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[2]} LOC=M6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[3]} LOC=N2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[3]} LOC=N2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[4]} LOC=P2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[4]} LOC=P2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[5]} LOC=P1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[5]} LOC=P1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[6]} LOC=R1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[6]} LOC=R1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[7]} LOC=N4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[7]} LOC=N4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[8]} LOC=J6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[8]} LOC=J6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[9]} LOC=K6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[9]} LOC=K6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[10]} LOC=M2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[10]} LOC=M2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[11]} LOC=M3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[11]} LOC=M3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[12]} LOC=K3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[12]} LOC=K3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[13]} LOC=L3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[13]} LOC=L3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[14]} LOC=J4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[14]} LOC=J4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dq[15]} LOC=K4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE
Executing : def_port {mem_dq[15]} LOC=K4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON UNUSED=TRUE successfully
Executing : def_port {mem_dqs[0]} LOC=P5 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE
Executing : def_port {mem_dqs[0]} LOC=P5 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE successfully
Executing : def_port {mem_dqs[1]} LOC=M1 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE
Executing : def_port {mem_dqs[1]} LOC=M1 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE successfully
Executing : def_port {mem_dqs_n[0]} LOC=P4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE
Executing : def_port {mem_dqs_n[0]} LOC=P4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE successfully
Executing : def_port {mem_dqs_n[1]} LOC=L1 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE
Executing : def_port {mem_dqs_n[1]} LOC=L1 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST VREF_MODE=INT VREF_MODE_VALUE=0.5 DDR_TERM_MODE=ON DDR_RES=60 CP_DYN_TERM=ON UNUSED=TRUE successfully
Executing : def_port {err_flag_led} LOC=J16 VCCIO=1.8 IOSTANDARD=LVCMOS18 DRIVE=4 SLEW=FAST NONE=TRUE
Executing : def_port {err_flag_led} LOC=J16 VCCIO=1.8 IOSTANDARD=LVCMOS18 DRIVE=4 SLEW=FAST NONE=TRUE successfully
Executing : def_port {heart_beat_led} LOC=M17 VCCIO=1.8 IOSTANDARD=LVCMOS18 DRIVE=4 SLEW=FAST NONE=TRUE
Executing : def_port {heart_beat_led} LOC=M17 VCCIO=1.8 IOSTANDARD=LVCMOS18 DRIVE=4 SLEW=FAST NONE=TRUE successfully
Executing : def_port {mem_a[0]} LOC=T1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[0]} LOC=T1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[1]} LOC=U1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[1]} LOC=U1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[2]} LOC=U2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[2]} LOC=U2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[3]} LOC=V2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[3]} LOC=V2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[4]} LOC=R3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[4]} LOC=R3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[5]} LOC=R2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[5]} LOC=R2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[6]} LOC=W2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[6]} LOC=W2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[7]} LOC=Y2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[7]} LOC=Y2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[8]} LOC=W1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[8]} LOC=W1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[9]} LOC=Y1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[9]} LOC=Y1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[10]} LOC=U3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[10]} LOC=U3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[11]} LOC=AA1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[11]} LOC=AA1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[12]} LOC=AB1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[12]} LOC=AB1 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[13]} LOC=AB3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[13]} LOC=AB3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_a[14]} LOC=AB2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_a[14]} LOC=AB2 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_ba[0]} LOC=AA3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_ba[0]} LOC=AA3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_ba[1]} LOC=AA5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_ba[1]} LOC=AA5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_ba[2]} LOC=AB5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_ba[2]} LOC=AB5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_cas_n} LOC=U6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_cas_n} LOC=U6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_ck} LOC=Y4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_ck} LOC=Y4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_ck_n} LOC=AA4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_ck_n} LOC=AA4 VCCIO=1.5 IOSTANDARD=SSTL15D_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_cke} LOC=W4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_cke} LOC=W4 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_cs_n} LOC=V5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_cs_n} LOC=V5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_dm[0]} LOC=N5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_dm[0]} LOC=N5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_dm[1]} LOC=L5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_dm[1]} LOC=L5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_odt} LOC=R6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_odt} LOC=R6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_ras_n} LOC=W5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_ras_n} LOC=W5 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_rst_n} LOC=T3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_rst_n} LOC=T3 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {mem_we_n} LOC=W6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE
Executing : def_port {mem_we_n} LOC=W6 VCCIO=1.5 IOSTANDARD=SSTL15_I DRIVE=8.9 SLEW=FAST UNUSED=TRUE successfully
Executing : def_port {free_clk} LOC=V4 VCCIO=1.5 IOSTANDARD=LVCMOS15 UNUSED=TRUE
Executing : def_port {free_clk} LOC=V4 VCCIO=1.5 IOSTANDARD=LVCMOS15 UNUSED=TRUE successfully
Executing : def_port {rst_board} LOC=M15 VCCIO=1.8 IOSTANDARD=LVCMOS18 UNUSED=TRUE
C: ConstraintEditor-2002: [D:/fpga_rk/ddr3_test/ddr3_test/ip_core/ddr3/pnr/device_map/test_ddr.pcf(line number: 55)] | Port rst_board has been placed at location M15, whose type is share pin.
Executing : def_port {rst_board} LOC=M15 VCCIO=1.8 IOSTANDARD=LVCMOS18 UNUSED=TRUE successfully
Executing : def_inst_site {I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv} CLMA_285_54 FF3
Executing : def_inst_site {I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv} CLMA_285_54 FF3 successfully
Executing : def_inst_site {I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv} CLMA_285_360 FF3
Executing : def_inst_site {I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv} CLMA_285_360 FF3 successfully
Executing : def_inst_site {I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst} DDRPHY_CPD_297_4
Executing : def_inst_site {I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst} DDRPHY_CPD_297_4 successfully
W: ConstraintEditor-4019: Port 'uart_rxd' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'uart_txd' unspecified I/O constraint.
Constraint check end.
I: Column Clock Check open.
Read Column Clock Map.

Placement started.
Phase 1 Pre global placement started.
Mapping instance GRS_INST/grs_ccs to CCS_75_10.
Mapping instance u_adc_ctrl/ADC_inst/XADC/gopadc to ADC_75_306.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst to GPLL_295_157.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst to DDRPHY_IOCLK_DIV_296_4.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst to PPLL_295_1.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst to DDR_PHY_297_159.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/ddc_inst to DDR_PHY_297_157.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/ddc_inst to DDR_PHY_297_3.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst to DDRPHY_IOCLK_DIV_296_310.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst to PPLL_295_307.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY to DDR_PHY_297_307.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY to DDR_PHY_297_309.
Phase 1.1 1st GP placement started.
Design Utilization : 14%.
First map gop timing takes 0.16 sec
Worst slack after clock region global placement is -599
Wirelength after clock region global placement is 111507 and checksum is 5197FCF0CDC43CF7.
1st GP placement takes 0.70 sec.

Phase 1.2 Clock placement started.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk to RCKB_291_150.
Mapping instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk to RCKB_291_456.
Mapping instance I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst to MRCKB_289_150.
Mapping instance I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg to USCM_167_270.
Mapping instance free_clk_ibufg/gopclkbufg to USCM_167_273.
Mapping instance I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst to GPLL_7_157.
Mapping instance I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg to USCM_167_276.
Clock placement takes 0.05 sec.

Wirelength after Pre Global Placement is 111507 and checksum is 5197FCF0CDC43CF7.
Pre global placement takes 0.77 sec.

Phase 2 Global placement started.
Phase 2.1 Fixed placement started.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1 on IOLHR_292_318.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1 on IOLHR_292_324.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1 on IOLHR_292_330.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[3].u_iobuf_dq/opit_1 on IOLHR_292_336.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1 on IOLHR_292_342.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1 on IOLHR_292_360.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[6].u_iobuf_dq/opit_1 on IOLHR_292_366.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1 on IOLHR_292_378.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/genblk1.u_iobufco_dqs/opit_2 on IOLHR_292_354.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_outbuft_dm/opit_1 on IOLHR_292_312.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[0].u_iobuf_dq/opit_1 on IOLHR_292_396.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[1].u_iobuf_dq/opit_1 on IOLHR_292_402.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[2].u_iobuf_dq/opit_1 on IOLHR_292_408.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[3].u_iobuf_dq/opit_1 on IOLHR_292_414.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[4].u_iobuf_dq/opit_1 on IOLHR_292_432.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[5].u_iobuf_dq/opit_1 on IOLHR_292_438.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[6].u_iobuf_dq/opit_1 on IOLHR_292_444.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/dq_loop[7].u_iobuf_dq/opit_1 on IOLHR_292_450.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/genblk1.u_iobufco_dqs/opit_2 on IOLHR_292_426.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_outbuft_dm/opit_1 on IOLHR_292_390.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[0].u_outbuft_addr0/opit_1 on IOLHR_292_294.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[1].u_outbuft_addr0/opit_1 on IOLHR_292_288.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[2].u_outbuft_addr0/opit_1 on IOLHR_292_282.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[3].u_outbuft_addr0/opit_1 on IOLHR_292_276.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[4].u_outbuft_addr0/opit_1 on IOLHR_292_270.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[5].u_outbuft_addr0/opit_1 on IOLHR_292_264.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[6].u_outbuft_addr0/opit_1 on IOLHR_292_258.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[7].u_outbuft_addr0/opit_1 on IOLHR_292_252.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[8].u_outbuft_addr0/opit_1 on IOLHR_292_246.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[9].u_outbuft_addr0/opit_1 on IOLHR_292_240.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[10].u_outbuft_addr0/opit_1 on IOLHR_292_234.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[11].u_outbuft_addr0/opit_1 on IOLHR_292_222.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[12].u_outbuft_addr0/opit_1 on IOLHR_292_216.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[13].u_outbuft_addr0/opit_1 on IOLHR_292_210.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_mem_addr_0[14].u_outbuft_addr0/opit_1 on IOLHR_292_204.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[0].u_outbuft_ba/opit_1 on IOLHR_292_192.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[1].u_outbuft_ba/opit_1 on IOLHR_292_186.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/k_mem_ba[2].u_outbuft_ba/opit_1 on IOLHR_292_180.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_casn/opit_1 on IOLHR_292_108.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_cke/opit_1 on IOLHR_292_156.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_csn/opit_1 on IOLHR_292_102.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_odt/opit_1 on IOLHR_292_96.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_rasn/opit_1 on IOLHR_292_114.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_wen/opit_1 on IOLHR_292_120.
Placed fixed group with base inst I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuftco_ck/opit_3 on IOLHR_292_174.
Placed fixed group with base inst err_flag_led_obuf/opit_1 on IOLHR_16_606.
Placed fixed group with base inst free_clk_ibuf/opit_1 on IOLHR_292_162.
Placed fixed group with base inst heart_beat_led_obuf/opit_1 on IOLHR_16_306.
Placed fixed group with base inst mem_rst_n_obuf/opit_1 on IOLHR_292_300.
Placed fixed group with base inst rst_board_ibuf/opit_1 on IOLHR_16_318.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[0]/opit_0_inv on CLMA_285_54.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate[1]/opit_0_inv on CLMA_285_360.
Placed fixed instance GRS_INST/grs_ccs on CCS_75_10.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_gpll/u_gpll/gpll_inst on GPLL_295_157.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/ddc_inst on DDR_PHY_297_159.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/ddc_inst on DDR_PHY_297_157.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/ddc_inst on DDR_PHY_297_3.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].ddrphy_ppll/u_ppll/ppll_inst on PPLL_295_1.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_clkbufr/goprclk on RCKB_291_150.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[0].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst on DDRPHY_IOCLK_DIV_296_4.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].ddrphy_ppll/u_ppll/ppll_inst on PPLL_295_307.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_clkbufr/goprclk on RCKB_291_456.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_bank[1].u_ddrphy_ioclkdiv/ddrphy_ioclk_div_inst on DDRPHY_IOCLK_DIV_296_310.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY on DDR_PHY_297_307.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/u_ddc_dq/ddc_inst_PHY on DDR_PHY_297_309.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst on GPLL_7_157.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/u_clkbufm/clkbufm_inst on MRCKB_289_150.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/u_ddrphy_cpd/cpd_inst on DDRPHY_CPD_297_4.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/u_rst_clk_bufg/gopclkbufg on USCM_167_276.
Placed fixed instance I_ips_ddr_top/u_ddrphy_top/u_sysclk_bufg/gopclkbufg on USCM_167_270.
Placed fixed instance free_clk_ibufg/gopclkbufg on USCM_167_273.
Placed fixed instance u_adc_ctrl/ADC_inst/XADC/gopadc on ADC_75_306.
Placed fixed instance BKCL_auto_0 on BKCL_1_340.
Placed fixed instance BKCL_auto_1 on BKCL_301_340.
Placed fixed instance BKCL_auto_2 on BKCL_301_34.
Fixed placement takes 0.08 sec.

Phase 2.2 Process placement started.
I: The IO driver of I_ips_ddr_top/u_ddrphy_top/rst_clk_gpll/u_gpll/gpll_inst(CLKIN1) is not constraint at pllpad, its clock path will pass through SRB.
Process placement takes 0.00 sec.

Phase 2.3 IO placement started.
IO placement takes 0.00 sec.

Phase 2.4 2nd GP placement started.
Run super clustering :
	Initial slack -6169.
	19 iterations finished.
	Final slack 433.
Super clustering done.
Design Utilization : 14%.
Worst slack after global placement is 2957
2nd GP placement takes 0.42 sec.

Wirelength after global placement is 52006 and checksum is A057E52768B3694F.
Global placement takes 0.50 sec.

Phase 3 Post global placement started.
Packing LUT6D started.
I: LUT6D pack result: There are 2561 LUT6 in collection, pack success:68
Packing LUT6D takes 0.11 sec.
Phase 3.1 Macro cell placement started.
I: Process macros using "Greedy".
Wirelength after macro cell placement is 52357 and checksum is 7355A6C07A5275C.
Macro cell placement takes 0.00 sec.

Phase 3.2 3rd GP placement started.
Run super clustering :
	Initial slack -6247.
	17 iterations finished.
	Final slack 402.
Super clustering done.
Design Utilization : 14%.
Worst slack after post global placement is 2503
3rd GP placement takes 0.33 sec.

Wirelength after post global placement is 48037 and checksum is ADE2229DBE8C43A0.
Packing LUT6D started.
I: LUT6D pack result: There are 2425 LUT6 in collection, pack success:2
Packing LUT6D takes 0.11 sec.
Post global placement takes 0.55 sec.

Phase 4 Legalization started.
The average distance in LP is 0.677565.
Wirelength after legalization is 57899 and checksum is 55364CDFC2945EA7.
Legalization takes 0.17 sec.

Phase 5 Timing-driven detailed placement started.
Phase 5.1 Replication placement started.
Worst slack before Replication Place is 2394.
Replication placement takes 0.08 sec.

Wirelength after replication placement is 57899 and checksum is 55364CDFC2945EA7.
Phase 5.2 Swapping placement started.
Worst slack before detailed placement is 2394, TNS before detailed placement is 0. 
Worst slack after detailed placement is 2394, TNS after detailed placement is 0. 
Swapping placement takes 0.03 sec.

Wirelength after detailed placement is 57899 and checksum is 55364CDFC2945EA7.
Timing-driven detailed placement takes 0.11 sec.

Worst slack is 2394, TNS after placement is 0.
Placement done.
Total placement takes 2.81 sec.
Finished placement.
Executing : def_route -prior_net {I_ips_ddr_top/u_ddrphy_top/ddrphy_ioclk_gate [0]}
Executing : def_route -prior_net {I_ips_ddr_top/u_ddrphy_top/ddrphy_ioclk_gate [0]} successfully.
Executing : def_route -prior_net {I_ips_ddr_top/u_ddrphy_top/ddrphy_ioclk_gate [1]}
Executing : def_route -prior_net {I_ips_ddr_top/u_ddrphy_top/ddrphy_ioclk_gate [1]} successfully.

Routing started.
Enter timing driven router mode.
Route thread size: 3
Building routing graph takes 1.04 sec.
Setup STE netlist take 206 msec.
Dispose control chain take 182 msec.
Collect const net info take 66 msec.
Total nets for routing: 8270.
Total loads for routing: 37730.
Direct connect net size: 1128
Build all design net take 287 msec.
Worst slack is 2394, TNS before route is 0.
Processing design graph takes 0.76 sec.
Delay table total memory: 0.46088982 MB
Route graph total memory: 81.62889671 MB
Route design total memory: 9.80878448 MB
Unrouted nets 0 at the end of iteration 0, which take 0.00 sec.
Global Routing step 1 take 0.01 sec.
Global Routing step 2 take 0.00 sec.
Global Routing step 3 take 0.00 sec.
Global routing takes 0.01 sec.
Total 8268 subnets.
Unrouted clock nets at iteration 0 (0.049 sec): 0
Total route nets size: 8222
Pre route takes 2.127 sec
Unrouted general nets at iteration 2 (MT total route time: 1.383 sec): 7231(overused: 47498)
Unrouted general nets at iteration 3 (MT total route time: 1.215 sec): 6476(overused: 37634)
Unrouted general nets at iteration 4 (MT total route time: 0.984 sec): 5407(overused: 24744)
Unrouted general nets at iteration 5 (MT total route time: 0.763 sec): 4669(overused: 17303)
Unrouted general nets at iteration 6 (MT total route time: 0.637 sec): 4031(overused: 13152)
Unrouted general nets at iteration 7 (MT total route time: 0.474 sec): 3180(overused: 10590)
Unrouted general nets at iteration 8 (MT total route time: 0.436 sec): 2528(overused: 7866)
Unrouted general nets at iteration 9 (MT total route time: 0.380 sec): 1968(overused: 5842)
Unrouted general nets at iteration 10 (MT total route time: 0.314 sec): 1612(overused: 4510)
Unrouted general nets at iteration 11 (MT total route time: 0.299 sec): 1350(overused: 3706)
Unrouted general nets at iteration 12 (MT total route time: 0.262 sec): 1155(overused: 2888)
Unrouted general nets at iteration 13 (MT total route time: 0.221 sec): 986(overused: 2511)
Unrouted general nets at iteration 14 (MT total route time: 0.189 sec): 878(overused: 2250)
Unrouted general nets at iteration 15 (MT total route time: 0.166 sec): 848(overused: 2023)
Unrouted general nets at iteration 16 (MT total route time: 0.160 sec): 796(overused: 2035)
Unrouted general nets at iteration 17 (MT total route time: 0.158 sec): 692(overused: 1593)
Unrouted general nets at iteration 18 (MT total route time: 0.131 sec): 624(overused: 1390)
Unrouted general nets at iteration 19 (MT total route time: 0.151 sec): 588(overused: 1389)
Unrouted general nets at iteration 20 (MT total route time: 0.128 sec): 531(overused: 1196)
Unrouted general nets at iteration 21 (MT total route time: 0.105 sec): 426(overused: 885)
Unrouted general nets at iteration 22 (MT total route time: 0.081 sec): 383(overused: 764)
Unrouted general nets at iteration 23 (MT total route time: 0.097 sec): 412(overused: 847)
Unrouted general nets at iteration 24 (MT total route time: 0.077 sec): 348(overused: 674)
Unrouted general nets at iteration 25 (MT total route time: 0.079 sec): 319(overused: 628)
Unrouted general nets at iteration 26 (MT total route time: 0.069 sec): 307(overused: 570)
Unrouted general nets at iteration 27 (MT total route time: 0.064 sec): 308(overused: 598)
Unrouted general nets at iteration 28 (MT total route time: 0.063 sec): 246(overused: 438)
Unrouted general nets at iteration 29 (MT total route time: 0.052 sec): 222(overused: 414)
Unrouted general nets at iteration 30 (MT total route time: 0.054 sec): 214(overused: 398)
Unrouted general nets at iteration 31 (MT total route time: 0.050 sec): 188(overused: 370)
Unrouted general nets at iteration 32 (MT total route time: 0.045 sec): 182(overused: 332)
Unrouted general nets at iteration 33 (MT total route time: 0.044 sec): 149(overused: 281)
Unrouted general nets at iteration 34 (MT total route time: 0.038 sec): 176(overused: 352)
Unrouted general nets at iteration 35 (MT total route time: 0.052 sec): 185(overused: 338)
Unrouted general nets at iteration 36 (MT total route time: 0.046 sec): 164(overused: 329)
Unrouted general nets at iteration 37 (MT total route time: 0.044 sec): 161(overused: 265)
Unrouted general nets at iteration 38 (MT total route time: 0.037 sec): 125(overused: 203)
Unrouted general nets at iteration 39 (MT total route time: 0.031 sec): 113(overused: 198)
Unrouted general nets at iteration 40 (MT total route time: 0.029 sec): 70(overused: 120)
Unrouted general nets at iteration 41 (MT total route time: 0.021 sec): 57(overused: 94)
Unrouted general nets at iteration 42 (MT total route time: 0.024 sec): 46(overused: 74)
Unrouted general nets at iteration 43 (MT total route time: 0.019 sec): 42(overused: 56)
Unrouted general nets at iteration 44 (MT total route time: 0.017 sec): 25(overused: 45)
Unrouted general nets at iteration 45 (MT total route time: 0.014 sec): 22(overused: 36)
Unrouted general nets at iteration 46 (MT total route time: 0.013 sec): 17(overused: 30)
Unrouted general nets at iteration 47 (MT total route time: 0.015 sec): 12(overused: 14)
Unrouted general nets at iteration 48 (MT total route time: 0.012 sec): 11(overused: 24)
Unrouted general nets at iteration 49 (MT total route time: 0.012 sec): 7(overused: 20)
Unrouted general nets at iteration 50 (MT total route time: 0.009 sec): 2(overused: 4)
Unrouted general nets at iteration 51 (MT total route time: 0.010 sec): 3(overused: 6)
Unrouted general nets at iteration 52 (MT total route time: 0.011 sec): 2(overused: 2)
Unrouted general nets at iteration 53 (MT total route time: 0.011 sec): 2(overused: 2)
Unrouted general nets at iteration 54 (MT total route time: 0.010 sec): 0(overused: 0)
----General net take 0.009 sec(route net take 0.003 sec, inc cost take 0.006 sec, iter times: 1)
----const net route take 0.023 sec
Unrouted nets at iteration 55 (0.034 sec): 0
Detailed routing takes 16.44 sec.
Fix violation Finished.
No hold violation.
Hold Violation Fix in router takes 5.53 sec.
Sort Original Nets take 0.005 sec
Build solution node for device pins which were mapped to more than one design pin take 0.014 sec
Total net: 8270, route succeed net: 8270
Generate routing result take 0.014 sec
Handle PERMUX permutation take 0.350 sec
Handle const net take 0.015 sec
Handle route through take 0.010 sec
Handle loads' routing node take 0.057 sec
Used SRB routing arc is 85022.
Finish routing takes 0.55 sec.
Total routing takes 25.77 sec.

C: Place-2025: The VCCIO 3.3 in BANK BANKL4 is incompatible.

Device Utilization Summary :
+------------------------------------------------------------------------------+
| Logic Utilization           | Used     | Available     | Utilization(%)     
+------------------------------------------------------------------------------+
| Use of ADC                  | 1        | 1             | 100                
| Use of ANALOG               | 0        | 1             | 0                  
| Use of APM                  | 0        | 120           | 0                  
| Use of BKCL                 | 3        | 5             | 60                 
| Use of CCS                  | 1        | 1             | 100                
| Use of CLMA                 | 1300     | 6575          | 20                 
|   FF                        | 4122     | 52600         | 8                  
|   LUT                       | 3986     | 26300         | 16                 
|   LUT-FF pairs              | 1890     | 26300         | 8                  
| Use of CLMS                 | 396      | 2375          | 17                 
|   FF                        | 1205     | 19000         | 7                  
|   LUT                       | 1096     | 9500          | 12                 
|   LUT-FF pairs              | 513      | 9500          | 6                  
|   Distributed RAM           | 39       | 9500          | 1                  
| Use of DDRPHY_CPD           | 1        | 10            | 10                 
| Use of DDRPHY_IOCLK_DIV     | 2        | 5             | 40                 
| Use of DDR_PHY              | 5        | 20            | 25                 
| Use of DRM                  | 0        | 85            | 0                  
| Use of GCLK_INBUF_SYN       | 0        | 20            | 0                  
| Use of GPLL                 | 2        | 5             | 40                 
| Use of GSEB                 | 0        | 123           | 0                  
| Use of HARD0                | 598      | 5850          | 11                 
| Use of HCKB                 | 13       | 72            | 19                 
|  HCKB dataused              | 0        | 72            | 0                  
| Use of HCKMUX_TEST          | 0        | 6             | 0                  
| Use of HSSTLP               | 0        | 1             | 0                  
| Use of IO                   | 55       | 250           | 22                 
|   IOBD                      | 27       | 120           | 23                 
|   IOBS                      | 28       | 130           | 22                 
| Use of IOCKB                | 0        | 20            | 0                  
| Use of IOCKMUX_TEST         | 0        | 5             | 0                  
| Use of IOLHR                | 55       | 250           | 22                 
| Use of KEYRAM               | 0        | 1             | 0                  
| Use of MFG_TEST             | 0        | 1             | 0                  
| Use of MRCKB                | 1        | 10            | 10                 
| Use of MRCKMUX_TEST         | 0        | 5             | 0                  
| Use of MRPOSTMUX_TEST       | 0        | 5             | 0                  
| Use of PCIE                 | 0        | 1             | 0                  
| Use of PCKMUX_TEST          | 0        | 10            | 0                  
| Use of PLLMRMUX_TEST        | 0        | 5             | 0                  
| Use of PLLREFMUX_TEST       | 0        | 5             | 0                  
| Use of PPLL                 | 2        | 5             | 40                 
| Use of PREGMUXC_TEST        | 0        | 3             | 0                  
| Use of PREGMUXLR_TEST       | 0        | 5             | 0                  
| Use of RCKB                 | 3        | 20            | 15                 
|  RCKB dataused              | 0        | 20            | 0                  
| Use of RCKMUX_TEST          | 0        | 5             | 0                  
| Use of SCANCHAIN            | 0        | 1             | 0                  
| Use of SCKMUX_TEST          | 0        | 10            | 0                  
| Use of SFB                  | 0        | 1375          | 0                  
| Use of SPAD                 | 0        | 4             | 0                  
| Use of TSERDES              | 10       | 40            | 25                 
| Use of USCM                 | 3        | 32            | 10                 
|  USCM dataused              | 0        | 32            | 0                  
| Use of USCMMUX_TEST         | 0        | 32            | 0                  
+------------------------------------------------------------------------------+

Finished routing.
Design 'test_ddr' has been placed and routed successfully.
Saving design to DB.
Finished placement and routing.
Action pnr: Real time elapsed is 0h:0m:59s
Action pnr: CPU time elapsed is 0h:0m:17s
Action pnr: Process CPU time elapsed is 0h:0m:24s
Current time: Wed Jan  8 10:14:55 2025
Action pnr: Peak memory pool usage is 1,896 MB
