#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: D:\DMYWdownloadsoftware\PDS\pango\PDS_2022.2-SP6.4\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.26100
#Hostname: LAPTOP-E50OTCNR
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Wed Nov  5 00:24:05 2025
Compiling verification operator library.
Compiling common defs.
Compiling prim grid devices.
Compiling gate devices.
Compiling gate operators.
Building architecture model.
Loading device packaging model.
Reading design from pnr DB.
Start Report Post-PnR timing.
W: Flow-4065: The port cmos2_pclk has a sdc constraint, but it do not connect to any pin.
Constructing timing graph ...
Timing graph has been constructed successfully
C: STA-3003: The timing arc 'I0->L6' of 'gopLUT6L5' are non_unate, The timing analyser will assume pos_unate for these arcs in clock propgation. Clock: 'cmos1_pclk_16bit'  from 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/I0' to: 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/L6'
C: STA-3003: The timing arc 'I0->L6' of 'gopLUT6L5' are non_unate, The timing analyser will assume pos_unate for these arcs in clock propgation. Clock: 'cmos1_pclk_16bit'  from 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/I0' to: 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/L6'
C: STA-3003: The timing arc 'I0->L6' of 'gopLUT6L5' are non_unate, The timing analyser will assume pos_unate for these arcs in clock propgation. Clock: 'cmos1_pclk_16bit'  from 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/I0' to: 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/L6'
C: STA-3003: The timing arc 'I0->L6' of 'gopLUT6L5' are non_unate, The timing analyser will assume pos_unate for these arcs in clock propgation. Clock: 'cmos1_pclk_16bit'  from 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/I0' to: 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/L6'
C: STA-3003: The timing arc 'I0->L6' of 'gopLUT6L5' are non_unate, The timing analyser will assume pos_unate for these arcs in clock propgation. Clock: 'cmos1_pclk_16bit'  from 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/I0' to: 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/L6'
C: STA-3003: The timing arc 'I0->L6' of 'gopLUT6L5' are non_unate, The timing analyser will assume pos_unate for these arcs in clock propgation. Clock: 'cmos1_pclk_16bit'  from 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/I0' to: 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/L6'
C: STA-3003: The timing arc 'I0->L6' of 'gopLUT6L5' are non_unate, The timing analyser will assume pos_unate for these arcs in clock propgation. Clock: 'cmos1_pclk_16bit'  from 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/I0' to: 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/L6'
C: STA-3003: The timing arc 'I0->L6' of 'gopLUT6L5' are non_unate, The timing analyser will assume pos_unate for these arcs in clock propgation. Clock: 'cmos1_pclk_16bit'  from 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/I0' to: 'cmos1_8_16bit/N8/gateop_LUT6DL5_perm/L6'
C: STA-3009: The clock cmos2_pclk is not connected to any clock endpoints,it will be treated as a normal port or pin.
C: STA-3009: The clock cmos2_pclk_16bit is not connected to any clock endpoints,it will be treated as a normal port or pin.
W: STA-3011: Clock pin 'coms1_reg_config/config_step_reg[0]/opit_0/CLK' (gopQ.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/config_step_reg[1]/opit_0_srl/CLK' (gopSRL2.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/reg_conf_done_reg/opit_0_L5Q_perm/CLK' (gopLUT6L5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/reg_data/gopdrm_18k/CLKA' (gopDRM18K.CLKA) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/reg_data/gopdrm_18k/CLKB' (gopDRM18K.CLKB) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/reg_index[0]/opit_0_L6Q_LUT6DQL5Q_perm/CLK' (gopLUT6QL5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/reg_index[3]/opit_0_L6QL5Q_perm/CLK' (gopLUT6QL5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/reg_index[4]/opit_0_L6QL5Q1_perm/CLK' (gopLUT6QL5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/reg_index[5]/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/reg_index[7]/opit_0_L6QL5Q_perm/CLK' (gopLUT6QL5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/start/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/u1/cyc_count[1]/opit_0_L5Q_perm/CLK' (gopLUT6L5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/u1/cyc_count[2]/opit_0_L5Q_perm/CLK' (gopLUT6L5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/u1/cyc_count[3]/opit_0_L6QL5Q_perm/CLK' (gopLUT6QL5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/u1/cyc_count[4]/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/u1/cyc_count[5]/opit_0_L5Q_perm/CLK' (gopLUT6L5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/u1/reg_sdat/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/u1/sclk/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms1_reg_config/u1/tr_end/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/config_step_reg[0]/opit_0/CLK' (gopQ.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/config_step_reg[1]/opit_0_srl/CLK' (gopSRL2.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/reg_conf_done_reg/opit_0_L6Q_LUT6DQL5_perm/CLK' (gopLUT6QL5.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/reg_data/gopdrm_18k/CLKA' (gopDRM18K.CLKA) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/reg_data/gopdrm_18k/CLKB' (gopDRM18K.CLKB) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/reg_index[3]/opit_0_L6QL5Q_perm/CLK' (gopLUT6QL5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/reg_index[4]/opit_0_L6QL5Q1_perm/CLK' (gopLUT6QL5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/reg_index[5]/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/reg_index[7]/opit_0_L6QL5Q_perm/CLK' (gopLUT6QL5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/reg_index[8]/opit_0_L6Q_LUT6DQL5Q_perm/CLK' (gopLUT6QL5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/start/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/u1/cyc_count[0]/opit_0_L5Q_perm/CLK' (gopLUT6L5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/u1/cyc_count[1]/opit_0_L5Q_perm/CLK' (gopLUT6L5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/u1/cyc_count[3]/opit_0_L6QL5Q_perm/CLK' (gopLUT6QL5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/u1/cyc_count[4]/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/u1/cyc_count[5]/opit_0_L5Q_perm/CLK' (gopLUT6L5Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/u1/reg_sdat/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/u1/sclk/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: STA-3011: Clock pin 'coms2_reg_config/u1/tr_end/opit_0_L6Q_perm/CLK' (gopLUT6Q.CLK) has no clock, timing propagation is disabled at the pin.
W: Timing-4087: Port 'cmos1_scl' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'cmos1_sda' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'cmos2_scl' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'cmos2_sda' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[0]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[0]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[1]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[1]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[2]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[2]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[3]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[3]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[4]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[4]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[5]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[5]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[6]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[6]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[7]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[7]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[8]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[8]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[9]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[9]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[10]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[10]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[11]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[11]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[12]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[12]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[13]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[13]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[14]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[14]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'ddr_mem_dq[15]' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'ddr_mem_dq[15]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_dqs[0]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_dqs[1]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_dqs_n[0]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_dqs_n[1]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'i2c_sda' is not constrained, it is treated as combinational input.
W: Timing-4087: Port 'i2c_sda' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'cmos1_reset' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'cmos2_reset' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[0]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[1]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[2]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[3]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[4]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[5]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[6]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[7]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[8]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[9]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[10]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[11]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[12]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[13]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_a[14]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_ba[0]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_ba[1]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_ba[2]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_cas_n' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_ck' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_ck_n' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_cke' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_cs_n' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_dm[0]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_dm[1]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_odt' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_ras_n' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_rst_n' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ddr_mem_we_n' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'pclk_led' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'ref_led' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'txn[0]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'txn[1]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'txp[0]' is not constrained, it is treated as combinational output.
W: Timing-4087: Port 'txp[1]' is not constrained, it is treated as combinational output.
W: Timing-4086: Port 'button_rst_n' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'cmos1_data[0]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'cmos1_data[1]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'cmos1_data[2]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'cmos1_data[3]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'cmos1_data[4]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'cmos1_data[5]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'cmos1_data[6]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'cmos1_data[7]' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'cmos1_href' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'cmos1_vsync' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'i2c_scl' is not constrained, it is treated as combinational input.
W: Timing-4086: Port 'perst_n' is not constrained, it is treated as combinational input.
Report timing is finished successfully.
Action report_timing: Real time elapsed is 0h:0m:21s
Action report_timing: CPU time elapsed is 0h:0m:19s
Action report_timing: Process CPU time elapsed is 0h:0m:20s
Current time: Wed Nov  5 00:24:24 2025
Action report_timing: Peak memory pool usage is 1,393 MB
