IP Generator (Version 2022.2-SP6.4 build 146967)
Check out license ...
Start generating at 2025-11-04 23:30
Instance: ddr3 (D:\DMYWdownloadsoftware\PDS\project\project_bs\PCIe_IIc_SXT_DDR_3_LC_TP_4_2\pcie_dma_test\my_code_file\DDR3\ip_core\ddr3\ddr3.idf)
IP: Pango DDR3 Interface (1.10)
Part: Logos2-PG2L50H-FBG484--6
Create directory 'example_design' ...
Create directory 'example_design\bench' ...
Create directory 'example_design\rtl' ...
Create directory 'example_design\rtl\adc' ...
Create directory 'example_design\rtl\uart_ctrl_32bit' ...
Create directory 'example_design\bench\ddr2_tb' ...
Create directory 'example_design\bench\ddr3_tb' ...
Create directory 'example_design\bench\lpddr_tb' ...
Create directory 'example_design\bench\mem' ...
Copy 'example_design\rtl\axi_bist_top_v1_0.v' to 'example_design\rtl' ...
Copy 'example_design\rtl\prbs15_64bit_v1_0.v' to 'example_design\rtl' ...
Copy 'example_design\rtl\prbs31_128bit_v1_0.v' to 'example_design\rtl' ...
Copy 'example_design\rtl\test_ddr.v.xml' to 'example_design\rtl' ...
Copy 'example_design\rtl\test_main_ctrl_v1_0.v' to 'example_design\rtl' ...
Copy 'example_design\rtl\test_rd_ctrl_v1_0.v' to 'example_design\rtl' ...
Copy 'example_design\rtl\test_wr_ctrl_v1_0.v' to 'example_design\rtl' ...
Copy 'example_design\rtl\uart_rd_lock.v' to 'example_design\rtl' ...
Copy 'example_design\rtl\adc\adc.v' to 'example_design\rtl\adc\' ...
Copy 'example_design\rtl\adc\adc_ctrl.v' to 'example_design\rtl\adc\' ...
Copy 'example_design\rtl\uart_ctrl_32bit\ips2l_clk_gen_32bit.v' to 'example_design\rtl\uart_ctrl_32bit\' ...
Copy 'example_design\rtl\uart_ctrl_32bit\ips2l_cmd_parser_32bit.v' to 'example_design\rtl\uart_ctrl_32bit\' ...
Copy 'example_design\rtl\uart_ctrl_32bit\ips2l_seu_rs232_intf.v' to 'example_design\rtl\uart_ctrl_32bit\' ...
Copy 'example_design\rtl\uart_ctrl_32bit\ips2l_seu_uart_rx.v' to 'example_design\rtl\uart_ctrl_32bit\' ...
Copy 'example_design\rtl\uart_ctrl_32bit\ips2l_seu_uart_tx.v' to 'example_design\rtl\uart_ctrl_32bit\' ...
Copy 'example_design\rtl\uart_ctrl_32bit\ips2l_uart_ctrl_32bit.v' to 'example_design\rtl\uart_ctrl_32bit\' ...
Copy 'example_design\rtl\uart_ctrl_32bit\ips2l_uart_ctrl_top_32bit.v' to 'example_design\rtl\uart_ctrl_32bit\' ...
Copy 'example_design\rtl\uart_ctrl_32bit\ips2l_ver_ctrl_32bit.v' to 'example_design\rtl\uart_ctrl_32bit\' ...
Copy 'example_design\bench\ddr3_tb\ddr3_test_top_tb.v.xml' to 'example_design\bench\ddr3_tb' ...
Copy 'example_design\bench\ddr2_tb\ddr2_test_top_tb.v.xml' to 'example_design\bench\ddr2_tb' ...
Copy 'example_design\bench\lpddr_tb\lpddr_test_top_tb.v.xml' to 'example_design\bench\lpddr_tb' ...
Copy 'example_design\bench\mem\2048Mb_mobile_ddr_parameters.vh' to 'example_design\bench\mem' ...
Copy 'example_design\bench\mem\ddr2.v' to 'example_design\bench\mem' ...
Copy 'example_design\bench\mem\ddr2_parameters.vh' to 'example_design\bench\mem' ...
Copy 'example_design\bench\mem\ddr3.v' to 'example_design\bench\mem' ...
Copy 'example_design\bench\mem\ddr3_parameters.vh' to 'example_design\bench\mem' ...
Copy 'example_design\bench\mem\mobile_ddr.v' to 'example_design\bench\mem' ...
Create directory 'pnr' ...
Copy 'pnr\100h_ddr2_324_x32.fdc' to 'pnr' ...
Copy 'pnr\100h_ddr2_484_x32.fdc' to 'pnr' ...
Copy 'pnr\100h_ddr2_676_x72.fdc' to 'pnr' ...
Copy 'pnr\100h_ddr3_324_x32.fdc' to 'pnr' ...
Copy 'pnr\100h_ddr3_484_x32.fdc' to 'pnr' ...
Copy 'pnr\100h_ddr3_676_x72.fdc' to 'pnr' ...
Copy 'pnr\100h_lpddr_324_x32.fdc' to 'pnr' ...
Copy 'pnr\100h_lpddr_484_x32.fdc' to 'pnr' ...
Copy 'pnr\100h_lpddr_676_x72.fdc' to 'pnr' ...
Copy 'pnr\200h_ddr2_1156_x72.fdc' to 'pnr' ...
Copy 'pnr\200h_ddr2_484_x32.fdc' to 'pnr' ...
Copy 'pnr\200h_ddr2_676_x72.fdc' to 'pnr' ...
Copy 'pnr\200h_ddr3_1156_x72.fdc' to 'pnr' ...
Copy 'pnr\200h_ddr3_484_x32.fdc' to 'pnr' ...
Copy 'pnr\200h_ddr3_676_x72.fdc' to 'pnr' ...
Copy 'pnr\200h_lpddr_1156_x72.fdc' to 'pnr' ...
Copy 'pnr\200h_lpddr_484_x32.fdc' to 'pnr' ...
Copy 'pnr\200h_lpddr_676_x72.fdc' to 'pnr' ...
Copy 'pnr\25h_ddr2_325_x32.fdc' to 'pnr' ...
Copy 'pnr\25h_ddr3_325_x32.fdc' to 'pnr' ...
Copy 'pnr\25h_lpddr_325_x32.fdc' to 'pnr' ...
Copy 'pnr\390h_ddr2_676_x72.fdc' to 'pnr' ...
Copy 'pnr\390h_ddr2_900_x72.fdc' to 'pnr' ...
Copy 'pnr\390h_ddr3_676_x72.fdc' to 'pnr' ...
Copy 'pnr\390h_ddr3_900_x72.fdc' to 'pnr' ...
Copy 'pnr\390h_lpddr_676_x72.fdc' to 'pnr' ...
Copy 'pnr\390h_lpddr_900_x72.fdc' to 'pnr' ...
Copy 'pnr\50h_ddr2_324_x32.fdc' to 'pnr' ...
Copy 'pnr\50h_ddr2_484_x32.fdc' to 'pnr' ...
Copy 'pnr\50h_ddr3_324_x32.fdc' to 'pnr' ...
Copy 'pnr\50h_ddr3_484_x32.fdc' to 'pnr' ...
Copy 'pnr\50h_lpddr_324_x32.fdc' to 'pnr' ...
Copy 'pnr\50h_lpddr_484_x32.fdc' to 'pnr' ...
Copy 'pnr\ctrl_phy_ip_filelist.f' to 'pnr' ...
Copy 'pnr\phy_only_ip_filelist.f' to 'pnr' ...
Copy 'pnr\prj_filelist.f' to 'pnr' ...
Create directory 'rtl' ...
Copy 'rtl\ips2l_rst_sync_v1_3.vp' to 'rtl' ...
Create directory 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_calib_mux_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_calib_top_v1_10.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_control_path_adj_v1_10.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_cpd_ctrl_v1_3.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_cpd_lock_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_data_slice_v1_10.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_data_slice_wrcal_v1_10.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_data_slice_wrlvl_v1_10.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_dfi_v1_3.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_dll_update_ctrl_v1_3.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_dqs_rddata_align_v1_10.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_drift_ctrl_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_eyecal_v1_5.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_gate_update_ctrl_v1_3.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_gatecal_v1_10.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_gpll_phase_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_info_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_init_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_main_ctrl_v1_10.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_rdcal_v1_10.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_reset_ctrl_v1_3.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_rst_debounce_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_slice_rddata_align_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_slice_top_v1_10_wrapper.v.xml' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_training_ctrl_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_upcal_v1_0.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_wdata_path_adj_v1_10.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_wrcal_v1_7.vp' to 'rtl\ddrphy' ...
Copy 'rtl\ddrphy\ips2l_ddrphy_wrlvl_v1_0.vp' to 'rtl\ddrphy' ...
Create directory 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_apb_cross_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_calib_delay_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_cfg_apb_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_dcd_bm_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_dcd_rowaddr_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_dcd_sm_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_dcd_top_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_dcp_back_ctrl_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_dcp_buf_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_dcp_out_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_dcp_top_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_dfi_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_lp_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_mrs_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_prefetch_fifo_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_rdatapath_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_reg_fifo2_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_ui_axi_v1_2a.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_wdatapath_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_wdp_align_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_wdp_dcp_v1_2.vp' to 'rtl\mcdq_ctrl' ...
Copy 'rtl\mcdq_ctrl\ips2l_mcdq_wrapper_v1_2b.vp' to 'rtl\mcdq_ctrl' ...
Create directory 'rtl\mcdq_ctrl\syn_mod' ...
Copy 'rtl\mcdq_ctrl\syn_mod\ips2l_mcdq_com_timing_v1_2.vp' to 'rtl\mcdq_ctrl\syn_mod' ...
Copy 'rtl\mcdq_ctrl\syn_mod\ips2l_mcdq_tfaw_timing_v1_2.vp' to 'rtl\mcdq_ctrl\syn_mod' ...
Copy 'rtl\mcdq_ctrl\syn_mod\ips2l_mcdq_tfaw_v1_2.vp' to 'rtl\mcdq_ctrl\syn_mod' ...
Copy 'rtl\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_act2wr_pass_v1_2.vp' to 'rtl\mcdq_ctrl\syn_mod' ...
Copy 'rtl\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_act_pass_v1_2.vp' to 'rtl\mcdq_ctrl\syn_mod' ...
Copy 'rtl\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_pre_pass_v1_2.vp' to 'rtl\mcdq_ctrl\syn_mod' ...
Copy 'rtl\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_rd_pass_v1_2.vp' to 'rtl\mcdq_ctrl\syn_mod' ...
Copy 'rtl\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_ref_pass_v1_2.vp' to 'rtl\mcdq_ctrl\syn_mod' ...
Copy 'rtl\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_wr_pass_v1_2.vp' to 'rtl\mcdq_ctrl\syn_mod' ...
Copy 'rtl\mcdq_ctrl\syn_mod\ips2l_mcdq_trc_timing_v1_2.vp' to 'rtl\mcdq_ctrl\syn_mod' ...
Create directory 'rtl\mcdq_ctrl\distributed_fifo' ...
Copy 'rtl\mcdq_ctrl\distributed_fifo\ips2l_distributed_fifo_v1_0.vp' to 'rtl\mcdq_ctrl\distributed_fifo' ...
Create directory 'rtl\mcdq_ctrl\distributed_fifo\rtl' ...
Copy 'rtl\mcdq_ctrl\distributed_fifo\rtl\ips2l_distributed_fifo_ctr_v1_0.vp' to 'rtl\mcdq_ctrl\distributed_fifo\rtl' ...
Copy 'rtl\mcdq_ctrl\distributed_fifo\rtl\ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp' to 'rtl\mcdq_ctrl\distributed_fifo\rtl' ...
Copy 'rtl\mcdq_ctrl\distributed_fifo\rtl\ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp' to 'rtl\mcdq_ctrl\distributed_fifo\rtl' ...
Create directory 'rtl\pll' ...
Copy 'rtl\pll\ips2l_ddrphy_gpll_v1_3.vp' to 'rtl\pll' ...
Copy 'rtl\pll\ips2l_ddrphy_ppll_v1_0.vp' to 'rtl\pll' ...
Create directory 'sim' ...
Create directory 'sim\modelsim' ...
Create directory 'sim\vcs' ...
Create directory 'sim_lib' ...
Create directory 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_apb_cross_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_calib_delay_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_cfg_apb_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_dcd_bm_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_dcd_rowaddr_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_dcd_sm_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_dcd_top_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_dcp_back_ctrl_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_dcp_buf_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_dcp_out_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_dcp_top_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_dfi_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_lp_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_mrs_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_prefetch_fifo_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_rdatapath_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_reg_fifo2_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_ui_axi_v1_2a.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_wdatapath_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_wdp_align_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_wdp_dcp_v1_2.vp' to 'sim_lib\mcdq_ctrl' ...
Copy 'sim_lib\mcdq_ctrl\ips2l_mcdq_wrapper_v1_2b.vp' to 'sim_lib\mcdq_ctrl' ...
Create directory 'sim_lib\mcdq_ctrl\syn_mod' ...
Copy 'sim_lib\mcdq_ctrl\syn_mod\ips2l_mcdq_com_timing_v1_2.vp' to 'sim_lib\mcdq_ctrl\syn_mod' ...
Copy 'sim_lib\mcdq_ctrl\syn_mod\ips2l_mcdq_tfaw_timing_v1_2.vp' to 'sim_lib\mcdq_ctrl\syn_mod' ...
Copy 'sim_lib\mcdq_ctrl\syn_mod\ips2l_mcdq_tfaw_v1_2.vp' to 'sim_lib\mcdq_ctrl\syn_mod' ...
Copy 'sim_lib\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_act2wr_pass_v1_2.vp' to 'sim_lib\mcdq_ctrl\syn_mod' ...
Copy 'sim_lib\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_act_pass_v1_2.vp' to 'sim_lib\mcdq_ctrl\syn_mod' ...
Copy 'sim_lib\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_pre_pass_v1_2.vp' to 'sim_lib\mcdq_ctrl\syn_mod' ...
Copy 'sim_lib\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_rd_pass_v1_2.vp' to 'sim_lib\mcdq_ctrl\syn_mod' ...
Copy 'sim_lib\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_ref_pass_v1_2.vp' to 'sim_lib\mcdq_ctrl\syn_mod' ...
Copy 'sim_lib\mcdq_ctrl\syn_mod\ips2l_mcdq_timing_wr_pass_v1_2.vp' to 'sim_lib\mcdq_ctrl\syn_mod' ...
Copy 'sim_lib\mcdq_ctrl\syn_mod\ips2l_mcdq_trc_timing_v1_2.vp' to 'sim_lib\mcdq_ctrl\syn_mod' ...
Create directory 'sim_lib\mcdq_ctrl\distributed_fifo' ...
Copy 'sim_lib\mcdq_ctrl\distributed_fifo\ips2l_distributed_fifo_v1_0.vp' to 'sim_lib\mcdq_ctrl\distributed_fifo' ...
Create directory 'sim_lib\mcdq_ctrl\distributed_fifo\rtl' ...
Copy 'sim_lib\mcdq_ctrl\distributed_fifo\rtl\ips2l_distributed_fifo_ctr_v1_0.vp' to 'sim_lib\mcdq_ctrl\distributed_fifo\rtl' ...
Copy 'sim_lib\mcdq_ctrl\distributed_fifo\rtl\ips2l_distributed_fifo_v1_0_distributed_fifo_v1_0.vp' to 'sim_lib\mcdq_ctrl\distributed_fifo\rtl' ...
Copy 'sim_lib\mcdq_ctrl\distributed_fifo\rtl\ips2l_distributed_sdpram_v1_0_distributed_fifo_v1_0.vp' to 'sim_lib\mcdq_ctrl\distributed_fifo\rtl' ...
Create directory 'sim_lib\ddrphy' ...
Create directory 'sim_lib\pll' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_calib_mux_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_calib_top_v1_10.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_control_path_adj_v1_10.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_cpd_ctrl_v1_3.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_cpd_lock_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_data_slice_dqs_gate_cal_v1_10.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_data_slice_v1_10.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_data_slice_wrcal_v1_10.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_data_slice_wrlvl_v1_10.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_dfi_v1_3.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_dll_update_ctrl_v1_3.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_dqs_gate_coarse_cal_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_dqs_rddata_align_v1_10.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_dqsi_rdel_cal_v1_3.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_drift_ctrl_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_eyecal_v1_5.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_gate_update_ctrl_v1_3.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_gatecal_v1_10.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_gpll_phase_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_info_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_init_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_main_ctrl_v1_10.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_rdcal_v1_10.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_reset_ctrl_v1_3.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_rst_clk_phase_adj_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_rst_debounce_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_slice_rddata_align_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_training_ctrl_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_upcal_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_wdata_path_adj_v1_10.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_wrcal_v1_7.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_wrlvl_v1_0.vp' to 'sim_lib\ddrphy' ...
Copy 'sim_lib\pll\ips2l_ddrphy_gpll_v1_3.vp' to 'sim_lib\pll' ...
Copy 'sim_lib\pll\ips2l_ddrphy_ppll_v1_0.vp' to 'sim_lib\pll' ...
Copy 'sim_lib\ips2l_rst_sync_v1_3.vp' to 'sim_lib' ...
Copy 'sim_lib\ddrphy\ips2l_ddrphy_slice_top_v1_10_wrapper.v.xml' to 'sim_lib\ddrphy' ...
Compile file 'sim_lib\ddrphy\ips2l_ddrphy_slice_top_v1_10_wrapper.v.xml' to 'sim_lib\ddrphy\ddr3_slice_top_v1_10.v' ...
Copy 'ips2l_ddr_top_v1_10_wrapper.v.xml' ...
Copy 'ips2l_ddrphy_top_v1_10_wrapper.v.xml' ...
Copy 'readme.txt' ...
Compile file 'ips2l_ddr_top_v1_10_wrapper.v.xml' to 'ddr3.v' ...
Found top module 'ddr3' in file 'ddr3.v'.
Compile file 'ips2l_ddrphy_top_v1_10_wrapper.v.xml' to 'ddr3_ddrphy_top.v' ...
Compile file 'rtl\ddrphy\ips2l_ddrphy_slice_top_v1_10_wrapper.v.xml' to 'rtl\ddrphy\ddr3_slice_top_v1_10.v' ...
Compile file 'example_design\rtl\test_ddr.v.xml' to 'example_design\rtl\test_ddr.v' ...
Compile file 'example_design\bench\ddr3_tb\ddr3_test_top_tb.v.xml' to 'example_design\bench\ddr3_tb\ddr3_test_top_tb.v' ...
Compile file 'example_design\bench\ddr2_tb\ddr2_test_top_tb.v.xml' to 'example_design\bench\ddr2_tb\ddr2_test_top_tb.v' ...
Compile file 'example_design\bench\lpddr_tb\lpddr_test_top_tb.v.xml' to 'example_design\bench\lpddr_tb\lpddr_test_top_tb.v' ...
Run file 'createFiles.tcl' ...
Create template file 'ddr3_tmpl.v' ...
Create template file 'ddr3_tmpl.vhdl' ...
Done: 0 error(s), 0 warning(s)
