<?xml version="1.0" encoding="UTF-8"?>
<ip_inst>
    <header>
        <vendor>Pango</vendor>
        <id>04100205</id>
        <display_name>DRM Based FIFO</display_name>
        <name>28nm DRM Based FIFO</name>
        <version>1.10</version>
        <instance>SXT1_FIFO</instance>
        <family>Logos2</family>
        <device>PG2L50H</device>
        <package>FBG484</package>
        <speedgrade>-6</speedgrade>
        <generator version="2022.2-SP6.4" build="146967">IP Compiler</generator>
    </header>
    <param_list>
        <param>
            <name>RD_OCE_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>RD_CLK_OR_POL_INV</name>
            <value>false</value>
        </param>
        <param>
            <name>ASYN_FIFO_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>RST_VAL</name>
            <value>0</value>
        </param>
        <param>
            <name>CAS_MODE</name>
            <value>36K</value>
        </param>
        <param>
            <name>WR_DEPTH_WIDTH</name>
            <value>10</value>
        </param>
        <param>
            <name>BE_WIDTH</name>
            <value>1</value>
        </param>
        <param>
            <name>RD_BE_WIDTH</name>
            <value>1</value>
        </param>
        <param>
            <name>FIFO_TYPE</name>
            <value>ASYN_FIFO</value>
        </param>
        <param>
            <name>OUTPUT_REG</name>
            <value>false</value>
        </param>
        <param>
            <name>BYTE_SIZE</name>
            <value>8</value>
        </param>
        <param>
            <name>ALMOST_EMPTY_NUM</name>
            <value>4</value>
        </param>
        <param>
            <name>WR_BYTE_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>RD_DEPTH_WIDTH</name>
            <value>10</value>
        </param>
        <param>
            <name>CAS_MODE_SEL</name>
            <value>AUTO</value>
        </param>
        <param>
            <name>RD_DATA_WIDTH</name>
            <value>128</value>
        </param>
        <param>
            <name>POWER_OPT</name>
            <value>false</value>
        </param>
        <param>
            <name>WR_DATA_WIDTH</name>
            <value>128</value>
        </param>
        <param>
            <name>RESET_TYPE</name>
            <value>ASYNC</value>
        </param>
        <param>
            <name>FULL_WL_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>FAB_REG</name>
            <value>false</value>
        </param>
        <param>
            <name>RST_VAL_EN</name>
            <value>false</value>
        </param>
        <param>
            <name>SAMEWIDTH_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>EMPTY_WL_EN</name>
            <value>true</value>
        </param>
        <param>
            <name>ALMOST_FULL_NUM</name>
            <value>1020</value>
        </param>
    </param_list>
    <pin_list>
        <pin>
            <name>wr_clk</name>
            <text>wr_clk</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>wr_rst</name>
            <text>wr_rst</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>wr_en</name>
            <text>wr_en</text>
            <dir>input</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>wr_data</name>
            <text>wr_data</text>
            <dir>input</dir>
            <pos>left</pos>
            <msb>127</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>wr_full</name>
            <text>wr_full</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>wr_water_level</name>
            <text>wr_water_level</text>
            <dir>output</dir>
            <pos>left</pos>
            <msb>10</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>almost_full</name>
            <text>almost_full</text>
            <dir>output</dir>
            <pos>left</pos>
        </pin>
        <pin>
            <name>rd_clk</name>
            <text>rd_clk</text>
            <dir>input</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>rd_rst</name>
            <text>rd_rst</text>
            <dir>input</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>rd_en</name>
            <text>rd_en</text>
            <dir>input</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>rd_data</name>
            <text>rd_data</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>127</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>rd_empty</name>
            <text>rd_empty</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
        <pin>
            <name>rd_water_level</name>
            <text>rd_water_level</text>
            <dir>output</dir>
            <pos>right</pos>
            <msb>10</msb>
            <lsb>0</lsb>
        </pin>
        <pin>
            <name>almost_empty</name>
            <text>almost_empty</text>
            <dir>output</dir>
            <pos>right</pos>
        </pin>
    </pin_list>
    <synthesis>
        <script><![CDATA[set_option -vlog_std v2001]]></script>
        <script><![CDATA[set_option -disable_io_insertion 1]]></script>
    </synthesis>
    <file_list>
        <output>
            <file pathname="generate.log" format="log" description="Generate Log"/>
            <file pathname="SXT1_FIFO_tb.v" format="verilog" description="Compiled File"/>
            <file pathname="SXT1_FIFO_tmpl.v" format="verilog" description="Instantiation Template"/>
            <file pathname="SXT1_FIFO_tmpl.vhdl" format="vhdl" description="Instantiation Template"/>
        </output>
        <source>
            <file pathname="rtl/ipm2l_fifo_ctrl_v1_1_SXT1_FIFO.v"/>
            <file pathname="rtl/ipm2l_sdpram_v1_10_SXT1_FIFO.v"/>
            <file pathname="rtl/ipm2l_fifo_v1_10_SXT1_FIFO.v"/>
            <file pathname="SXT1_FIFO.v"/>
        </source>
    </file_list>
</ip_inst>
