#Build: Fabric Compiler 2022.2-SP6.4, Build 146967, Jan 31 01:39 2024
#Install: E:\PDS_FPGA\PDS_2022.2-SP6.4\bin
#Application name: pds_shell.exe
#OS: Windows 10 10.0.26100
#Hostname: 傻额宁儿
Generated by Fabric Compiler (version 2022.2-SP6.4 build 146967) at Fri Nov  7 01:33:39 2025
# pvf -action compile

pvf_reg_constant coms2_reg_config/clock_20k_cnt[15] 0

pvf_reg_constant coms2_reg_config/clock_20k_cnt[14] 0

pvf_reg_constant coms2_reg_config/clock_20k_cnt[13] 0

pvf_reg_constant coms2_reg_config/clock_20k_cnt[12] 0

pvf_reg_constant coms2_reg_config/clock_20k_cnt[11] 0

pvf_reg_constant coms1_reg_config/clock_20k_cnt[15] 0

pvf_reg_constant coms1_reg_config/clock_20k_cnt[14] 0

pvf_reg_constant coms1_reg_config/clock_20k_cnt[13] 0

pvf_reg_constant coms1_reg_config/clock_20k_cnt[12] 0

pvf_reg_constant coms1_reg_config/clock_20k_cnt[11] 0

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_gate_update_ctrl/update_start -deleted u_ddr3/u_ddrphy_top/ddrphy_gate_update_ctrl/ddrphy_update_req

pvf_reg_constant u_ddr3/u_ips_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/cnt[6] 0

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cs_n

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_we_n

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/genblk2.init_cas_n -deleted u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/genblk2.init_ras_n

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[3] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_wrcal/delay_cnt[2] 0

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dqs_gate_comp_done -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dqs_gate_comp_en_r

pvf_reg_merging  -survived u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dqs_gate_comp_done -deleted u_ddr3/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].ddrphy_data_slice/ddrphy_data_slice_dqs_gate_cal/ddrphy_gatecal/dqs_gate_comp_en_r

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_controller/o_user_define_data_flag 0

pvf_reg_constant u_ddr3/u_ddrphy_top/u_ips2l_ddrphy_rst_clk_phase_adj/rst_clk_adj_dir 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_gate_update_ctrl/update_start 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_cpld_tx_ctrl/o_axis_slave0_tuser 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tuser 0

pvf_reg_constant u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mwr_tx_ctrl/o_axis_slave2_tuser 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_eyecal/eyecal_ba[0] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[2] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[1] 0

pvf_reg_constant u_ddr3/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrcal/wrcal_ba[0] 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[0].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[1].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[2].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN 0

pvf_reg_constant u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_rx_rst_mcrsw/genblk1[3].hsst_rst4mcrsw_rx_init/rx_rst_initfsm_multi_sw_lane/P_RX_PLL_RSTN 0

pvf_reg_merging  -survived bar0_wr_en -deleted ddr_fifo_rd_en_pcie

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_cs_n -deleted u_ddr3/u_ips_ddrc_top/mcdq_dfi/mrs2dfi_ras_n

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cs_n[1] -deleted u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_ras_n[1]

pvf_reg_merging  -survived u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_cs_n[0] -deleted u_ddr3/u_ips_ddrc_top/mcdq_lp/lp_ras_n[0]

pvf_reg_merging  -survived u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tlast -deleted u_ips2l_pcie_dma/u_ips2l_pcie_dma_tx_top/u_ips2l_pcie_dma_mrd_tx_ctrl/o_axis_slave1_tvld

pvf_reg_merging  -survived u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_PMA_LANE_PD -deleted u_ips2l_pcie_wrap/U_IPS2L_PCIE_TOP/U_IPS2L_HSSTLP_PCIE_SOFT_PHY/hsst_pciex4_rst/hsst_tx_rst_mcrsw/tx_rst_fsm_multi_sw_lane/P_PMA_TX_PD
