Project Name: General-Purpose I/O (GPIO) Core

Description

The GPIO IP core is user-programmable general-purpose I/O controller. Its use is to implement functions that are not implemented with the dedicated controllers in a system and require simple input and/or output software controlled signals.

Features

The following lists the main features of GPIO IP core:

- Number of general-purpose I/O signals is user selectable and can be in range from 1 to 32. For more I/Os several GPIO cores can be used in parallel.
- All general-purpose I/O signals can be bi-directional (external bi-directional I/O cells are required in this case).
- All general-purpose I/O signals can be three-stated or open-drain enabled (external three-state or open-drain I/O cells are required in this case).
- General-purpose I/O signals programmed as inputs can cause interrupt to the CPU.
- General-purpose I/O signals programmed as inputs can be registered at raising edge of system clock or at user programmed edge of external clock.
- All general-purpose I/O signals are programmed as inputs at hardware reset.
- Auxiliary inputs to GPIO core to bypass outputs from RGPIO_OUT register.
- Alternative input reference clock signal from external interface.
- WISHBONE SoC Interconnection Rev. B compliant interface

More information about the WISHBONE SoC and a full specification can be found here.

For further information, questions and general discussions related to the GPIO core, please visit the Cores Mailing list. To subscribe to the Cores mailing list go to the Mailing-Lists page and select cores from the pull down menu at the end of the page. Enter your email address and click "Do it!"

Status

- Verilog RTL and verification suite under development
- The Specification is complete: gpio_spec.pdf (about 2.3MB)

Downloading

To get a snapshot of the latest release, please go to CVSget (from main OpenCores web page) and enter "gpio" as Module Name (without quotes). This will create a gzip'ed tar file of the entire GPIO core.

Author / Maintainer

Damjan Lampret
lampret@opencores.org_NOSPAM

Feel free to send me comments, suggestions and bug reports.

Change Log

- 22/3/2001 DL Preliminary Spec available
- 21/3/2001 DL Initial web page