This is the complete example for the wb_dma UVM testbench in UVM with a legacy Testbench.
The Directory structure is a bit different from all the others in this example.

the BENCH directory contains all the testbenches. There is verilog directory which contains the original
verilog testbenches. 
The common directory contains the common code
the wb_dma_uvm directory contains the uvm testbench. Structure is identical to the other directories here. 

The other directories were part of the wb_dma_uvm offerring

To run these tests, 
change to the sim directory and type "make"


